 Hello everyone, welcome to lecture on test bench for encoders. At the end of this session, students will be able to build the test bench for encoder and also verify the previously designed VHDL code using this test bench. Now before starting with the actual session, let's pause the video and think about what is a encoder. If you remember, if you saw the previous video lectures, we have designed the VHDL modules for different combinational circuits and sequential circuits and in that we covered full adder, half adder, encoder, decoder and multiplexer, demultiplexer. So if you remember that the encoder is nothing but which is converts one form to the other form or one format to other format or which maps inputs to the different outputs format. So you can see over here, this is a 8 bit inputs are there and which are mapped with the 3 bit output. So it is called 8s to 3 encoder. So it encodes your inputs into the outputs. So 8 bit inputs are there, 8 bit inputs are encoded in 3 bit output. So how this mapping is done or how this mapping is performed, you can see the disk table. So whatever the 8 bits are there in an input, so this combination is mapped with this combination of 3 bit output. You can see over here. So whenever the i of 0th bit is 1, in that case you are having all the 0s at the output line. And whenever the i of 1 bit is 1, your z of 0 bit is 1. As your every 1 bit from the input is 1, according that you are having different combination in the output side. Means that your 8 bits are encoded in the form of 3 bits on the output side. So that is why it is called as 8s to 3 encoder. Now before starting the test bench writing, you must know about the VHDL code or module for this 8s to 3 encoder. So let us have a look at that. VHDL module for 8s to 3 encoder. Every module has 3 different parts or important parts you can say. First is a library declaration. So library is included, library IEEE and from that we are using the package that is STD logic 1164. So and from that package we are using all. So that is why use IEEE dot STD logic 1164 dot all. So this is the library declaration part. Second important part of your VHDL module is the entity declaration. So entity is written. Now this one is the 8s to 3 encoder. So mention name mention for the entity is encoder 83. In the entity it describes the inputs and outputs of your device or system. Now in this case your encoder is having 8 inputs and 3 outputs. So I is the input, I mode is in, type is a STD logic vector, 8 bits are there. So that is why it is mentioned 7 down to 0, Z is the output. So Z mode is out, type is again a STD logic vector because 3 bit output is there. So that is why it is mentioned 2 down to 0. Once you done with the inputs and outputs mentioning you have to end the entity. So end entity name is there right. Third important part of your USDM module is a final part that is the architecture writing. So architecture, architecture name of for which entity you are writing the architecture that entity name supposed to be there here we are writing for encoder 8s to 3. So that name supposed to be same right is then your architecture begin. After that you have to write the behavior of your 8s to 3 encoder how your circuit is going to functional right. So that can be summarized with the help of table whatever we created in a previous slide. So that can be written with the help of case statement using in this VHDL module. So that can be written in the inside the process. So we have to include the process, process in the bracket I, I is nothing but the sensitivity list you have to mention while writing the process. Sensitivity list is nothing but the list which affects the output of your system right. So in this case you are having only one signal which affects the output. So that is why I is there. Then your process begin right then case statement we have used. So case I is when I is having this value you can refer that table whatever we created in a previous slide. When I is having this value then Z is having this that is why we created the table. Similarly when I is having this combination second bit is 1 in that case Z is having 001. So this is how we can complete all the conditions once we done one more condition last is there when others other than this combination is there on the input side. In that case your output is having all Z that is high impedance right. Once you done with the case writing you have to end the case all the cases you are done you have to end the case after that you have to end the process so end process and you have to end the architecture, end architecture right. After this you can use the any simulator there are lots of simulator available in the market you can use the any simulator use this code complete perform the simulation you can verify the with the help of your forms. If you run the simulation you will get the output like this right. So this is the input 8 bit input and below are the individual bit wise is shown and this is the 3 bit output and again it is shown bit wise right. Now when the input is all you means undefined in that case your last statement whatever you return in a case statement when others your Z equals output equals to Z Z Z so that is why it is shown Z Z Z right. Then according if any condition satisfy from the cases given according that the output is changes see it is 0000 then 001 then 1100 then all 1. If according any having bits 1 and this satisfy the from the case statement you are having according that output generated. So this is how you can verify the VHDL module now let us go for the test bench writing of that right. So again for the test bench writing you have 3 important parts library declaration same as you done for the VHDL module then entity writing but here the entity supposed to be empty nothing to write in that entity you just mention the entity name and end the entity that is it. So that is why it is entity entity name and end entity name right. Then architecture part is there architecture name of for which entity you are writing the architecture that entity name supposed to there is then component declaration done. So component declaration means for which you are writing the test bench for that module you have to use as a component. So we are using writing a test bench for encoder 8s to 3 so we are using that entity as a component so same entity mention as a component. So only the difference is what instead of entity keyword we have used keyword component. So component declaration is done same port supposed to be there as you created in a entity right. After that end component then you have to mention the inputs and outputs inputs i is input which is as taken as a signal again type of vector ranges 7 down to 0 8 bit input signal is there. Then z is output again type is a vector that is 2 down to 0 because 3 bit output signal is there right. After that we have taken one constant called period of 100 nanoseconds right you can take this one or you can directly write 100 nanosecond while using it right instead of calling period right. Then we have to start the architecture so architecture begin begin keyword is there so whatever the statement written between this architecture line and begin keyword all are the declarative part right. Then you have to write the component instantiation right so for that you have to follow the syntax that is a label then component name component name is there here encoder 8 3 then port map keyword you have to use and inside the brackets you have to perform the mapping that is i is mapped with the i this i is mapped with this i and z is mapped with this z right. Once you done with the component instantiation you have to write the process. So process then process begin keyword now here you have to write all the cases what you have for which you are writing test bench first case let us see when i equals to i am assigning with the value i with this and we have waited for period here instead of period you can directly write 100 nanosecond right. Then assert statement is used assert statement is used to check the Boolean condition and if that condition fails then it generates the report statement whatever it is mentioned if that condition fails i am saying it is not similar to the if loop if condition whenever the condition is true then and then it comes in a loop in if here it is opposite if that condition fails in assert then Boolean condition fails then it comes in to generate the report statement right. So if that condition fails it generates the report statement which are of different types the report statement can be of note type can be of warning type can be of error type. So this one is of error type right and if that condition true Boolean condition true it go for the next case. So this is one case i equals to this value z is supposed to be this right if that is true go for the next. So similarly this is a one case you have to complete the remaining cases. So these are the remaining cases you can go through that whenever i is having this value z is supposed to be this if that fails it generates this statement report this statement. So this is how the assert statement is used right for all cases right once you done with the all the combinations of your input right then you have to end the process right and then you have to end the architecture. So end architecture. So this is how you can write the test bench same way you can verify with the help of simulation. So if you run this code in a simulator and if you perform the simulation you will get the output something like this. So i is the input of 8 bit say it is the output of 3 bit right for each input combination it will show the output and if you you can verify this with the your previous VHDL module code and you can say that my code is working properly right. If it is having any error in that case the waveform will be different right. So these are the references thank you.