 Currently, there are two main approaches to scaling high-K gate dielectric layers, using higher K materials with greater than 20% K value, or employing interfacial layer, IL, scavenging techniques. Law-based higher K materials have shown aggressive equivalent oxide thickness, EU, scaling down to 0.5 nanometers, but they are only suitable for n-type field effect transistors, FETs. Further exploration for p-type FET-compatible higher K materials is necessary. Meanwhile, Illinois scavenging has been found to be a promising approach to extend HF-based high-K dielectrics to future nodes. Remote IL scavenging techniques allow for EOT scaling below 0.5 nanometers, while maintaining mobility and EWF control. Short-channel performance improvements are possible with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling, zero IL, is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime, and LT, 0.5 Nm, will. This article was authored by Takashi Ando.