 Hi, I'm Drew Festini and I wanted to talk today about two of my favorite things, which are Linux and open source hardware. I'm an open source hardware designer at a PCB manufacturing service in the U.S. called OSH Park. I'm also on the board of directors of the Beaglebutterdorg foundation. You may have heard of the Beaglebone. It's a small open source hardware Linux computer. I'm also on the board of directors of the open source hardware association. And we have an open source hardware certification program that you can find out more about on our website. And I'm also a risk 5 ambassador. So there's many risk 5 virtual meetups around the world, including Munich and Bay Area. You can find out more of them at risk5.org slash local. And coming up in a few days, we have the risk 5 summit, which is the big annual risk 5 event. There'll be lots of interesting talks about risk 5, so I recommend checking it out. So I mentioned open source hardware. So that's hardware whose design is made publicly available so that anyone can study, modify, distribute, make and sell the design or hardware based on their design. So in the context of electronics, we're talking about the documentation would be required is the schematics and the board layout and the editable source files from the CAD software. So not just the PDF or an image file. And ideally those not required is to use open source software. So for example, key CAD. And this lowers the barriers of entry for people that want to participate in the project. You can use proprietary CAD software though in the, no, it can still be considered open source hardware. So it's not required, but it is best practice to use open source software if you can. Then also the build materials or the parts list also not a strict requirement, but it's best practice for all the components to be available from distributors in low quantity. And the point of all this is to lower the barriers of entry to enable collaborative development, which is kind of the theme behind open source hardware. I talked more about open source hardware, including different licensing options in a talk I gave last year and you can watch that video online. So risk 5 is an instruction set or an ISA. This is the interface between the hardware and the software. For example, let's say we have a C++ program. Well that gets compiled into instructions for a microprocessor to execute. But how does the compiler know what instructions the CPU understands? This is defined by the instructions that architecture. So the ISA is a standard, a set of rules that define the tasks the processor can perform. Proprietary ISAs like X86 from Intel and ARM, which you'd find in your laptop and desktop and most servers in ARM, which you'd find in your smartphones. These are proprietary instruction sets and they require commercial licensing. However, risk 5 is a free and open instruction set. So this started about 10 years ago by computer architecture researchers at UC Berkeley. The professor that started the project has a great talk called instruction sets want to be free that I recommend checking out. Some people, sometimes people ask me, what's the V? So this is actually the Roman numeral 5 because it's the fifth risk instruction set to come out of Berkeley. And why do I see it as free and open? This is because the specifications for risk 5 are licensed under as creative commons attribution, which is considered an open source license. So what's different about risk 5? Because there's many instruction sets out there. Well, it's a simple and clean slate design kind of built upon the many decades of knowledge and skills that the team at Berkeley had developed. It's far smaller than commercial instruction sets and has a clear separation between unprivileged and privileged instruction set. It also avoids baking in micro architecture or technology dependent features into the instruction set. There's a separation there between the standard, the specification, and how it's implemented. So risk 5 is also modular, so it's both extensible and you can specialize it for different use cases. That's because there's a small standard base with multiple standard extensions that makes it suitable for everything from a tiny microcontroller to a big supercomputer. And it's stable, which means that the base and standard extensions are frozen now. So they'll always be supported by a risk 5 processor. And then additions are made via optional extensions. For example, there is a vector processing extension that's being developed right now in a hypervisor extension that's being developed. But these don't require new versions of the base ISA. They're just optional extensions on top of that. So there's four base integer ISAs. There's RV32I, which is 32-bit, and it's less than 50 instructions. So relatively easy for people to implement in a design. And then there's RV32E, which is just a reduced register account to make it better for implementing small microcontrollers. There's RV64I, and this is 64-bit, and this will be the one that we're most interested in terms of risk 5 processors that can run Linux. There's even 128-bit. So this is kind of feature-proof to make sure there's enough address space when nonvolatile RAM capacities increase potentially. It also is beneficial for security as well to have a larger address space. So there's risk 5 standard extensions that I mentioned, and those include M for multiplying divide, A for atomic, FD and Q for different precisions of floating point, and then there's G, which is general purpose. So this is equivalent to several of those existing ones, the integer, multiply, atomic, float, and double float. And then there's C, which is compressed instructions to conserve memory and cache. So this is similar to ARM thumb. And as I said before, these standard extensions have been ratified, so they will be supported forever as long as the processor conforms to the risk 5 instruction set. And then Linux distros like Debian and Fedora are targeting RV64GC, so if you're looking at processor designs and you're interested in ones that will be supported by Linux distros potentially, then you want to be looking for RV64GC. And here's the base instruction sets along with the standard extensions on a reference card, which is kind of nice to see it all there. If you were to compare this to something like Intel, you can see that it's much easier to wrap your mind around risk 5. If you want to learn more about risk 5, including the different base instruction sets and the standard extensions and also some new ones that are being worked on like Vector and Hypervisor, check out the risk 5 reader. It's only about 100 pages. I really recommend giving it a quick read through. It's available in several different languages as well. So risk 5 international now controls the specifications that were originally developed at Berkeley and you can find this at risk5.org. So it's a non-profit organization. It's always growing. It's probably over 700 members now from 50 different countries, including companies and universities and more. You as an individual can become a member free of cost. It's also free of cost for nonprofits to join as well. And there's also a YouTube channel for risk 5 international that has hundreds of talks from over the years. That's one of the ways that I've learned a lot about risk 5, so I highly recommend checking that out. In companies planned to ship billions of devices with risk 5 cores, NVIDIA is actually already shipping risk 5 cores for system management in its GPU products. And Western Digital has announced that they're planning to swap out the controllers and all their different storage devices with risk 5 based designs, which will be a large number of devices out there in the world with risk 5 cores in them. So one of the reasons to choose risk 5 is to avoid instruction set licensing costs and royalty fees. This includes the legal costs and also I've heard mentioned the long delays. So to license something like an instruction set, it can be kind of complex and it can take a long time. And the researchers at Berkeley mentioned that was one of the reasons why they decided to just go ahead and design their own instruction set. But more importantly than just saving on licensing and royalty fees, it gives you the freedom to choose your own micro architecture implementation. So the way in which you implement the instruction set is up to you. Whereas with ARM, only a few companies like Apple and Samsung and Qualcomm have architecture licenses that allow them to do their own custom implementations. So everyone else is pretty much just licensing existing cores from ARM. And with risk 5, you also have the freedom to leverage existing open source implementations. So for the context of Linux, there's Rocket and Boom from Berkeley and there's also Ariane from the ETH Zurich pulp theme that are capable of running Linux. One of the things that's really important when it comes to an instruction set is software support. And risk 5 already has a well supported software ecosystem. If you click on that link there, it'll take you to a GitHub where risk 5 international keeps a list of support for all the different operating systems and languages and tool chains and it's evolving very well. Kemaraj gave a talk back at the embedded Linux conference North America about the state of software development tool service 5. So if you're wondering about like particular language you're interested in or library, definitely check that out and you can find the latest information. But overall it's pretty well supported. So most of the things that you would expect to be there are there now. So risk 5 international is based in Switzerland. So back at the beginning of this year, previously there had been an organization called Risk 5 Foundation that was US based. And back at the beginning of this year, risk 5 international was incorporated in Switzerland to alleviate any concerns from the membership over US politics. Also the European Union, India and Pakistan have national risk 5 processor design initiatives and I think we're seeing here a desire for sovereign control over technology and to avoid back doors from other nations that might be in search and pieces of technology. There's also strong interest from chip makers in China. So if you remember back in 2019 US companies were banned from doing business with Huawei and I think there's concern there of like what company might be next. ARM ultimately was deemed to be a UK origin technology so they could continue to do business with Huawei, but how long will that last and how will the NVIDIA acquisition impact that? So sometimes they hear the question, is risk 5 an open source processor? So that's not quite right. Risk 5 is a set of specifications under an open license, under an open source license. And risk 5 implementation is going to both be open source and proprietary. So just because this risk 5 doesn't mean that it's an open source implementation of a processor, it just means it's implementing the open risk 5 specification. And that's important because open specifications make open source implementations possible. An open ISA like risk 5 enables there to be open source processor implementations. So with risk 5 we can have fully open source chips if the people that are doing the implementations choose to do that. So risk 5 has what's called a privilege architecture and this is used for running a full operating system like Linux. So there's three different privilege modes. There's machine load or M mode where you find the boot loader and firmware. There's supervisor mode or S mode where you find the operating system kernel like Linux. And then finally there's user mode or U mode where you have the applications running. There's also a hypervisor spec that's in draft that also gives a HMS which is a modified S mode. So there's five boot flows, similar to what you might have seen on ARM systems, but there is a piece in the middle there which is called open SPI which you may not be familiar with. Also before I proceed, just one thing I wanted to point out which confused me for a little while when I was learning risk 5 terminology is you'll see the term heart and this stands for hardware threat of execution. So you can think of it as a core or a schedulable mutant. So I mentioned SPI. So this is stands for the supervisor binary interface and this is something that's specific to risk 5. So it's the calling convention between the supervisor mode or S mode OS and the supervisor execution environment or SEE that's running in machine mode. And this allows the supervisor mode software to be written so that's portable to all different risk 5 limitations. So this is important. So the architectural support in the Linux kernel for risk 5 is not written for a specific risk 5 chip. It's written to the risk 5 architecture and SPI access the abstraction there that makes that possible. And this came out of the Unix class platform spec working group. It's chaired by Ariel Elstone and recently it changed the name to the risk 5 platform spec working group. The idea there was to be broader than just Linux. Open SPI is an open source implementation of that SPI standard. And the idea here is that it has layers of implementation. So at the core there's the SPI library that implements that implements SPI. And then there's platform specific libraries for different risk 5 SoCs. And then there's even complete platform specific reference for different SoCs and boards. So this provides runtime, provides a runtime in end mode. So typically it's used in the boot stage following the ROM loader and it provides support for several reference platforms and generic drivers that are included for M mode to be able to operate. And that's the machine mode, the bare metal kind of mode. Something that's been standard for a long time in the Intel world is UEFI and with the advent of ARM V8 and 64-bit ARM also saw that it started to be adopted for ARM servers. And UEFI support is there for risk 5. So support in the Linux kernel is coming in 5.10. There's already implementations for UEFI and risk 5 with Uboot and Tiano Core ADK2. And Grub 2 can be used as a UEFI payload on risk 5. Risk 5 is also well supported in QEMU. So if you don't have any hardware and you can actually run either full 64-bit or 32-bit risk 5 Linux in QEMU. And if you click on that link there, there's a nice tutorial that'll get you going with running risk 5 Linux on your PC or laptop. So risk 5 has been supported in the Linux kernel since the initial port by Palmer back in Linux 4.15. If you're interested in following along subscribe to the mailing list there. And there's also the archives available on lore. And a great talk that was given earlier this year was from Bjorn Topol at Munich risk 5 meetup, one of the virtual meetups that I had mentioned earlier. And it's called what's missing in risk 5 Linux and how you can help. And one of the things that he mentioned in the talk was risk 5 support in Linux is a great way to learn the nitty gritty details of the kernel. And it's also a fun friendly and still pretty small community, the risk 5 architecture support in comparison to Linux as a whole, which is thousands of developers. And one of the things from his talk that he mentioned was there's this script in the Linux source that you can run, and it shows you all the architecture features that are still need to work on. So if you're interested in digging in, these are the things that are still necessary to do for the architecture. And some of the recent work for debug and tracing security risk 5 support in Linux kernel includes the EPPF jet. So this is important because EPPF is bringing lots of exciting capabilities to Linux and it's important for that to be supported on risk 5. Also K probes and K rep probes will enable BPF trace and make perf much more usable. And those are very powerful tools. There's also KGB and KDB support being worked on, which is useful for debugging. Also K exact and K dump and relocatable kernel work is being done, which will help address space layout randomization implementation and also the syscaller fuzzing bot or the syscaller, which does fuzzing to discover security vulnerabilities now supports risk 5 as well. The recent work on hardware support includes KVM. So KVM is basically complete now. It's just waiting on the ratification of that hypervisor specification. There's also support being worked on for the vector I say, which is also a draft extension that has going to be pretty exciting capabilities in terms of doing heavier processing in risk 5. There's also SV48 support, which is for page for level page table for up to 64 terabytes of physical RAM, which should hopefully be enough for a while. And there's also work to unify enuma implementations for bigger systems. There's also work being done to support some of the more recent risk 5 dev boards. So Linux distros, Fedora has a port which aims to provide the full Fedora experience on risk 5. And they're at the point now where you can either run Fedora risk 5 under QEMU, like on your desktop or on a server. And it's also supported on one of the risk 5 development boards that's currently available. We'll talk a little more about the different dev boards that are out there in a minute. And if you want to, you can go through the installation instructions and start running risk 5 Fedora on your PC using QEMU. There's also a port of Debian to risk 5, and Debian is known for having the massive source packages of like 20,000. And the good news is over 95% of those packages are building right now for risk 5. And you can see there on that graph, the top gray line is a risk 5. And if you don't need a full general Linux distro, there's also support for risk 5 and open embedded in Yachto project through the meta risk 5 layer. There's also support in build route as well. And if you want to go through, there's a great tutorial from Michael at Boo Land of how to build an embedded Linux system from scratch in 40 minutes using build route. So what about actual chips? So we talked about how there's great QEMU support, but we want to actually run on real hardware. So sci-fi is a startup founded by some of the people from that Berkeley team. And back in 2018, they debuted the FU540, which was the first risk 5 system on chip that could run Linux. It had four 64 bit cores that were intended for running Linux and also a lower power core for doing system management tasks. It has 64 bit DDR4 interface, gigabit ethernet, kind of the standard peripherals you have, unfortunately not USB. And along with that, they announced back in 2018 and came out with the first Linux-capable risk 5 dev board called the sci-fi freedom unleashed. And this is what you saw back on the Fedora slide. None of the other things that's neat is the actual board design for it is open source hardware. So it was quite high performance compared to FPGAs, which is one of the other alternatives. The FU540 SoC is clock, it's gonna be 10 times or more faster than the soft cores. You know, the other thing I wanted to note here was sometimes you'll hear the term ASIC and that usually is referring to a system on chip that has a hard processor core constructed by silicon fabrication instead of a soft core that's loaded into an FPGA. And with an ASIC, we can run the clock much, much faster than an FPGA. However, this board was too expensive for widespread adoption. It's sold for about $1,000 on crowd supply and it's not available anymore. You know, and the chip itself was never sold separately. And the reason for this is SyFive's core business is designing cores. It's not to build SOCs or dev boards. But one of, actually, so one of the nice things about this is if you get the expansion hardware, including a graphics card, you can actually run a full Fedora GNOME image on RIS5, which is neat to see. And one of SyFive's customers was Microchip and they came out recently with the PolarFire SOC. So this is similar to that SyFive U540, but it adds an FPGA. So it had like the SyFive SOC, it has four 64 bit cores that come on Linux. It has DDR interface. This one also has PCI Express and USB and Gigabit Ethernet. And the great thing about this too is that it's a full commercial product family. So it's available, it's gonna be available from distributors. And if you're wondering, I didn't realize Microchip made FPGAs. Well, this is because it's the formerly MicroSemi, which is now part of Microchip. And to debut this SOC, they came out with the PolarFire SOC dev board. This was announced back in July for $500, so half the cost of that SyFive Unleashed board. The pre-orders are now shipping and it'll be available soon from distributors. And this one has the RIS5 cores collected at 600 megahertz and it has the large FPGA fabric with 250,000 logic elements. It has two gigabytes of DDR memory and eight gigabytes of MMC flash. So it actually comes with Linux installed on it, which is nice. One of the other boards I wanted to mention that's using that PolarFire OSC is the Savvy board. And one of the neat things here is actually is designed to be able to be stacking. So if you wanna build a cluster of these boards, in addition, it has dual 10 gigabit fiber Ethernet. So the idea here I think pie for HPC sort of workloads. It also brings out PCI Express over Type-C connectors. But those boards are pretty expensive and might not be in your budget but you still wanna play around with RIS5. So I recommend checking out the Kendrick K210. It's a 400 megahertz dual core 64-bit core. It has eight megabytes of SRAM, which is a lot of SRAM, but it doesn't have DRAM. So it makes it a little bit difficult for us to run Linux. And you can find this in affordable dev boards from SIPED, such as the SIPED MaxBit, which I'm holding here, which is only $13. And at first it didn't seem like it was gonna be possible, but last year, some hackers like Damian Lamal and Christopher Helvig got it to work and added the support to Linux 5.8. There's also now support in UBOO for two of the boards from Sean Anderson. And part of the trick there was the chip does have an MMU, but it's not supported. It's at earlier draft spec and it's not supported in Linux. So they have to treat it as not having an MMU and just running Linux in M mode or machine mode. So the problem there is that the eight megabytes runs out very quickly. Since we don't have virtual memory, we can't do shared libraries. So we end up running out of memory very quickly. There's a few people we're working on, potentially ways to improve that. So there's a talk there link that you can check out if you wanna find out more about that. But it can run busybox. So the default instructions are you can use build root to build a root FS with busybox. And that's being in the process of being upstream. There's a great tutorial on CNX software that takes you through all the different steps you need to go through to build the kernel and build the root FS and load it up onto the board. Here's me running what was at the time, the mainline Linux on it. And for $13, I had to recommend getting one of these boards and checking it out and building the kernel and building root FS and putting on the board and just kind of getting familiar with some of the different tools. Now something that's gonna be more practical because it has DRAM is the PicoRio. So this is an open source project from RiosLab. And the goal here is to create a low cost Linux Kipple with RISC-5 platform. We were very excited back in September during the RISC-5 Global Summit that this was announced. They have three different phases that they wanna do of the system on chip. The first one of which is expected to start having samples by the end of this year. So that's pretty exciting. Sci-Fi also has followed up back in October with a new version of the dev board. So the new one's called Unmatched. And this one is on crowd supply right now for $665 and is expected to ship at the beginning of next year. This has a new SOC from Sci-Fi called the FU740 which is a much higher performance one with four 64-bit cores for running Linux and also one of those companion cores as well. One of the things you wanna notice is actually a mini ITX form factor so it's possible to build that kind of a proper PC out of this. And that's what was demoed at the conference recently. The board has eight gigabytes of DDR4 memory. It has four USB3 ports. It has gigabit ethernet. It also has a full PCI Express expansion slot and also has connectors, M2 connectors for things like NVMe SSDs and Wi-Fi Bluetooth modules. And the highest performance chip that's been announced so far is from TeeHead which is a subsidiary of Alibama. And this is called the Jean T910. It's a 16-core, or you might also see it referred to as C910. It's a 16-core, 2.5 gigahertz processor and this implements a draft version of the vector extension which is quite interesting and this is expected to debut next year. There's also Cypede announced just like two weeks ago that they're gonna be doing a board with a new all-winner SOC. So this actually is gonna be using another core, a smaller core designed by Alibaba TeeHead that's gonna be in an all-winner system on chip. So this is gonna be a single core up to one gigahertz but the board is gonna be less than $13 and they're saying it's gonna have at least 256 megabytes of DRAM so it'll be much more useful for running Linux than that Kendrite board. However, there aren't really that many options when it comes to hardware on Linux with RIS-5. So one of the other alternatives is to leverage FPGAs. So an FPGA is a field programmable Gatorade. So this is a chip that you can think of as being a sea or an ocean of different logic elements and these can be configured to be any sort of digital logic that we want them to be and if we have enough we can even configure it to be a processor core which we call a soft core. Now, when I learned FPGAs maybe about 15 years ago well we had to use proprietary tools from the FPGA vendor and one of the awesome things that's happened more recently is there's a strong open FPGA community that's been working on open source tool chains for certain FPGAs. So this started off with the Lattice Ice 40 with a project called Project Ice Storm by Claire Wolf. This is a smaller FPGA but it paved the way towards more capable FPGAs being supported such as the Lattice ECB-5 which is supported by Project Trellis and much more capable FPGAs are from Xilinx and Project Xray and Simboflow are working on also supporting the Xilinx Series 7 and that should be coming soon. One of the things you can think of these open FPGA tool chains is being kind of similar to GCC for FPGAs. The idea here is we can use free software to take our processor design and turn it into what's called the Bitstream to load into the FPGA using only open source software which is a pretty awesome thing that's happened in the last few years. So I mentioned that ECB-5 is supported by the open source FPGA tools and I wanted to talk about a project I was involved with last year. So as is the fashion now for many hardware hacking conferences is to have an electronic conference batch so that you can put graphics on and play games and have different sorts of interactions and we were at the Hackaday SuperCon last year and it was in this kind of large Game Boy form factor and it had a ECB-5 FPGA on it and it was designed to kind of run this graphics engine where people could develop games and put little animations on the color LCD of their name and things like that. But several of us at the conference thought, okay, that's nice, but what about running Linux? So we got together and we called ourselves Team Linux on Badge and we first tried the 16 megabytes of spying connected SRAM that was on the board, but that didn't work out but because it was a hardware hacking conference, one of the people, Jacob Creed, and he had already designed an add-in cartridge that had 32 megabytes of SD RAM which did prove to be sufficient for running Linux. And the design of the badge was a Game Boy thing so on the back there was a header to plug in these other circuit boards which were called cartridges so here's the 32 megabytes of SD RAM plugged into the badge on the back. And I mentioned soft cores earlier and I thought this was a neat way of kind of conceptualizing it at a, or visualizing it at a macro level. So this is an FPGA where the gates have been configured to serve as a soft processor core that can run Linux. And you can see that there's actually still space left there for just finding all our source of logic. Also, great follow, ICO, TC on Twitter if you're interested in open FPGA discussions. But specifically, how did we create the SOC that got loaded into that ECB-5 FPGA on the Hackaday badge to run Linux? Well, we used Python, which may be a bit surprising but Python has advantages over traditional hardware description languages like VHDL or Verilog. Many people are already familiar with Python versus HDLs. Like at the conference, most of us came from a software engineering background. And there are currently more, I would say there's currently more software developers and hardware designers so a nice way to get more people into doing chip level hardware design is to leverage a language like Python. Specifically, we used Nijen which is a Python framework that can automate chip design. It leverages the object oriented modular nature of Python and it produces Verilog code just like all the other tools so it can be used with existing chip design workflows even though we're coding in Python, it produces Verilog ultimately. There's a great talk about using Python for creating hardware to record open source conferences so I highly recommend checking that out if you're interested to learn some of the more background behind it. And that's from Tim Ansel and he was one of the people that was part of team badge on Linux at the Hackaday conference. So to give you an example of what Nijen looks like. So on the left there in VHDL, which is a traditional hard description language, this is I believe a D flip flop which is a simple digital circuit. On the right there, we have the same circuit, same digital logic defined there in Python. And to me, I think the right hand side actually is easier to understand. So you can see how it's leveraging kind of the object current in nature of Python to I think make it a little bit more understandable. And then based on my gen, there's a framework called Litex which allows us to build a full system of chip that can be loaded into the FPGA. And Litex has a collection of open cores for things like DRAM and Ethernet and PCI Express and SATA and more. So rather than having to write our own DRAM controller or own serial controller, we can just grab those open cores from the Litex project. And one of the things that brought all this together is a repository called Linux on Litex VexRiskV. So VexRiskV is a 32-bit Linux-capable RISC-5 implementation designed to be FPGA-friendly so it makes efficient use of the resources that are on FPGA. And it's written in a hard description language called Spinal which is based on Scala so also an object-oriented language that can kind of leverage software engineering skills. And it builds a system on chip using VexRisk as the core and the different Litex modules so we can pull on the ones we need like Lite DRAM or Lite Ethernet or SD card or PCI Express. And while you probably don't have the Hackaday badge, Linux on Litex VexRiskV actually supports a large number of FPGA dev boards and there's also a simulator if you don't have a dev board. So you can actually just go and clone that repository and run the build script and you'll be running Linux on a simulated RISC-5 core on your PC. And here is me with the badge connected to the serial port or the terminal emulator on my laptop so we can see the console on the badge and you can see there that what's happened here is we've used the open source tools to synthesize the Litex design into a bit stream that gets loaded onto the ECP-5 FPGA and then once the soft core is running inside the FPGA we then load the Linux kernel up onto it in a RudaFest and it boots into the Linux kernel and loads up busybox there which you can see in the window. So when the conference ended thought it was a good idea to upstream the work that we had done to get it running on the badge and while most people probably don't have the badge unless you're running a couple hundred people at the conference, this is a good example of how to add a new board to Linux on Litex VEX RISC. And to give you an idea of what the Python MeeGen syntax looks like this is what's called the pin constraints for the project and this is how it maps the pins on the FPGA to the different signals inside the design. Another good example of the extensibility of Litex and MeeGen is we had a DRAM chip on that cartridge that was not already supported in Lite DRAM. So we had to add that in. However, it just involved inheriting or extended in the SD RAM module to have a new class specific to our DRAM chip. So we just had to go and grab the different timings from the datasheet and plug them in there. So much simpler than having to write our own DRAM controller. We just leveraged the abject guarantee nature of Python to extend it with just the specifics to our hardware that was new. Another interesting thing that happened in this project was so we got it working, but it was booting really slow. It was taking almost five minutes. So I posted a GitHub issue and Litex is maintained by a user named enjoy digital who his actual name is Florent. Really nice guy and really responsive maintainer. So within a few hours, he had actually posted a patch that improved the performance by 10 times. So it was booting up in less than 30 seconds, which was pretty awesome to see. And also just to give you more of that Python flavor of what Mijian looks like. You can see here, this is the diff of part of the changes that he made to optimize Linux running on our VADGE. You know, because we had slow, I think just eight bit SD RAM memory accesses were pretty expensive. So in this case, the L2 cache data width was made larger. And this allowed us to have better performance. And you can see here in this diff, to me it's a little bit more understandable because in Python versus something like Verilog or VHDL. And you might have noticed there was an LCD. Well, Greg Davil is an awesome hardware hacker in Australia. And a few weeks after the conference, he was actually able to get the LCD working with the Lite video module. So now we don't have to have it connected to a PC to see Linux boot up on it and get to the busybox shell. So while you probably don't have the Hackaday badge and it's not available for sale, but there are other open source boards that have the ECB-5 FPGA. One of which is from a hacker space in Croatia called Radiona, it's the ULX 3S. It also has the 32 megabytes of SD RAM so we can run Linux on it. And it's sold on CrowdSupply and Mauser. And then another board I like a lot from Greg is the OrangeCrab. It has 120 megabytes of DDR memory so it's much more capable of running Linux. It has more space in a faster memory interface. And it's in this neat little form factor called Feather which you might have seen different Adafruit boards having. And you can get that on GroupGets. And if you're new to FPGA, starting with a larger FPGA like the ECB-5 with a soft core running Linux, it's probably not the best place to start. So I highly recommend checking out the FOMU. It's an open source board and there's a great online workshop that goes along with it. And it's a tiny little board. It fits inside the USB port so you can take it around in your laptop everywhere. And it has a great tutorial that takes you through the process of blinking LED first in MicroPython and then in Verilog and then finally in Mijen in Litex. If you don't have any hardware at all, I highly recommend Renode. It's an open source project started by AntMicro and it can simulate physical hardware systems including CPUs and peripherals and sensors and even wired or wireless nodes be network, a wired or wireless network with different nodes. And one of the great things about Renode is it has profile for different dev boards. So remember I mentioned that Sci-Fi, High-Five Unleashed Board, that Fedora project and a lot of people were using, well, it's expensive and hard to find. So that's, you know, if you don't have the board, you can still run the software that's supposed to run on it by using the profile in Renode. So here's an example of my laptop pretending to be the Sci-Fi Unleashed Board booting up the same software that runs on the board. Because it's a full modern laptop, it actually runs pretty fast. So it doesn't feel like it's some super slow simulator. Finally to leave you with, I thought this was a really interesting concept that I came across, the idea of a trustworthy self-hosted computer. So Gabriel Osamlo at Carnegie Mellon came up with this concept of, okay, now we have open source tools that we can use to load designs into an FPGA. And we have soft cores that come on inside of the FPGA that are capable of running Linux. And we can run those FPGA tools inside of Linux. So we can actually create a self-hosted system that can build itself, which is I think quite an interesting concept. I highly recommend checking out the talk that he has that I linked to. And here's just one of the slides from it, showing how he's using Litex along with Rocket, which is a core from Berkeley and how those all come together to be a self-hosted FPGA Linux computer. So thank you for watching. And I'm happy to take any questions online. And hopefully we'll be chatting throughout the rest of the conference. And I think the slack that we'll have for the different talks and topics. Thank you.