 अज़ी नशाला देखेंगे, उसको हम जो ता, सेकेट जो ता, उसको हम सुल्फ करेंगे, तुब कुईन मेखलसकी मेखद जो एकस्पैशन ता, अप फिर चेख करेंगे, के जो आप कान्सर है, नाजवेदर आनसर आता वो एक ही है, यान कुछ मुख्तलिफ है. तुब परच्ट की हम ने एकस्पैशन ली थी, जिसके चार इंपृट थे, तुछगाँट परच्ट थे, तुच को कैसे हम ने असके एकस्पैशन लिचनी बेसिक्ट तुछगे ज़ा तेबल वित फुर वेरिख़िएवल्ग, शुकस्टीन पस़बल अंपृट से, तीन तु नहीं ता पृट ली प्रप्टिशन से, वेरिख़े पुड़ा पूँट वेरिख़िएवल्ग, तो ताख थो कानवख नीप अपका काम करेगा, उसके भात कान अप मैप काम नहीं करेगा अपट आपकसिक्टःए ली परच्ट वेरिख़िएवल्ग, तो गिस के शार, क्य� illnessesues that means you have completed step one step two basically you have स्रन्द करे शुएत सेद की निस्झाव आप क्याईर हन और Kṛṣṇa, Śrīsāakra, Prabīda अद रसमों भी इखेया और और सेद आताशी एकठाव मैं तो बिवहा कियाँओ אתה इनल craving Hersama आप concentrated on �appedोड़िज़िंग स्वasti दिजों yeah just simply discontin सुःमा 그냥, दॉशाताएम ृम 144 नम AWSA नम्दम benim णबिश destroys या भी। नुथकर्फ विए प् sujet सुथ्रि लगता ऑा interf త్విర్వ్టాలి. లికిఇ లిక్తిర్న్ందిత్ల్లోవా. క్టికిమాలిక్ల్జి లికుందిర్స్ార్ణటిక్కికాసార్ాసంర్ది. సండికేకాన్తతిదాటాని塔 20這個 Army一个  Nepal . . . . . . . अ तुक्ये तू asc usable  Gaga Moo 2 1 2 2 3 1 105 15 5 10 10 5 School 11 22 23 25 26 Fast 37 38 36 37 खुहिनक Ausmahlack अब जोंग साथ बेग्धा वो ग 넘ीurallyे बैगाई नहीं रहीं बार नहीं शाथ plain खैश कँहिननät्नग ख unters वो चिमसका रहीं रहींक गदुन काई पू الجुरते। आप गुत बार मी खुन काई तो प्रग साथक अग, बी इबा़ � consciously बहुत ड Centers of the वर premiers वर दुश� पद दरा arises भी रउज़ बदा देए ап 없는 ऐट again बी फ्मा उस्कोईMon Mein villages of the comparisons between two terms in table three are represented in a separate table refer to as table for the first column less degree terms that have been compared together to eliminate common variables so terms 1 3 3, 5 & 7 form a single term eliminating variables C & D forming the product term A bar, B bar, A the comparison terms 1, 3 & 5, 7 are marked as used in table 3 similarly terms 1, 3, 17 & 19 form a single term eliminating variables A & D forming the product term B bar, C bar, E both these terms are marked as used in table 3. Product terms in table 4 are compared to eliminate common variables. No more comparisons of terms and elimination of variables takes place thus the prime implicants have been found. There are 3 prime implicants in table 4 and 5 prime implicants in table 3. The 8 prime implicants are represented by the product terms A bar, C bar, DE, A bar, C, D bar, E, B, C, D bar, E, A, C, DE, A, B, C, E, A bar, B bar, E, B bar, C bar, E & B bar, DE. In the second step of Quen-McLeod's case method the essential and minimal prime implicants are found. The prime implicants found in the first step are listed in the left most column of the table. The table is referred to as table 5. All the original minterms are listed in the top row so the minterms are 1, 3, 5, 7, 11, 13, 17, 19, 23, 29 and 31. In each cell an X is marked indicating that the prime implicant listed in the left column covers the minterm mentioned in the top row. Thus the prime implicant A bar, C bar, D covers the minterms 1 & 5. In other words minterms 1 & 5 all have the product terms A bar, C bar, D. The table 5 can be directly implemented from table 3 & 4. Circles are marked in cells having X which represent minterms covered by only a single prime implicant. Thus the minterms 11 & 17 are covered by only the prime implicants A bar, C bar, DE and B bar, C bar, E respectively. These implicants do not cover all the minterms. The other essential implicants that have minimum number of variables and which cover all the remaining minterms are B, C, D bar, E, A, C, DE and A bar, B bar, E. Thus the simplified expression that represents the odd prime number in the range 0 to 31 is represented by the product terms A bar, C bar, DE, B, C, D bar, E, A, C, DE, A bar, B bar, E and B bar, C bar, E. We just looked at the expression derived for the odd prime number checker circuit. I hope the expression which we have derived here is the same as the expression which you derived using your program. Let us start with the combinational logic. Combination logic as we said is basically combining a combination of different gates. A KLM gate and gate or gate no matter be gate how it cannot perform any useful function. So, they have to be joined together, they have to be combined together to form or to do some useful function. On what basis can we combine these gates? Basically, the expression which represents a function is used to implement the circuit. So, we have a Boolean expression which let us say represents the add function. We have a Boolean expression which represents the odd prime number checker circuit. We have an expression which represents the comparator circuit and so on. The last step would be to implement these expressions using combinational logic or different gates combined together. Now, we have studied two forms of expressions, the sum of product form and the product of sum form. So, if you are going to be implementing a circuit or a combinational logic circuit, it has to be based on these two expressions, either the sum of product form or the product of sum form. Now, considering the sum of product form expression, basically it has product terms which are added together. So, how would you implement a circuit? Combination logic circuit which is based on the sum of product form, basically it would have number of AND gates. Each AND gate would be implementing one of the product terms. You would have a single OR gate which would be adding all the product terms together. So, the outputs of all the AND gates would be connected to the inputs of the single OR gate. Now, each of the product terms have complemented input or uncomplimented input. So, for example, you have the product term AB bar. So, how would you implement AB bar? Basically you have an AND gate, one of the inputs is connected to A, the other input is connected to B complemented. So, B complement, how would you obtain that by using a OR gate? So, basically implementing a sum of product expression using logic gates, you would have a circuit having three levels of gates. The first level of gates would have the OR gate which basically sums up all the product terms. The second level would be comprising of all the AND gates which generate the product terms. The third level of gates would comprise of the inverters, the NOT gates which complement the different variables and provide them as an input to the AND gates. So, three levels of gates. Now, considering the product of sum form of expression, in the product of sum form of Boolean expression, you have sum terms which are ANDed together through an AND gate. So, again if you are going to be implementing a product of sum expression, you would again have a combination circuit having three levels of gates. First level would be comprised of the AND gate, the second level would be comprised of the OR gates which in fact generate sum terms and the third level would be comprised of the inverters or the NOT gates which provide complemented inputs to the OR gates. Let us have a look at the general architecture of the sum of product form of expression, the implementation of sum of product expression and the implementation of products of sum expression. The diagram shows the general architecture of the sum of product implementation. Sum of product expression is implemented by the AND or combination of gates. The AND gates produce the product terms, output of all the AND gates are connected to a single multiple input OR gate for sum of products. The product terms comprise of literals in their complemented form and uncomplimented form which are implemented by NOT gates connected to the inputs of the AND gates. The diagram shows the general architecture of the product of sum implementation. Product of sum expression is implemented by the OR AND combination of gates. The OR gates produce the sum terms, outputs of all the OR gates are connected to a single multiple input AND gate for product of sum terms. The sum terms comprise of literals in their complemented form and uncomplimented form which are implemented by NOT gates connected to the inputs of the OR gates. We have just looked at two generalized form of combinational circuits. One form is basically the implementation of sum of product expression. The other implementation is basically the implementation of product of sum Boolean expression. Now, let us look at the entire method. Where do you start? How do you design a circuit? How do you implement a circuit? Let us take an example. The example of a 2-bit adder. Now, what does a 2-bit adder do? Basically, it adds two numbers and each number is of 2 bits. The answer would again be of 2 bits but a carry might be generated. So, basically the function of a 2-bit adder is to add. How would you represent the function? Basically, you would draw out a truth table where you would have all the possible inputs and the outputs. Now, how many inputs do you need and how many outputs do you need? Basically, you need four inputs representing the two 2-bit numbers and 2-bit outputs. The adder, of course, also generates a carry. So, you need another single-bit output representing the carry. The adder might also add a previous carry. So, it needs another carry input pen. So, now you have defined the function of the adder through a truth table. You have defined the number of inputs and the number of outputs. What do you do next? Basically, you have to represent this function in the form of an expression, a Boolean expression. So, how many outputs do you have? You have basically three outputs, the two sum outputs and the carry output. Now, you can directly implement a combination circuit from the truth table. Now, the truth table, remember, has three outputs. It would have different combinations of 1s and 0s. Now, to implement, let us say, the carry output, you would select the main terms for which the carry output has been set to 1. So, what would be the circuit in terms of sum of product forms? You would have AND gates, which would be generating the product terms for different input combinations. The outputs of all those AND gates would be connected to a single OR gate. The output of the OR gate would represent the carry out function. Similarly, for the two outputs representing the sum, again you would represent or implement a circuit having multiple AND gates and OR gate. Now, if you implement a circuit directly from the function table, it would of course work, but it would use a large number of gates. Now, if you have large number of gates in your circuit, what happens? Basically, it occupies a large area. The circuit size is going to increase. The power requirement is going to increase. The propagation delay is going to increase. So, perhaps it would not be able to work at high frequencies. Now, the best option is to first simplify the expression. How do you simplify the expression? You have the function table, which completely represents the adder function. Now, for each output, you have to come up with a Boolean expression. Use a Karnaugh map or the McFleskey method or an appropriate method to simplify the expression. The simplified Boolean expression can then be implemented using combination circuits, logic gates. Now, the combination circuit formed after having simplified the Boolean expression would be simpler, smaller. Power requirement would be low and perhaps propagation delay would be low. So, we are going to be looking at some examples, which describe such circuits. Let us go through this design procedure. We would be designing a circuit. First of all, we would be defining its function. Then perhaps we would be defining its expression and then implementing the combinational circuit. Now, the circuit, which we are going to design is an adjacent 1 detector. What is an adjacent 1 detector? Let us suppose you have 4 bits 1, 0, 1, 1. Now, in 1, 0, 1, 1, you have 2 adjacent 1s. So, if your circuit looks at these 4 bits, it should be able to detect the 2 adjacent 1s. If you have another number 1, 0, 1, 0, now you do not have any adjacent 1s. So, your circuit should not be able to detect that. Now, first of all, we would be defining the function of this adjacent 1 detector circuit. Once we have defined the function, then we can either directly implement the combinational circuit from the function table or we could have a simple expression represented through a Karnoff map and then implement that. We can also implement a combinational circuit based on NAND gates. So, let us have a look at the different implementations. The adjacent 1s detector circuit accepts a 4 bit binary input and generates a 1 output when it detects a combination of 2 adjacent 1s. The function diagram shows the 16 possible input combinations and the corresponding outputs. Thus, for the input combinations 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 and 1, 1, 1, 1, 1, the output function is a 1. The information provided by the function table can be directly implemented to form the adjacent 1s detector circuit. Now, how many NAND gates are required? Basically 8 gates are required to implement the 8 MIN terms. As you can see from the function table, the output F is set to 1 for 8 different MIN terms. So, 8 NAND gates are required to implement the 8 product terms. How many OR gates are required? Since it is a sum of product implementation, therefore all the product terms have to be summed together. So, a single OR gate is required. The OR gate has 8 inputs. Some NAND gates are also required to implement complemented literals in some of the product terms. The sum of product based implementation of the adjacent 1s detector circuit is shown, implemented directly from the function table. The implementation uses maximum number of gates. The total gate count is a single 8 input OR gate, 8 4 input NAND gates and 10 NOT gates. All together 19 gates are required to complete the circuit. The increased number of gates increases the cost, the size of the circuit, the power requirement and the propagation delay which is of the order of 3 gates. An appropriate way to implement the adjacent 1s detector circuit is to simplify the SOP or the sum of product Boolean expression represented by the function table and then implement the circuit based on the simplified expression. The function table information is directly mapped to a 4 variable Carnoff map. The 1s are grouped together forming 3 product terms. The 3 product terms are AB, CD and BC. The simplified circuit is implemented using 3 2 input NAND gates and a single 3 input OR gate. The total circuit count is 4 gates. The cost of the circuit reduces. The size of the circuit reduces. The power requirement of the circuit reduces and the propagation delay has reduced from 3 gate delay to 2 gate delay. The simplified 4 gate circuit can be implemented using only NAND gates without a change in the total number of gates. Bubbles representing NOT gates are placed at the output of the 3 NAND gates converting the 3 NAND gates to NAND gates. To balance out the 3 NOT gates added at the outputs of the 3 NAND gates, 3 bubbles representing 3 NOT gates are also placed at the 3 inputs of the OR gate. The resulting OR gate symbol with 3 bubbles at the 3 inputs is an alternate symbol for a 3 input NAND gate. The NAND gate base circuit is shown. We have looked at 3 different implementations of the 1s adjacent detector circuit. Basically, we started with the standard sum of product expression. If you look at the function table, you see different MIN terms. If all the MIN terms are written, you would have a standard sum of product expression. If you implement all the MIN terms directly through an NAND gate, you would have the complete circuit. Now, this particular circuit requires a large number of gates. So, the circuit size of course increases. The 2nd implementation we saw, if you simplify the expression, basically in the function table, all the MIN terms are mapped. In the Karnaugh map, you end up with 3 product terms. If you implement them, you get a very simple circuit composed of 4 gates. There are 3 NAND gates and 1 OR gate. The last implementation, which we saw was the NAND-gaste-based implementation. Sare jo gates unko me convert kar diye in the form of NAND gates. So, in 3 circuits ka jo output hai ya function hai wo bilkul identical hai. Now, we have been saying that if you have a function table where you have all the MIN terms and the MAX terms, you can form 2 different type of expressions, a product of sum expression and sum of product expression. Now, 2 no expressions jo hai ek hi baat ka rahe hain. 2 no ka output jo hai ek hi aayega. Now, if you implement both these expressions through AND OR gates or OR AND gates, the output of the circuit would be identical. So, let's check that. Abhi hum ne jo 3 circuits implement kehte, basically wo sum of product expression pe based hai. Ab hum jo hai dubarase circuit bhenayenge, they would be based on the product of sum expression. So, usi tana you have the same function table. Usme ab MAX terms jo hai wo apne sare likh le nahin hai. So, you would have a standard product of sum expression. Ab usko kaise implement karenge, basically har jo MAX terms hai, that would be implemented through an OR gate. So, you would have a number of OR gates, basically agar ab dekhhi 8 MAX terms apko function table mein nazar aar hiye. So, you would have 8 OR gates. Now, the output of all those 8 OR gates would be connected to an AND gate, of course, which is doing what it is doing the sum of products or rather product of sums. The AND gate has 8 inputs of course. So, let us have a look at the 3 different circuits wo osko dubarase in baad mein summarize karenge. The product of sum based implementation of the adjacent ones detector circuit is shown, implement it directly from the function table. This implementation uses maximum number of gates. The total gate count is 1, 8 input AND gate, 8, 4 input OR gates and 10 NOT gates. Altogether 19 gates are required. Now, the gates required in this product of sum implementation are equal to the gates required in the sum of product implementation. So, the increased number of gates mean increased cost of the circuit, the size of the circuit of course increases, the power requirement increases and the propagation delay is of the order of 3 gates. An appropriate way to implement the adjacent ones detector circuit is to simplify the product of some Boolean expression represented by the function table. And then from the simplified Boolean expression the circuit can be implemented. The circuit of course would be simpler as compared to the standard product of sum based expression. The function table information is directly mapped to a 4 variable kan of map. The zeros are grouped together forming 3 sum terms. 3 terms are a plus c, b plus c and b plus d. The simplified product of sum based circuit is implemented using 3 2 input OR gates and a single 3 input AND gate. The total circuit count is 4 gates. The cost of the circuit reduces, the size of the circuit reduces, the power requirement of the circuit reduces and the propagation delay has reduced from 3 gate delay to 2 gate delay. The simplified 4 gate circuit can be implemented using only NOR gates without a change in the total number of gates. Bubbles representing NOR gates are placed at the output of the 3 OR gates converting the 3 OR gates to NOR gates. To balance out the 3 NOR gates added at the outputs of the 3 OR gates, 3 bubbles representing 3 NOR gates are also placed at the 3 inputs of the AND gate. The resulting AND gate symbol with 3 bubbles at the 3 inputs is an alternate symbol for a 3 input NOR gate. The NOR based circuit is shown. We have seen 3 different implementations based on the product of sum expression. The original circuit was based directly on the standard product of sum expression. You have a function table, you have the max terms, you can just write out all the max terms and you can then directly implement each max term using an OR gate. Basically max terms Well, we have said that the appropriate way to implement a circuit is to first simplify the Boolean expression representing the function of the circuit and then implement it. The idea is to reduce the circuit size to reduce the number of gates. We also looked at alternate ways of implementing circuits. Basically NAND gates कुम ने देखाता using all NAND gates, you can implement a circuit. Using all NOR gates, you can implement a circuit. कुम देखाता, basically we mentioned that a NOR gate is a universal gate. Similarly, a NOR gate is a universal gate. So, if you have a NAND gate or a NOR gate, you can in fact implement any gate. So, by implementing the same circuit, the adjacent one's circuit using NAND gates and NOR gates, we have proved that actually you can represent any circuit using NAND and NOR gates. एक फेदा एसका ये भी है, के if you look at an IC, Integrated Circuit उस में चार NAND gates है. So, basically when you are implementing a circuit, which requires let's say four NAND gates, you can only use a single chip. अगर वी सर्कित आप बनार हैं, using an OR gate and get different gates. So, different integrated circuits use only. So, again the circuit size would increase. So, it is better to implement a circuit using the same set of gates. Now, we have talked about two different ways of implementing combination circuits. How do we look at the performance of a combination circuit? ज़से में शुर में बात की थी, अपको अगर याध, तामिंग डियाग्राम की हम ने बात की थी. तामिंग डियाग्राम्स क्या रबजन करते हैं, if you have a certain circuit, you apply certain inputs and those inputs are changing over a period of time. So, you need to check the output for that certain period of time. कैसे करेंगे? तु ए तामिंग डियाग्राम्. So, basically, when you implement the adjacent one's circuit या कोई और भी circuit, then you have to check its performance, its operation for a certain time period. उस तामिंग बात कोंसे इंपुर्ष अपलाई करेंगे? बैसेकली आपने तेस्ट करना है, के वो जु फुंक्षन तेबल आपने बनाया है, जिस के तहाद आपने फुंक्षन तेस्ट करना आपने बनाया था, वोई वाले एंपुष आप अपलाई करेंगे, और देखेंगे, अबफुट पे क्या वोई चीज आ रही है गे नहीं? So, basically, we are now going to have a look at the timing diagram and see if our circuit actually gives the values which we are looking for. The timing diagram describes the operation of the circuit for the product of some based simplified circuit for the intervals T0 to T8. A, B, C and D are the inputs to the circuit. The timing diagrams show the inputs A, B, C and D changing with time. The timing signals 1, 2 and 3 represent the outputs of the OR gates 1, 2 and 3. The timing signal F represents the output of the circuit. At interval T0, the input A, B, C, D to the circuit is 0, 0, 0. The outputs of the 3 OR gates are 0, 0 and 0 and the circuit output is also 0. Now, this can be seen in the timing diagram. For the interval T0, the timing diagram 1, 2, 3 and F shows logic 0. At the interval T3, the input A, B, C, D to the circuit is 0, 0, 1, 1. Now, you have two adjacent ones. So, the output of the circuit F should show a 1. Let us have a look at the timing diagram. The outputs of OR gates 1, 2 and 3 are all ones as can be seen in the timing diagram. The output F is also a 1. At interval T6, the input A, B, C, D to the circuit is 0, 1, 1, 0. The outputs of OR gates 1, 2 and 3 are all ones. The output F is 1 indicating adjacent ones. The operation of the circuit which is based on product of sums simplified expression also proves that the product of sum based expression determined from the truth table and the kind of map results in a circuit which operates in an identical manner to that of a sum of product based circuit. We have just looked at the timing diagram of the adjacent ones detector circuit. As you saw, we can represent all the inputs and the output and the outputs of different gates within the circuit through a timing diagram. And then for different time intervals, we can in fact see the different outputs, the intermediate outputs and the inputs and we can verify the operation of the circuit. The other thing which we saw in this particular diagram was that we used the product of sum implementation of the circuit and we applied the different inputs and we determined that the product of sum circuit does gives you the appropriate output. So, it is equivalent to a sum of product circuit. Now, let us talk about active high levels and active low levels. What are active high and active low levels? Up till now, we have talked about different circuits. For example, this particular circuit detecting adjacent ones. Now, if the circuit detects adjacent ones, what is the output? Basically, the output is 1. Well, we could have said that if the circuit detects adjacent ones, the output should be 0. Similarly, we have studied circuits like the comparator circuit. In comparator circuit, we had 4 inputs representing 2 2-bit numbers. So, when they were compared, we had 3 outputs. So, if both the numbers are equal, then the equal output would be 1. So, let us see. Now, if you look at the comparator circuit, 3 outputs in normal state are 0. If a is equal to b, then the equal output a equals to b, then what is its state? It goes to logic 1 or binary 1. Similarly, if a is greater than b, in normal state, a greater than b, the output a is 0. Whenever a becomes greater than b, the output goes to 1. Similarly, the output a less than b, in normal state, is 0. Whenever a is less than b, the output goes to 1. So, basically, we call the output of this circuit as an active high. The output is active high or logic high. Now, we could design this comparator circuit so that the outputs, in normal state, the outputs go to 1. Whenever a is equal to b, the output goes to 0. Similarly, whenever a is greater than b, the output goes to 0. Similarly, whenever a is less than b, the output goes to 0. When there is a circuit like this, the output of the output state is active low or logic low. We have made this comparator circuit. Its output state is output high, active high. If we want to make it active low, then basically, we will put inverters on the outputs. How do we symbolically represent inverters by a bubble? So, basically, if we put bubbles on the output of comparator circuit diagram, it would indicate an active low output. Similarly, any circuit's input could also be active low. Considering the comparator circuit, when we give 1, 1 is represented by, of course, binary 1. Now, we could say that 1 is represented by logic 0. So, if logic 0 is given for the circuit to work, it should invert it and take it as a 1. So, what will we do? We will have to put bubbles on the input. So, that means the comparator circuit is accepting an active low input or logic low input. Let us look at the adjacent 1's circuit. In a normal state, what is the output of adjacent 1? It is 0. Whenever that adjacent 1 detects, what is the output? It is 1. So, its output is active high. If we want to make it active low, that means in a normal state, we are giving 1 on the output. Whatever that adjacent 1 detects, the output should be 0. So, then the circuit would become, the output would become active low. What do we have to do to make an active low output? We have to put an inverter on its output. How do we represent an inverter through a bubble? So, in the diagram, if we see bubbles on the output of adjacent 1, it means it has an active low output. Similarly, adjacent 1's circuit is its input. We can make it active low in that. What we are dedicating to adjacent 1's is how we represent them by binary 1's. Let us suppose if we give the adjacent 1's circuit an active low input, then what we have to do? We have to put an inverter on its input. So, if we look at the diagram of adjacent 1's circuit, we will see bubbles on its input. Bubbles would of course indicate that the input is active low. Now, let us consider the 4 gates which we talked about, the AND gate, the NAND gate, the OR gate and the NOR gate. If you remember the symbol of AND gate, its inputs are active high. So, 1 AND 1, what is the output? It is an active high output. 1 AND 1 gives you 1 output. If you look at NAND gate, the symbol of NAND gate is similar to that AND gate symbol with a bubble at the output. How does it work? Basically, 1 AND 1, active highs, inputs. What is the output? 0 is the active low output. Let us look at OR gate. OR gate, both the inputs are not bubble. That means 1 OR 1, both are active high inputs. What is the output? If any of them are 1, the output is F1. So, output is active high. What is NOR gate? NOR gate is similar to OR gate, but it has a bubble at the output. So, what does this mean? If there are 2 active highs on the input of NOR gate, 1 OR 1, the output is 0. Active low should be there. So, just remember this rule. Any circuit which is active high input can be active high output, active low input can be active high, active low output can be, combination can also be active high input, active low output. Similarly, active low input, active high output. So, different 4 combinations can be done. In fact, we have made 2 adjacent circuits. We will make it active low. Let us have a diagram. Let us come check it through a timing diagram. Let us quickly have a look at the 4 gates. AND gate performs AND operation on 2 active high inputs to result in an active high output. Similarly, NAND gate performs AND operation on 2 active high inputs resulting in an active low output. OR gate performs OR operation on 2 active high inputs to result in an active high output. Similarly, NOR gate performs OR operation on 2 active high inputs to result in an active low output. The simplified sum of product paste implementation has an active high output. The circuit can be implemented to have an active low output by connecting a NOR gate at the output of the circuit. Now, whenever adjacent ones are detected, the circuit output is set to 0. The circuit is also shown to have active high inputs. The circuit can work with active low inputs producing an active high output if NOR gates are connected to the inputs of all the AND gates. Consider now the sum of product based circuit which has active high inputs and active high outputs. If the inputs of the circuit are made active low and the output of the circuit is also made active low then bubbles are added at all inputs of the 3 AND gates. A bubble is also added to the output of the OR gate. The bubbles added at the input of the AND gate represent the alternate symbol for the NOR gate. Similarly, the bubble added to the output of the OR gate also makes it a NOR gate. By modifying the circuit to have active low inputs and outputs, the circuit sets the output F to active 0 to indicate detection of adjacent ones. Since the inputs are also represented by active low, therefore the input ABCD equals to 0, 0, 0, 0 actually represents 1, 1, 1, 1. Similarly, ABCD active low input 0, 0, 0, 1 actually represents 1, 1, 1, 0. Let us now have a look at the timing diagram. The timing diagram describes the operation of the circuit for the intervals T0 to T8. The timing signals ABC and D represent the active low inputs applied at the inputs of the circuit. The timing signals 1, 2 and 3 represent the outputs of the NOR gates 1, 2 and 3 respectively. The timing signal F represents the active low output. At interval T0, the active low input at inputs ABCD is 0, 0, 0, 0 which actually represents 1, 1, 1, 1. The active low output F is 0 which indicates that adjacent ones have been detected. Similarly, at intervals T1 to T4, the active low inputs ABCD are 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 and 0, 1, 0, 0 which actually represents the numbers 1, 1, 1, 0, 1, 1, 1, 1, 1, 0 and 1, 0, 1, 1. The output is 0 indicating that adjacent ones have been detected. Up till now, we have been assuming that logic circuits work with an active logic level of 1. Whenever they are activated, the logic level should be 1. It is not necessary. As we have seen in the example, logic circuits can operate with active levels as 0s and 1s. So, in the course, we will see different circuits which are being activated on 0 or on 1 and different examples taking them. Now, let us look at another example, the example of an odd parity generator. We will make a circuit which will generate odd parity. Now, if you remember, we mentioned that when we transmit data from one end to the other end, some bits can be damaged due to some external noise. 0 to 1 will happen, 1 to 0 will happen. So, by adding a parity bit, we can detect a single bit error. Ok, what will happen? We have, let us say, 4-bit data which we have to send from one end to the other end. What we will do is, we will send a parity bit which means 5-bit data on the other end. Now, if we are using odd parity, that means, we will count the 4-bit data in the number of 1s. If the total number of 1s is 0, then the parity should be set to 1. So, the 5-bit data will have parity 1. If the 4-bit data has odd number 1 or 3, then the parity bit would be set to 0. So, the total number of 1s in the 5-bit data remains an odd number. Now, how to make the circuit of the odd-bit parity generator? Well, let us just discuss that. Basically, we have to make a function diagram which would indicate the inputs and the appropriate outputs. We can directly make a circuit by making the function diagram. The circuit would be complicated because it would have a large number of gates. We can simplify the expression and then implement the circuit. That would be a simpler circuit. And of course, perhaps it would be faster propagation delay come, power requirements come and so on. Those are the advantages as compared to the large circuit implemented using the standard sum of product expression or product of sum expression. Let us first look at the function diagram of the odd-parity generator circuit. Now, let us assume that 4-bit data has to be sent. So, how many inputs are there, how many variables are there? Basically, 4 variables are there in the function table. There are 16 different inputs. That means, 4-bit data is represented in 16 different combinations. Now, what would be the output? The output would be basically the only one. The output would be the parity bit which has to be generated. So, for example, the data is 0-0-0. Four bits are 0. the odd parity generator circuit in the next lecture function diagram banane, regression likhane or combination circuit banane till the next lecture hode haafiz and asalam aleikum