 Hello everyone welcome to the second lab of priming of unit 5 in this lab we will focus on the post layout timing analysis so we will talk about we will practically see all the concepts that we have been discussing in the lecture 25 we will look at the propagated logs, we will look at the parasitics, we will look at the OCD settings, timing the rates, PR, PR and so on right so we will focus on this one also during this course you can please make a note of I will keep pointing on the important thing that differ between data and post layout and just please make a note of it obviously it is also mentioned in the lecture sessions also so it will just try to make a connection between what changes will be go from the area of the post layout. So our design is this design comes from one of this example so this is the design ORCA Routed.v this is an ORCA as a small CPU I think it is open source CPU small CPU so it has a clock generator so it has various blocks it has a clock it has multiple the good thing is that it has multiple clock so we will also look at the cases how to deal with multiple clocks this is the top level ORCA and inside it has some memories also some clock generation logic there is a PNN also so it is a good test case for us to do. We also see let us take a look at the parasitics also how does the parasitics will look like so this is step so step is the header explains what is the order of units so the important thing is here is the capacitor unit on the R unit there also L unit is specified but there are no L extractors so since inductance is negligible the extraction tools will not extract the inductance at all so all the L unit is present here but there is no inductance value. So it has the first section here then is the name map section where a number is assigned to every port and every net every pin every port so that means all since the nets so parasitics are characteristics of nets not cells so and a net is a connection between two cells so for each of these nets for each of these pins of cells that they are above for connecting to above for the net this is something like this that the RMC of a particular net between point A and point B is something now the point A it will be for example point A it will be output pin of a particular cell point B will be input pin of a particular cell all such pins are given some numbers so this is the first section here the name map is given is assigning some numbers to various pins for example see see this the IO at the top IPCI core you tell this is a number is assigned a number similarly these are input so power save is an input to this chip so this is a complete chip it even has power so it is kind of a small chip design is kind of a small chip and so every there are various numbers here now if we go go forward there will be lot of numbers and now let us go in the now for every so there is a cap section so this is a net so the section in the D net and it is assigned it is connected from a number and so this is the connectivity from something I so to something ZN so this is this is the way it shows the connection and for this particular net it will show what is the so these are the segments these are the net segments 1 2 1 3 for this particular net 4 3085 and it is given the capacitive of the net with respect to the ground so it might also have the coupling cap but I do not see it here double check it in time time but this is a way it looks like it looks like it has resistance and for each net it will have let us say for each net it will have a cap value a cap table in a resistance table and these are the nodes Coulomb 1 Coulomb 2 Coulomb 3 so you can even try to pick up a particular net and see so as an assignment what you can do you can pick up a particular net in a net list and correspondingly try to search for that net R and C value in this book so this is a good assignment that way you can understand better how the syntax works I can do this here but it is not that important and if you take some time because stuff is a big file again and searching through it is it takes time so you can also do this kind of debugging in time time also so now so we will use this design for this particular time and then go to the work directory and open form form now I have already prepared a script so we will again study what all goes into this script many of the sections are familiar to you some of the commands that are new will be specific to post them so we will first set the search path the link library here is a slightly bit because it contains so many memories RAM 32, 32, 15, 14, 15 and so on so it has a clock multiply and PLL so clock multiply and PLL both go both are coming from this library special.db memory come from RAM something.db the IOs are also present here so it IOs come from IOMag 32 so it is a very common phenomenon because for each of these the vendors might be separate the standard cell vendor is usually separate then memory cell even if the same when vendor is providing the library they will prefer to separate out these they will give standard cell as one deliverable they will give memory and other IO as another PLL as another so you have full chip STA link library list will be pretty long so we will set this so we set the search path and the link path then we read this slide and link it so it shows that it is loading so and so libraries this information removing 24 unneeded designs what it tells us is that prime time to save on memory space it will load up the full chip whatever the complete netlist and it will only keep limited information about the internal design so you cannot change the current design however link has an option so if you do a link link has an option keeps up designs so it will keep all that 100% design info after linking so that you can change to that particular design but this is not recommended since usually SP is carried out at the top level of a particular block or a particular chip so it is recommended to do just link and let prime time remove some information related to the designs that are in the within the hierarchy and it is not leading to any loss of information for all timing purposes it is not leading to any loss of information it saves on some memory plus but the only thing is that it is it won't let you prime time will now won't let you change the current design to something else after you have with the top design right so this is the only disadvantage so this is the default needed of link it will remove the unneeded designs so it does give some methods regarding to the operating condition but we will set the operating operating conditions directly now the important command here is specific to posting of the read capacity so this is the command so we will read we tell what is the format and we will read this step which is for this design and now it will give some message about some information and if there are some errors it is very important to understand those errors those are slightly so those errors would be related to whether it is not able to find any net which is given in this or there might be cases where the net in the in the net list do not have any corresponding nets in the set so it will give errors with regarding that those nets so if a net if an extra net is within so if any such mismatch occurs it means that the net list on which the net list that you have and this test that is extracted has some mismatches and most probably the net list you have or one of the step needs to be updated so the back end lead will giving you the or if you are the back end engineer if you know a mismatch then you need to make sure that this you are taking the net the same net list which we use to do the example it is very necessary to do that which is the errors like missing net one of the net list of this now if there is some extra net in the set fine it will give another but if there is some some nets which are not present in this set then time time will use by load model to so by default when after you need pass it takes time time is not able to find any R and C for a particular net in this set it will complete it using viral model and it is not recommended because you are working at a post layout stage and you should resolve all the errors before time right. So, it tells us there are 0 errors how many annotated nets that means these main number of nets have resisted within them the step and they are annotated capital. So, these are the total annotated nets these are the capital senses and resisted. So, each net can have multiple caps multiple nodes and different resistances. So, it says that there are the coupling capital senses 0 we will look at if I am able to find let ok let us do one thing we will do remove annotated parasitic. So, remove annotated parasitic will remove whatever annotations look this process is called annotation. So, we could do remove annotated parasitic minus all we will read the parasitic again, but let us look at the help first for this read parasitic it is a very expensive smart. So, the important things here are that this complete this completion type this tells us the this time time that if you do not find any nets in the step complete with either 0 or viral model that means, apply a viral model or do not apply anything. Lumped cap here if you are reading steps you could not use this option, pin cap included this test where it is that the RC network includes the pin capital senses in most of the cases the RC network inside steps will not include pin cap resistances pin cap will come from the library itself increment is something where you are reading multiple step 5 or hierarchical step 5 then you have to use increment power prefix increment are used to when you are when you are reading. So, for example, a chip level has multiple blocks and each let us say it has 5 blocks and all 5 blocks have been made out separately. So, there will be separate steps you will use minus increment and minus path option to annotate this step at a particular instance path and this is important keep the capacitive coupling which try out keep capacitive coupling is like for if the step has capacitive coupling and you want to do signal integrity noise analysis then you have to turn this option on let us see if it gives something ok it tells us that annotated coupling capacitive is 0 that means, although we give keep coupling keep capacitive coupling, but it tells us that annotated coupling capacitive is 0 that means, it does not have any coupling data and we will not be able to do noise analysis on this. So, a very useful command is the report after you read in this parasitic a very useful command is report annotated parasitic the help it will. So, it tells us it gives the summary report of what is annotated and what is not. So, you can do lot of you can do it on a particular net you can do it for internal nets, boundary nets, driverless nets, loadless nets there is only one. So, just do the default thing. So, it will give certain messages. So, even if so, there was no error reading the parasitic this is the first phase. So, fine all the so, there is no mismatch in terms of the nets and pin names between these both on the network that is sure, but now it is saying that there are some RC annotations that are incomplete right and in this in the summary we can see that. So, there are two types of nets internal nets and boundary nets, internal nets are pin to pin boundary nets are those are coming from ports. So, this pin to pin not annotated is 0 the first the first one is very important RC network for all internal net is completed not annotated is 0. So, there is no problem here good. Now, it comes to driverless nets. Now, usually driverless nets a non net are without drivers. So, they are kind of having nets usually any problem here not annotated 24 is usually ok to it is not a serious issue because that net is not driving anything loadless net again it is correct here not annotated is 0. Boundary there might be some problems like this. So, penalty when are not annotated for boundary port net and you might need to debug it you might need to debug with the backend engineer or you also for the backend engineer you might need to debug why the port nets are not annotated. So, many times the port nets are usually lumped into some value because some is lumped into some value many times if there are pads involved then such cases can occur. So, it depends on case to case basis, but as a an ST engineer then this is the most important thing internal network should be completely annotated. Now, although it is giving some messages here that ignoring the incomplete. So, for example, if you that this driver thing is missing in the RC annotation for this particular net. So, it might happen that this there is nothing which is driving this or let us look at. So, for a particular message you can look at what it means by doing a man on this. So, it tells me so it tells us that you receive this message informs you that RC network on a specified net is ignored because it is incomplete the specified way is not physically connected to authentication. So, you probably have to debug this and make sure that it is ok to go. So, there are many error and warnings that you can wait, but only after careful checking right. So, we have now read the parasitics to now we are not working at a valid model level we are working at an RC level. Now, we set the operating condition and now this is very important on chip variation. We will set it to on chip variation and this is type is on chip variation and we have this is the operating condition. So, this is the one thing that we have probably explains why there is no talking about it might be negligible. So, this is the worst case operating condition and now we will be working at a worst case in the worst case model because we have read the all the max DBs. So, transparently there will be min DBs for the model. Now, we will create clocks we will create some clocks. So, there are now 3 clocks here 6 clock, p clock and sd i clock we will create each of this clock. So, now we are up to constraints. So, we will create this clock I have assigned some periods I am not sure what the specification of the chip is I have just found some period model 6 clock p clock and sd i clock now there is 3 clock. Now, there is also a generated clock that we need to define the generated clock is at the output of a. So, let us go at the syntax this is a generated clock I have given a name I have seen multiply by 2 because this is what we what we expect what I understood from the net list this is the source. So, this particular block I CLT mal is a clock multiplied and I have seen from the net list that at this input it gets 6 clock and output is this this multipliers clock to it ok. So, I will I will show you the net list. So, what I will do is I will create a multiply by clock multiply by 2 clock of this output and the source I am giving as this I can even give source as this because this is the clock that reaches there. So, you can give source can be anything before the generation clock generated clock creation form. So, source can be before anything before this in the panel network. So, I am creating this clock now. So, now I have created all the clocks now the next is that you should specify what is the clock relationship between the clocks among all the clocks. Now, in this case what I have learned from the net list or what I have seen from the earlier time in the process of is that these 3 clocks are not synchronous to each other. Anyway, let us assume for once let us not assume anything. So, we will not give any false thoughts right. Now, let us say you are you are driving you are writing the constraint and you know that these are the 3 2 2 15 5 and 12. And now you do not assume that they are either fault they are either asynchronous or synchronous. However, one thing is clear that the periods for 5 and 15 yes the periods are some simple multiple, but for 5 and 12 it is not a simple multiple even for 12 and 15 it is not a simple multiple. So, one thing you can reduce from the 3 20 with them whether they are synchronous or asynchronous. Secondly, you can see whether what source they might be coming from. So, typically if at a chip level you are working at a chip level and at a chip level if 2 clocks are coming from the outside world most probably they will be asynchronous. Why because since the routing resources people want to limit it in we want to limit the routing resources especially for high people like clock any there is no reason in most of the cases there is no reason to provide 2 synchronous clock at the chip level or even at a clock in a layout clock if it is not absolute density. If the 2 clocks are coming from 2 separate period does not depend what period they have they should be declared as asynchronous. Now, let us say we want to the other cases of this generated clock. Now, this generated clock is generated from 6 clock 6 clock 2 x is generated from this clock because this is this pin gets this clock. So, now let us what let us do a simple update timing for ok let us not do not apply any false path and let us proceed now. So, let us not apply a false path for now we will apply clock uncertainty and now clock uncertainty here will be a much lower value earlier we used to say 0.3, 0.5 now I said it to be 0.1, but it should be a lower value than earlier because now the clock network is in place it will calculate all the delay the excuse will be real the only thing which will be part of clock uncertainty will be most probably clock data and nothing else or some margin if you want to have. So, I apply clock uncertainty very important giving the propagated clocks set of clock or we will set all clocks to propagated mode only then time time will calculate all the actual latency all the actual network delay and then I will group pass this I find it very useful to group the input output path group to make sure I have different groups for input group and different clock path group for the output group then I will enable this I will enable the CRPR pessimism removal by setting this at time and remove clock between specific input group I will enable this if not it will not give me CRPR credit you will see how that happens then I will set the timing periods. Now this is the worst case I believe although I should ideally set the timing date the late timing date to 1, but I will set it to just one point one just to show you what effect does it have. So, I will set the timing dates and then that is it. So, what is special for course layout timing date CR turning CRPR on propagating the clock reading the parasitics setting it to OCB. So, these are the important things you read the actual parasitics by doing set propagated clock you are posting time time to calculate the all the proper latencies by applying timing dates and setting the chip to OCB setting the operating condition analysis mode to OCB you are making sure that you are accounting for the on separation for the physical effect CRPR you are making sure that unnecessary pessimism does not harm your parts in the clock uncertainty you have to adjust for you do not have to now estimate the clock skew clock skew would be real calculated. So, you need to reduce this value now we will do update time now update timing will gives lot of messages many would be for some dry resistance is being too low and. So, prime time and adjusted the dry resistance first type of messages are ok they are not harmful next is very important when it gives this PT 0 1 6 kind of movie. Now if you remember we discussed about the if you have two class of different frequencies how does prime time calculate the set of the voltage. Now in the first rule was that it will expand the analysis time period to the LCM of the two clocks concern. So, now the LCM for each we have we will do report clock now see we have P clock SDR clock 6 clock and now we have 6 clock 2 X. So, we gave we told and time to create this clock. So, the second part of the report is about a genetic clock we told I am time to create a genetic clock and we gave this as a master source and this is a genetic source. So, prime time has determined that this is 6 clock is reaching this and the waveform is multiplied by 2. Now let us say if this protein had multiple clocks reaching it this can be possible which is possible then you should also give master clock source as an extra element between the two clock. Ideally you only give to me to give name master source, genetic source that is it, but if the master source has multiple clocks then time time will not flow which clock to you with the master clock. So, then you also need to specify otherwise it is fine otherwise it is ok to give only master source and genetic source. So, you can know more about it by looking at a genetic clock minus help. So, you have a master pin which is compulsory to give source and then master clock clock is essential if multiple clocks are present in multiple. So, it has other options also edges what we discussed again multiply by divide by. So, you can read more about it there are so many options of you can compare in many cases we have complex genetic clock. So, this this genetic clock command is very powerful it will handle almost all the cases. Now, so now we have three clocks one period is 5 other is 12 other is 15. So, it will expand each clock to the LCM of these three or these four other and the LCM of all these is 60. So, it will expand it to 60. Now, assume if one clock had a period like 33 or 17 the LCM will be three later. So, you have to look for this message three messages in update timing expanding clock. If the clock expansion period here is too large then you have a problem right. Now, what I will do I will simply do now we did we loaded the parasitics we saw how to make sure that parasitics are okay by doing report and update the parasitics and looking out for other messages we saw how to create multiple clock how to create the new clock. Now, let us do a report timing I will just go report time minus no state. So, this will give you just to repeat this will give me the worst part for each part break one worst part among each all among all the path groups. So, this is what it gave me let us do let us output it into some report and then look at that report. Now, this is a set of report obviously, it is an I did not do I think about it all the report path group 18 default 18 default is for recovery renewal. So, it is showing me that now see this is where the problem occurred. Now, we see that now since there is no there is no we have not defined any basic relationship between the clocks all the clocks are considered to be similar. So, now it will decide on edges now this is an assignment for you that you know that sysclock period is 15 sysclock period is 15 SDI clock period is 12. Now, you have to convince yourself why did the setup edges why in the setup edge 45 and 40 remember you have to examine all the setup edges within the LCM period which is 16. So, one thing is clear what an experienced person could tell you quickly is that ok period 12 period 15 that means. So, see you have to also see that what is the launch it says capital LDR launch is 6 launch is 15 capture is LDR. So, down the LCM it will happen down the period it will happen that some SDR clock edge which. So, first it will be the rise will be at both rise are at 0. Now, in this case I have not specified any waveform. So, for both the rise it has 0 for this the rise edge is at 0 the capture is at 7.5 for this the rise is at 0 capture is at 6 ok. Since the waveform is similar in the sense they have 0 rise the period difference is 3. So, at some point of time during the complete SDI period it will happen that the this clock if this is the capture clock will capture after a period difference of whatever is the period difference. So, where you see the difference is 3 and here if you see 6 clock 45 SDI clock 48 the difference is 3. So, it will happen for hold if you do not give any specify any waveform and since the edges are coming at 0 0 the checking will always be performed at 0 0 in most of the cases. So, but do do not take my word for it draw the waveform on the paper yourself convince yourself that if this SIS clock is launching and SDR clock is capturing if time time has done a correct correct job of going 45 and 48. Second important thing clock network delay propagated clock network delay propagated is the sum of it is the total clock latency that time time is calculated. So, it is giving a propagated figure it will give just a figure here if you do not give any option and report. So, 45 is the rise edge plus 3.09 is the propagated plus this you already know clock to delay I will expand this report time in each and every time. So, I will tell you the major figures here clock network delay propagated these are again gate delays then the capture edge again it will give clock network delay propagated now see this is the skew 3.09 is the propagated delay versus clock 1.96 is the propagated delay for SDR clock there is a through the through and this is where the clock relationships are very very important. Now clock 3 network needs to know whether 2 clocks are synchronized if the 2 clocks are synchronized together it will build a common clock 3 because it needs to balance this through across. So, skew balancing is needed for all the parts which interact with each other if the 2 clocks are synchronized then there will be timing part between them and the clock 3 synthesis algorithm will consider that and build a common clock 3 and so the skews will be within some particular strict limit. If in the back end the 2 clocks are deemed as a synchronous then there will be independent clock phase and then their skews will not match. So, if in back end if in clock 3 synthesis 2 clocks are deemed to be a synchronous, but in STA you are calling them synchronous then it is a problem the skews will not match right. Now here we see that we see that the there is ok there is a clock network in propagated and this is the proper skew 3.09 minus 1.96. Clock reconversion pessimism is 0 why 0 because there is no common clock path I will I will explain this further, but here is 0 we have here is 0 this is also one indication now, one indication that these clocks are recent must now see as I explained you know obviously this will not be the case for people working in industry. When I started on this lab I did not know anything about the clock I just decided that it is an arbitrary clock period and I did not know whether these clocks are so, I decided not to assume anything I did not set any false time, but now I see that first indication skew is mismatch 3 and 1 1.96 there is a big difference 1 nano second is a big skew 1 indication that they are not synchronous. Second indication there is no common path these are both are coming from primary mode so, there is second indication that they are asynchronous people and let us see other reports then here it is a sysclock and sysclock. So, here it is good sysclock to sysclock so, now we see good this is an example of a half cycle path where the launch clock or latch is working on a negative f. So, now usually when a path is launched by sysclock captured by sysclock usually it will be full period long 0 and 15, but here the launch point is the negative level sensitive latch. Now since it is negative the launch active edge here is the fallage so, this is the fallage this is the rise it is capture it. So, now you get a period of 7.5 see here the CRPR has some value. So, it is delaying CRPR removal is delaying the capture clocks when you delay the capture clock in case of set up it is an advantage. So, CRPR is a pessimist removal it is not a pessimist addition pessimist if you do not do CRPR analysis that means, extra unneeded pessimism is added to your flow CRPR is a process to remove this pessimism. So, it will credit to the slack right. So, this is one example let us go further this is an input group it is assuming some 0 input input delay because we have not specified any input delay. Now, here also in case of multi clock till clock now you cannot give single input delay with respect to one thing you clock to all the input. You have to know design wise which inputs talk to which clocks for example, here this report without even giving any input today this report tells me that there is a part between SB this pin and this clock domain. So, I know that yes this pin SD DQ pin should be given some input delay with respect to SBR clock not any other clock as you make let us say SBR is a synchronous clock that I should be very careful. Now, let us say you have you are working in a chip some of the inputs go to memory controller other inputs go to CPU. Now, we should not assign input delay on memory controller course with respect to the CPU clock you should restate the domain assign input delay on the memory controller course with respect to the memory controller clock. This is what here we have to do SD pins are the names added they are related to some SBR interface memory interface. SBR clock is again a memory clock. So, these pins should be assigned input delay with respect to SBR clock only what with respect to any of the. So, things become a bit more complex a bit more detailed when you go to when you have multiple clocks right. So, you have to be careful. Now, so we have applied clock uncertainty to all the clocks which is it is getting subtracted here and rest all you are already already familiar let us move ahead. Again we see the path from SDR clock to P2. Now, here the problem is that we are only getting again the skew mismatch here 2.85, 1.97, one evident second evident both of them are coming from the ports. So, they have no common clock common logic clock logic. So, CRPR is 0 CRPR and again repeat clock reconversions precedence removal can only happen if you have a common clock path between launch and capture. So, here also since both the clocks are coming from primary port there is no common path CRPR is 0. The report timing report also tells us what are one of the delays and now with the present top frequency we see that the launch rate is 24, capture is 25 something wrong there is 1 nanosecond difference 130 nanometer logic cannot work at 20 levels. So, it appears that SDR and P clock are again asynchronous to each other. So, again you have some strange relationships 22.5 and 24. So, if you do not declare your if you have such few years and if you are spec actually state that your clock should be asynchronous to each other and if you do not declare it as such you will have not of strange timing reports for the like this launch launch at 22.5 capture it to be just same numbers right as my experience says. So, what I do I will clean up this, but as an assignment just do one exercise that assume the 2 clocks to be 1 clock to be 15 other clock to be 12 and give me what are the tell me what are the launch and capture is you the answer is here you have to just make sure that understand it. So, in this case it is 45 and 48 it is a set up remember here the launch is 6, capture is SDR, launch is 15, capture is 12. Let us see so, let me go to the specific case now from get clocks 6 clock S2 clocks SDR this is how I do specific report time and again 45 and 48 is ok and advance to make it clear right. Now, see when I did this there are two timing reports here one is the async default. So, async default since it is a different group than the clock group. So, it will give me again it any report timing command it will try to give me whatever path group to satisfy for each path group it will give me the work clock. So, in this case the capture clock is SDR clock, but here also for the async default also the capture clock is SDR clock, but since it is a recovery removal type of check it is grouped under async default it will give me the async default report plus it will also give me the regular S2 S2. So, 45 to 42 ok now let us make this one interesting I will now report the whole time I say whole time how do you report you said delay type mean. Now, here is 0 and 0 which is what I told you always if the two clocks you do not give any waveform numbers it will assume the rise is 0 and if you do not have asynchronous relationship if you do not define false path then the hold edges in all probability would be 0 and 0. You can verify this by again drawing it in your on a on paper draw other waveforms make sure you understand how the edges are calculated. I can you can do the other way round also now let us say minus 2 and minus 0. So, delay mean is ok 30 30 30 30 is same as 0 0 no difference, but here so see here it is 0 0 here is 30 30. So, 0 0 is exactly same as 30 0 it is no difference form. So, sometimes time time will go to the same 30 30 here why because there is a fallage. So, there is a fallage here and there is a rise edge and why there is a fallage because it it has some poly mesh because this clock in somewhere which is launching the data. So, it will give the fallage and it will because the fallage is a 30 the capture is at rise is at 30 for hold. So, it is so 0 0 is same as 30 30 time time will shift the edges when it when it comes negative right for hold. So, understand this between both these clock to and from I will again give the so now see it is 12 and 15. So, this is very clear if you draw a figure this will become very clear because now the launch in SBR capture is this. The SBR rise it comes at 0 then again at 12 for 6 clock the rise comes at 0 the capture comes at 15. It is for the capture clock the capture edge is coming at 15 the rise edge is coming at 0 and 15. So, at the 15 the launch edge of the launch the launch clocks launch edge just before this is 12. So, it is 12 and 15 similarly you will see that how it is 45 and 48 when you turn the when you do the launch of the SBR. So, as an assignment draw the wave form on a paper for both these clock as you have one clock to be launch other clock to be capture do it for both the cases with the clock then and make sure that you understand what are the launch edges what are the capture for both set up and both will be set up right and make sure that you understand it completely. If you do not understand it go back to the lecture slide in which we discussed this concept. Read the man page read the documentation and make yourself very comfortable with it right. Now, I do the actual stuff now I have seen that there are evidences that these clocks are asynchronous to each other. Now, I will flag all four. Now, since I am not doing noise analysis I can use false paths to declare by clock relationships it is alright to do this if you are not doing noise analysis. Now, one thing you have to be careful is that in this design 6 clock and 6 clock 2 x are not asynchronous 6 clock 2 x is multiplied by 2 of this clock. So, you should not by mistake set a false path between these two. So, what how I do it I do something like this. There are many ways to declare false paths between a Drupal clock many people will write some tickle procedure many people will do some more sophisticated, but we will do very basic stuff here we will just use we will not write any procedure we will write the clock names here. So, here I say minus from the clock list 6 clock and 6 clock 2 x and grouping them in the same list because they two are they should not be set that false path with respect to each other. So, now for end time with a player false path from this clock and 6 clock 2 x to p clock and SDR clock. Now, secondly I should do p clock to this group. So, so then I do from p clock I do from p clock from p clock to 6 clock 6 clock 2 x SDR clock I do like this then I do the last case which is from SDR clock to 6 clock 6 clock 2 x and p clock. These three statements make sure that 6 clock and 6 clock 2 x are synchronous from this group between this group and p clock they are asynchronous between this group and SDR clock they are asynchronous SDR is asynchronous to p. So, these three commands will make sure that you have clock or clock relationships defined any change in constraints I have to do update timing even if I do not do it the next command I run one will force it. So, I will do update timing now see prime time is giving me one information now one information of about p t 0 1 6 with the code p t 0 1 6 it is expanding this clock to it. Now, let us report blocks let us do report blocks again. So, clock 2 x period is 7.5 this clock period is 15 both of them are synchronous that is why prime time needs to expand the period of this clock 2 x to 15 the LPM of these 2 15 and 7.5 is 15 it is a typical case of master clock and a multi-climbing 2 or a master clock and a divided by 2 it is a typical case right. Now, my constraints are good enough except input and output in it. Now, let us look deeply into what all options is report timing now let us understand our CRPR works let us do some clock analysis. Let us do what an STI engineer will do during the the process of making sure that the constraints are correct everything is correct right and later we will come to the point now this is. So, do this analysis this session will focus on how to debug stuff how to understand timing reports and make sure that the constraints you have specified the rates you have set and everything is is in place it is correct and the second part the later in extension of this is now you analyze volitions and you try and fix them as an STI engineer the job is also to help fix the quality right. So, we will look into that later probably in this job or the person of the clock. Now, there is a very interesting command called report clock timing report clock timing helps us in analyzing a particular clock in terms of its latency and speed. Now, it has a lot of options it has almost a lot of options which are common to report timing why because they are common to and so on. So, one example I will show you I will say report clock timing is there a minus clock option. So, yeah it has a minus clock option otherwise it will do for more all the clock. So, let us do it for one clock more let us do it for PCLK and the compulsory option is minus time right asking you what. So, let us give minus types cube report clock timing minus clock PCLK types cube. Now, it will tell us now ok now there will be a bunch of registers driven by this clock. So, what we could do is we can say how do I know this I can do all registers minus clock PCLK now this way this is a command you can write to the list of all the registers that are driven by PCLK. So, now among all these registers so, I will give one more interesting command it is called size of collection. So, now let us say I want to know the number like the session is closing yeah. So, before clock timing minus so, I will I was showing you an interesting command which is so, all registers minus clock PCLK will give you a list of all the registers. If you can any any command that returns a collection in ticker you can do a size of collection on it and it will give you the number. So, there are 1076 registers on register PCLK. Now, this command report clock timing minus clock clock name and types cube gives us among these 1076 and clock it will give us the clock that has the best latency and give us the clock that has the worst latency. So, this block here has the best latency of 2.86 this block this block here the block in of this block has a best latency of 1.89 this is the CRPR among these two because there will be a there will be a common clock period although there might not be a path between these two there might and might not be a path between these two, but it will show you the latency it will show you the CRPR and the SKU SKU this is a difference to the difference adjusted by the value of CRPR here it will tell what is the edge whether it is the riser. So, it is right rise p means clock is propagated and minus plus are just like what is the riser what is the launch and what is the capture edge. Now, so, this can this this this command is the quality of the clock you can also say in minus type latency and now it will give the it will give only right now it is giving only one clock with a particular it will be it will be this same clock it is giving the latency to be total latency to be 2.89 or transition IPCI score yeah it is giving a some clock and it is giving latency value. Now, you can give ok so, no no ok I will I will I will experiment again because I will I will I will I will I will I will explain it wrongly in terms of SKU let me analyze latency first forget about SKU I will correct on the SKU part on the SKU part if you So, minus inverse to be let us say 50 and I will give minus no script. So, among all the 1073th ah plot points it will list down the latency in the decreasing order the the the plots with the worst latency that will come at the top and it will keep on decreasing. So, we see that these are the list of plots that have 2.8 and latency everything is 2.8 then we can increase the significant digit to the 50 and we see that this is ok it is same as we can even do let us say 100 100 and so it it tells us that ok it shows us that in decreasing order of in decreasing latency. So, it also tells us what is the transition ah the slope latency which is we do for everything we have a I mean specified in slope latency then this is the I think this is the rise latency this is the fall latency ok yeah this is the rise edge or or this is the fall edge this is the rise edge. So, minus plus I guess means that fall and rise and yeah. So, this is the fall this is the rise. Now skew is different if skew that is what ok let us do skew again now among all these timing path on this particular plot it will give which timing path has the worst skew that is why this vr pair appears there. It tells us that this path has the worst skew ah now this this this these two end points might not have the worst latency or the best latency, but among all the timing paths these particular two particular slots have the worst skew. So, there will be a timing path from either from this to this or from this to this and this is the worst worst latency I mean the worst skew ah this skew number is calculated as a difference of these two adjusted by the CRT RL. So, this is the skew. So, see the actual skew number. So, skew matters only when there is a timing path first important thing the clock tree synthesis tool will try and match the clock latency to work for all the clocks on the clock tree. Let us say for this clock has thousand centipede clock it will try to match these two numbers it will try to match latency path it will try to keep a latency unit within a tight range for all these thousand centipedes skew is the difference between the the clock latencies of any two clocks, but there should be timing path between these two clocks not all clocks will have timing paths with all right there are some clocks will not have timing paths to other clock. So, this skew number here minus types skew gives you the worst skew number and actual clock skew is always CRPR adjusted. If you take the value without CRPR the skew is 2.86 minus 1.8 and skew is about 1 nanosecond, but these skew has to be adjusted by the CRPR value otherwise it is not a real skew because of the delays because in the common clock path ah in the same path it is treated if the same cells are being treated taken as maximum in one case and will be treated in another case they have to separate the delay which is not possible physically that is why actual skew number is 0.27 which is good for this clock the actual skew number is 0.27 you can change the clock here you can do this clock and these skew here is 1.34 this is bad now this might also happen because of there is so if there is some generated clock logic now consider that ah a clock has a generated clock logic on it. So, there is a master clock and there is some generated clock on it and there is a another cloud of logic. Now for any generated clock logic CTLX will not will keep this generated clock logic out of the skew path it will not balance why because the generated clock logic will not have regular timing path ah a clock divider for example, will not have a regular data path. So, it does not need to be it does not need a usually if there is a generated clock and if it balanced if a clock that is generating a clock and if it is balanced with the rest of that group it will have very big latency and always we want to keep the clock latency to lower the lower the clock latency the better is the timing because of the OPD type you have to understand this. Consider this ah ah case and thought on this the larger the clock latency means the larger the delay from the clock definition point to the loss the larger the clock latency the larger portion of the clock free will be non-common. Increasing the non-common clock free path will affect your timing negatively affect your timing. So, all the tools will try to keep lower and lower it into a clock that is generating a clock from a master clock if the clock divider need not be balanced with the rest of the logic in such a such cases you can see some some skew numbers. So, skew numbers are just a measure of the clock free they are not a measure of the timing we will see timing afterwards. So, this is the command report clock timing which you can use to analyze the clock free this is not a very famous ah command this is not a very highly used command, but you should understand that ah such a command exists and you can hold some skew numbers and some latency numbers you can use. We use this ah ah command for a very specific case when you go to industry you might find some application that requires the use of this command. Now, there is one more ah ah command we we have already seen this command check timing. Now, let us run check timing here. So, check time is a very useful commands if let us say you forgot to define some clock check timing will tell it will tell here that there are some clocks which have no clock. I will show you a check timing report a verbose report which is without clocks I have not defined any clocks for a particular design. So, this is the kind of report it gives it tells me there are unconstrained end points unconstrained end points are because of the clock being absent plus it will ah give me a list of this is a check time verbose report it will also give me a list of registers with no clock these registers do not get clock checking no clock it gives the number and a list of register that do not have clock. So, it also tells an expandable clock that means, if you have ah clocks with real periods and they are not ah if the L team is pretty big or if the generated clock does not is not connected to the master clock in the net system or there is some difference between the generated clock definition in the net list of check then it will give an expandable clock that means, that it is not able to an expandable means it is not able to find out the period of the generated clock. So, it will give warnings here. So, this is a very it will give combination loops warning here it will give generated clock with the other warnings here. So, ah you need to make sure that check timing report is being you understand all the warnings here before proceeding to the timing reports. Now, let us look at report time now I will do again do report timing and minus no state. So, again it will give me lot of thing. Now, let us analyze one only one particular timing report ah and look it into it into detail what it all it has let us look at just now sys clock gives me this particular report. So, we have already seen ah. So, we now keep expanding the ah now here important point the first path here is launch by sys clock to x 1 by sys clock it is launch by sys clock to x it is captured by sys clock. Now, please note that a particular clock can get multiple clocks due to some some reason there are there can be many reasons. Now, let us ah first analyze so, how do you see ah how do you see that a clock gets multiple clock I will tell you about there we can know this by doing a check timing. So, check timing by default has is include list and a so it has a multiple clock option also. So, yeah. So, by default it does not check let us try and include this include multiple clocks. So, it will check so, it is telling me that timing is enabled multiple clocks for register set to true. So, if you set this variable to call then time time will give warning when registers have multiple clock, but right time is set to true actually it is possible in static timing analysis ah it is very possible it is used also that multiple clocks ah can reach particular register. Now, let us say there are two different clock sources which can reach a particular logic and they are depending on some muck selection. Now, ah as an amateur you might choose to set some case analysis on this muck and ah propagate only one clock at a time, but as you become more experienced you realize that you do not set any case analysis on this particular select time you let both the clocks through and so, you can analyze both the clock at the same time there is no harm in doing that it is actually it is allowed you to do that. So, that is why this variable is set to true. So, we will ah we will see this we will debug this later let us look at the report form again. So, now, see this that sysclock 2 x y there is a 7.5 call is that I mean capture is that sysclock capture is sysclock it has 15 this is 30 this is expected because sysclock is twice it is multiple sysclock 2 x is a multiply by 2 of sysclock. So, the edges are the period is expanded to 15 because the L Th is the theme for cases you can again verify this on paper ah for cases where you have long form of clock and capture by a 2 x clock or the other way round. The period you get is equivalent to full cycle of the faster clock or half cycle of the slower clock both are same in this case the faster clock period is 7.5 is slower clock period is 15. So, if you launch from one and capture at another the total period you get will always be equal to 1 period of the faster clock the 7.5 you can verify this you can verify this by making here the waveform. So, here the launch is at 7.5 capture is at 15 which is expected. So, anytime you have a launch and a capture between 2 clocks that are either divide by 2 or multiply by 2 the period you get is 1 period of the faster clock. Here the faster clock is sysclock 2 x the period is 7.5 what is the difference here 7.5 and 15 the difference is again 7.5. So, this is a setup check you can even do this the other way round this is clock let us see what is the worst part here the clock 2 x the worst part is the from sysclock to sysclock to x. So, again 0 and 7.5. So, again whether the launch is slower or launches from faster the period you get is 1 clock period of the faster clock. So, here it is 0 and 7.5 ok. Now, let us explore a couple of options in report timing. So, I will keep this report timing as it is I will expand it further. Now, there is a type there is a path type which is very useful. Now, this path type is default this path type is normal you can have a summary. You can have a summary path like this or and you can add things to it you can add input you can add net you can add transition you can add capacitance I will add these and see this is what now the timing report looks like let I have already explained this in one of the last, but let me explain something fan out when you give nets it will start giving fan out information also. So, we will know how and when it fan out again it will report transition and capacitance. If you are doing pre layout you will not notice this ampersand sign this ampersand sign is only for post layout it tells you that R and C is annotated for this and prime timing is doing delay calculation based on that. So, if you do not see ampersand at some point it means that prime time is not is either doing via load or not doing anything. So, you have to investigate that. So, you have to see. So, if you are made sure that you have no errors while reading the analysis if you have made sure that your report are not doing positive you do not need to look for ampersand, but I am just telling you for information that ampersand means that this is an annotated delay or calculated delay from step ok. Then now it will also show inputs of every step because we have a very minus input pins. Now clock network delay propagator this is very important here, but still we see that path is starting from the proctin of the launch clock. Here the launch clock is rising a trigger this is the launch clock operand vred and path is starting from this. What about the launch clock clock? Launch clock path is compressed here it is represented by a single statement clock network delay propagated let me open a quick video let us do we see that actually the path should start from this the path should start from somewhere from here clock launch path it should show as a launch path then data path and then the clock capture path, but here it is not showing you the clock launch path clock launch path is represented by just a single command single statement clock network is propagated. In case of pre layout this comes as ideal because you set the clock to propagated mode it is now propagated it is showing me a complete just a symbol delay value I will expand this further. Second thing again capture clock network delay is also propagated compressed there is no information clock uncertainty TRPR is fine now let us expand it. So, now there is a option called we will remove capacitor in position for a while we will add minus path type full clock this will show me the full clock path. Now see the report has length has increased now see it will start from the port this is very important now it starts on the port it is now showing me the launch path as well launch clock path clock goes to path shows me the incremental delay shows me the cumulative delay it goes to some clock MUX logic there is a see there is a clock multiplier here there is a clock multiplier clock multiplier 1 x this is a. So, every time it is showing the reference also this cell is of type this bug d 2 this cell is of type bug d 2 this is a net it is a this cell is of type MUX and so on and it goes to something it goes to OSITS 2 x clock and then. So, now and then it reaches yeah then it reaches goes through some logic and reaches this. So, here 3.304 it reaches at 3.304 now the time in report starts from 0 in the earlier case the time in report started from right from 3.04 because the latency of 3.04. So, by doing minus full clock you can do some you can expand the clock logic you can see the after launch path let me output it to report and we will see this. So, this is how you see the complete clock path right it also tells us what is what are the option that we take. So, this is how you see the complete clock path and second at the capture path now also you see this now here this is the this strange thing still the clock like source latency is coming out to be 0.98 in the launch path the clock latency is coming out to be 0 which is expected because it starts from the clock generation point. Whereas, the capture path say this is a generated clock says clock mu is not a primary clock this is a generated clock. So, still it did not give us the complete path or the generated clock this is the generated clock latency this is known as the generated clock latency, but it starts at the generated clock creation point which is this if this latency generated clock latency is 0 then there is something wrong. If you have defined a generated clock and there is a clock generation logic it should be time it should be correctly time then only it is correct. If the figure here is 0 there is something wrong and obviously, you will get some check timing messages you would also get messages using update time, but we did not get any messages and we have a proper we have some figure here right. So, it is correct and then we also see the clock capture path as well it also and that is it you know everything clock reaches the clock in here there is a CRPR credit given to you clock uncertainty and so on right. So, this is now how do I see the generated clock network as well there is a option called full clock expanded. So, the types for summary full clock and full clock and full clock and full clock expanded the one the default thing where the only thing is just the one figure that is the propagated figure is the full. So, they are summary full full means full data path full clock means full clock path full clock path expanded means full clock along with the generated clock report also. Now, let us look at the timing report the only thing that will change is for the clock now for the capture it is again starts at 0. Now, it starts at 0 it starts at the master clock again which is same 6 clock is same here it goes to path and then it tells us this is the g clock source this is the generated clock source. This is how you see and make sure and verify that is the new clock latency be calculated you do report timing and this is where report timing is so powerful it has so many options it gives you so many options to report. So, this is where we are getting we we got generated how this is how prime time calculated generated clock latency right. So, what is the generated clock latency from here this time minus this time 8.48 minus 7.5 which is 0.9 which is what we saw earlier. So, now it so since it shows the complete clock propagation it does not show a combined latency figure right it is not showing a summary latency figure there because we have used the expanded option. Now, let us show common ok now let us talk about CRP now let me report a simpler report I will say minus look 6 clock and from get clock 6 clock. Now, this is where I am saying that report timing give you a report the launch 6 clock and the capture is also 6 clock. So, capture is controlled by the group option launch can be from to 6 clock get clock 6 clock. Now, here I have not done minus expanded that is all right. Now, I see ok I see some figures here I see that launch that 0 capture is at 15 which is ok and I see all the delays time. Now, let us talk about CRP for hold for setup this is a set of report setup it will give you the credit and move the capture edge to later point in time. Capture edge after network delay 17.63 it will add CRPR it is giving you credit anything that moves your capture edge later in time for setup check is helping you I will do this for hold CRPR value it will move the capture edge back in time anything for hold if it moves your clock capture edge back in time is helping you giving you credit if the CRPR was not there this slack would have been worse by 0.19 minus 0.87 minus 0.19 this would have been the slack if not CRPR if not because of CRPR CRPR is reducing the slack by 0.19 right. So, this is how you understand CRPR figures let us go back to setup report. Now, let me give you something else report delay calculation this is a report CRPR command I can say report CRPR from now CRPR is between clock. So, you can do this and to this any to launch and capture you can do a report CRPR and it will now tell you something it will tell you first what is the common point and does it also report the common point using something. So, let me also do a report timing and minus path type pull up and yeah and I will do a reports yeah yeah. So, this is the common point this is the clock common point which is I Blender and buff BD G6 B2 IU. So, we see that this is the common point. So, in fact the common point is right before the capture edge and for the launch this common point is this is the common point and it diverges from here. So, it is telling me that this is the common point which is from this figure this is the this is the common point we are talking about the after 1.2 NS on the clock network which is the common clock path. It also tells me what is the launch in at common point what is the capture edge rising rising arrival time early late now this early and late arrival timing are only because of mostly because of it can be because of different parts also, but nearly let us see the path here the path is going through a MUFS yeah. So, it can be because of different path or it can be because it is not because of different path because the common clock is the common path is common it is meaning. So, it is because of CRPR it is because of the delayed values we have given derived as 1.1 and 0.9. So, it is telling me that let us only worry about the right edge because the launch and clock capital are both rising it is doing it for both calls I will call. So, early is 2.29 late is 3.21 the actual delay is between these two values. So, the actual delay is most probably early is 2.29. So, what I will do I will divide 2.29 by 0.9. So, actual delay is 2.54 and about 2.54 and 2.54 into 0.9 is the early delay which is 2.29 and actual delay into 1.1 is the it is strange 3.31 I have to see what it is I have to double check. So, ID is 2.29 because it is related let me take the delayed value it is 1.1 and 0.9. So, it is 2.29 is the early the latest 3.31 and the CRPR the difference is 1.02 which is giving the edges match time which has rise and rise edge and CRPR value of 1.02 is given back to you. So, this is how you debug CRPR number that you have to otherwise everything is going fine then. So, just make sure that whenever you are worried about clock skew you have to take into account CRPR value because clock skew actual clock skew the real clock skew is the reported clock skew adjusted by the CRPR value right. So, for example, in this report particular report you say that clock network delay complicated is 2.63 this is 3.7 to the skew is more than 1 minute, but the actual skew is that number adjusted by 1.0. So, the actual skew is pretty good in this case. So, this is how you debug CRPR. Now, let us talk about delay power, talking about delay power come back to delay power. Before timing is an option where you can give minus delay and it will also start reporting delay. So, let me yeah. So, now it is telling me that we will let us give minus clock in a clock type full clock and delay delay. So, here we are given minus delay now it is also started showing me the delay number. Now, I have given the late delay to be 1.1. So, it will multiply all such timing. So, this is already multiplied timing it is showing me the delay. It multiplied all such this is 3 after multiplication these days after multiplication. It multiplied the launch clock edge plus it multiplied all the the data parts by 1.1. So, everything in the launch part in the first part of the report will be multiplied by 1.1. It is already multiplied it is just showing me the multiplication factor. Everything in the capture is already multiplied by 0.9 because it will be early part. So, remember for setup the launch clock path and the data path are taken as maximum. The capture clock path is taken as minimum at early. So, this is early right and at the end it also gives me a delay report summary. Total delay required time is 0.29 arrival time is minus 1.21. Total delay slack is 1.11. That is telling us that the total delay applied in the required time is 0.29 by multiplying it by 0.9. So, all the figures the delay effect is 0.29 for the required edge for the capture edge. The delay effect is 1.21 for the launch part. The delay effect is more because the data path is delay plus it also has a launch clock path. The the required time only has the clock capture path that is why the delay effect is less. Slack is 1.51. Slack with delaying applied is 5. CRPR due to delaying is minus 0.56. Slack with no delaying that means if there was no delaying if there was no delaying what would have been the slack. The slack is without the delaying is 5.95. That means how did it come up with this number? 5.95. So, this is the total delay. This is the total slack delay. If the delay was not there then CRPR would have been not there and the CRPR credit should be again adjusted. So, 1.51 is a total delay. This is applied. So, this is minus shows it is a delay delay in the arrival time. So, total delay is 1.51 plus slack with delaying applied is 5 minus 5 point. So, it will be something like this 5 minus 0.56 plus 1.51. So, this is the slab without the delay. How do I achieve? I will repeat again without with the delay this slack is 5. Now, what are the delaying applied? The rate says 0.29 for required 1.21 for arrival sum is 1.51. We add 1.51. This is the 1.51 is the time that the rate has consumed. 5 is the slack of the rates. So, 1.5 is the time consumed by the rate we added. So, slack would increase, but now the CRPR credit is given back to us because of the delay. If we do not apply the rate the CRPR credit will be taken back. So, I will subtract whatever CRPR is given. This is the way it arrives which are number. So, this is the this is how you can also see the effects of the delay in report timing. Please remember without the rates the OCV does not make sense right. There has to be some delay to model the on separation. So, this is how we do it right and applying the rates setting the analysis condition as on separation and CRPR they all come under a single methodology of on separation. So, this is how you see the denoted clause this is how you see the denoted clause expanded report you see the the rates you see the OCV, you see the you can do a report clock report CRPR you can do a minus direct option see all the direct values here and so on right. So, this is all the calculation about the report time. So, we have seen now let us let us look at report delay and now let us look at ok first look at the delay in report. Now, we are looking at min edge is as 0 and 0 now change is for hold for hold the launch clock path and the data path are made to come early. So, they are multiplied by 0.9 for capture part is delayed. So, it is 1.1 here it is showing me how much slack was. So, this is validating by 0.87 it is showing me what is the effect of the rate here and it is adjusting using the same formula that we use for set up it is showing us slack with no derating. So, we see that derating in both the case of set up and hold it will make the path work right. Now, you can do something like let us look at the timing report a simple timing report and let us do you can at any point of. So, at any time if you want to see how did the prime time calculate delay you can do something like this report delay calculation minus from any pin to any pin. Now, let us say I am doing from the input of a particular cell to the output of the same cell right this is where I am asking prime time to tell me the delay calculation for the cell delay. So, if I do this then it is telling me that let us again redirect it. So, this is I am now focusing on a particular cell from pin. So, it is telling me the units it is telling me this library it comes from it is telling me with cell we are talking about we are talking about an idle cell between the in and carry out it is telling me it is a positive unit. So, it is telling me for the positive unit first it is telling me the R C network. So, it is telling me that number of elements on C O R C caps and two resistances. So, it will add the total this total cap resistance is the pin cap plus the whatever cap it sees from the R C network total resistance then here it is telling you what is the input transition time what is the effective cap what is the trigonestance what is the output transition time and the cell delay this is where it calculates. So, it will not show you the actual algorithm and how many it is obviously provided, but it will show you what is the input transition value what is the output value for the particular cell it will now show you for the. So, for all the it will show you from input to output it will show you for all the time in time that are defined in the library. So, for here for example, the first part is it is telling that R C delay calculation is still because R C delay calculation was not used for time over time. We are more focused on the cell delay here. So, first one is from to this R C is positive unit. Now, it is telling us that here there is a condition positive unit, but the condition is a 1 and b 0. So, it will give us for all the condition this is the condition a 0 and b 1. So, for whatever data is defined in the library .lib using that data. So, there can be a conditional data also timing type depending on the when condition on some input condition you can define the data for all such conditions it will output the delay calculation. Now, I can also do delay calculation for a particular net let us try that. Let us again look at the timing report and let us see now delay calculation minus from the output of a particular cell to the input of another cell. Now, here I am not sure what this message is, but because the R C delay calculation is not used this is delay I am not sure what this is. But looks like there is some delay calculation because there are some there are some caps and there is a senses. So, it will tell what is the net delay what is the provision time prompt and transition time looping transition time and so on. Because this is now not we are not asking about the R type is net it will not sell right. So, it is telling you what is the R C network it is telling me this message might be related to the CCS model like this we are using the MLDM model. So, it is it is. So, for any section of the circuit of the design you can do a delay calculation by using the report delay function. Now, let us look at one more option in report timing for report timing let us look at the. So, report timing has the I guess the most number of options. So, there is something called PDA mode this is what we discussed. We discussed the graph based analysis where the cube calculation time time will maintain one skew number. So, one skew number which is for the worst skew for cells which are multiple inputs or time time cannot keep the complete data. So, what we could do that is ok let us look at the worst violation both let look at the report constraints minus all validers what all violations yes and now analyze the design for violation. So, right. So, till this point we have understood about the report timing about the all the options all the famous options that report timing supports. We have already seen in the earlier lab about the inverse about the MOSFAR about how to get the MOSFAR groups today we studied about the full clock the full clock from the minus rate PR PR so on we also learn learn about the delay calculation. Now let us see let us focus on the looking at the timing violation right what all timing violations are there how many types of time violations are there. Now let us do a report delay calculate let us do a report constraints minus all validers let us. So, there are so many violations here this one most of it most of it we do when you are writing to a report with the all all clock. Now this is what so once you verify that you have applied all the constraints you have set the operating condition as it is more perfectly your power factor weighting is correct your clocks are correct your clock relationships are correct. Then you come to your are you write some kind of report which tells you somebody of all the violations this is that report all the violations of MPT. Now it is telling me that PCLK has only one endpoint that is valid in for hold it is first ok ok it is telling me naturally there is only one violation. Now so, because it gives all the match delays as it was then it is telling me mean delay hold clock dating there is one violation big violation this is a big violation might be caused. Min delay input group there are so many violations we have not really specified any input today. So, I will we let us not go let us not give much importance to this again. So, now PCLK has these many violations in hold again FDR clock has these many violations for hold this clock has these many violations for hold a lot of violations for this clock and so on. So, it will give me give us again this clock to it for so many hold violations removal there are so many violations removal is of a hold type recoveries of a ticker type. So, report constraints minus all validers give that a good summary of how many timing violations are in their in their design and now we have already mentioned that we are doing corner it also give us the the max trans violation. So, this is a max trans violation. Now we have seen that we talked about corner based estimate and we discussed that there will be multiple corners on which you do SBA. So, I believe on every corner that you do SBA you would have to make sure that there is no set up and there is no hold violation cross sign off there is no DRC violation. Now we see that there are some hold violations in the worst corner that means these hold violations are going to get bad they are going to get worse when you move to the best corner. So, this this constraint fine. So, probably you would want to separate out this constraint file into two files one file which will define the environment condition like this and second file it actually defines the clock. The second file will be common for the constraint file without the environment condition will be common for all the all the corners worst case best case corners because they do not change the clock definition will not change, but the first file which defines the link library will be different for different conditions. So, you do now do when you do the best case analysis which here you read the min dv and then you do the analysis. So, but I see that here there are lot of hold violations and the hold violations will get worse when you move to when you probably move with the best performance. Now let us look at one part for example, report timing we saw that there is one set of violation in the in the timing. So, we see there is one violation in the p clock broken set of violation in the worst case corner. So, if I make sure that this violation is not there then I I will only have the hold violations to take care and then I will probably go to the best case corner and do the analysis there. Now, since I have only one violation left I am very tempted to try out pba. How do I try out pba? I say minus pba I do not do it for the complete group right. So, what I will do I will I will narrow my choice first I have to narrow my choice I say group in pba and minus flat. So, lesser than 0, let us say for any any clock even you have let us say more than number of violations this is generally proposed this is I am talking about. So, report timing minus group a particular clock slack lesser than 0 will give me and I increase the number of parts to let us say 5. Now in this case there is only one part, but again this approach is going to report I am talking about. Now for such case where you have let us say you selected a few number of parts with slack lesser than 0 now you can give pba mode and give exhausted. So, the option can be exhausted. So, you can exhaust it. Now see the slack is decreasing although it has not given us a clean report, but it is saying recalculated 5 parts why because we gave max 5 returned 1 parts it it it first initially had 5 parts returned 1 part because only 1 part was satisfying this criteria. The maximum number of parts recalculated is 5 I do not know it sometimes maybe the internal bottom lift takes to look at the max part 5 it recalculated it recalculated the function number and this will give or this gave a better slack. So, it gave us some advantage, but not as good it is not a great advantage, but still it gave us some advantage in some of the parts it is a very very long it will give a lot of advantage. If you have a very long data part it will the more the longer data part you have the more pba will give you advantage this is that is why you see what are such a critical part, such a critical part are you giving the part which have later logic depth which have more number of stages. Such parts pba will go give more advantage because such parts will have cells with multiple things and obviously some transmission approximation because of graph-based analysis. Again the thing to note here is that pba is reports the slack will always be either better than or equal to the graph-based analysis that is why we say that graph-based analysis is significant it is more conservative because pba is accuracy improvement over graph-based analysis. Second the hold when a hold path is critical hold path is critical when the logic depth is less when there is less delay. So, pba will probably not give you a lot of advantages for this why because the logic depth still is small there are just 3 or 4 maybe 2 or 3 stages in the data part. So, not not a lot of pba advantage. So, this is how we do a pba analysis. So, next in next lab session I will talk about how to fix setup and hold times what also check before fixing setup and hold time. We will talk about class of commands which come under what is analysis in time time this is very very it is a slightly advanced lab, but it will be very very useful when you go going to the industry and work. So, this is so till this point we have learned about how to set up the time limitation, we learned about parasitics we learned about the constraints we learned about different reporting commands. In the next one we will explore how to actually fix time limit we will talk about more. Thank you.