 Hello and welcome to the series of today lectures on the subject digital techniques for secondary IT students. I am Dr. Rishal Gajbar and in this today lecture we are going to implement forest 1 multiplexer circuit by using veriloc sdl language. At the end of this session you will be able to implement forest 1 multiplexer circuit by using veriloc sdl. You will also be able to write the test bench in veriloc to verify the module correctness. So, the software that we are going to use for the simulation purpose is model sim student edition. It is a free of cost software and you can download this by using the link which is provided here. This is the workflow for our session. We will first discuss the veriloc module for a circuit which is forest 1 multiplexer in our case. Then we will discuss the test bench for this circuit for verifying its correctness. Then we will verify the simulation results in model sim finally. So, the diagram here shows the forest 1 multiplexer. The forest 1 multiplexer is a combinational circuit which has 4 inputs and only one output and to select any of these 4 inputs we require 2 select inputs which are represented here using s 1 and s 0. S 1 represent the MSB whereas, s 0 represent the LSB of the select inputs and depending on the select combination which you provide here the particular input will be. So, the output will be connected to particular input and that input will be available at the output. So, this is the function table which represent the operation. So, here you can see for the input combination 0 0 at the select input the y is equal to i 0. So, what is the meaning that whenever you provide s 1 equal to 0 and s 0 equal to 0 this y will be connected to the i 0 and whatever is available at the i 0 that will be available for the y which is our output and similarly you can also see the other input combinations also. So, for 0 1 you get y 1. So, for 1 0 y is equal to i 2 and so on. The same function table you can represent by using this logical expression. Now, let us discuss the variable of module for 4 s to 1 multiplexer. So, the module definition will start with the module keyword, MUX 4 1 is the name of the module and inside the bracket we provide the list of input and output. So, in this case I am providing input underscore lines comma select underscore lines comma y. So, input lines comma select lines comma y. So, these 2 are our inputs input lines and select lines whereas, we have only one output which is nothing but our y. The select line in this case. So, since we have 2 select line we are going to represent it as a vector. So, this vector select line is represented as a vector here. So, this vector representation is shown here. So, here you can see 1 colon 0 inside the square bracket and input is the keyword which represent that the select lines are the inputs and this one represent that the first bit is the MSB of the select line that is what the meaning of 1 colon 0 in this case. So, similarly the input lines there are 4 input lines. So, that is also represented using the vector in this case. So, input space in the square bracket 3 colon 0. The meaning here is that the third bit will be the MSB and the 0th bit will be the LSB of this select lines sorry for this input lines. So, here we have defined inputs and output is defined as output space y then output y is defined as a reg data type. So, reg space y the select lines are represented as wire data type in these 2 lines. Why? Because here we here in these 3 lines we are just representing what is input and what is output. So, input and output we have defined explicitly here and the data types are represented in these 3 lines. So, output is defined as a reg data type whereas the select line and input lines are represented as the wire data type. Then we will write down the always block. So, always will be written using the always keyword. Always block is like a while one it is going to execute continuously. So, always at the rate inside the bracket we are going to provide the OR operation between input underscore lines or select underscore lines. The meaning here is that for any valued input these input lines or select lines take this block is going to get executed. Then inside the bracket we are going to write down the case right. So, case statement. So, the case statement will be written as follows. So, case is the keyword that will be used. So, all the bold letters in this case are nothing but the keywords bold and lower case all these are the keywords of the V-relock. So, case inside bracket you are providing the select lines which is the select input in our case and select lines. How many select lines are there? Two select lines are there right. So, we have to define the 2 bit binary number in this case. So, the first case will be represented as the 2 dash B 0 0 here 2 represent that it is a 2 bit binary number dash B represent it is a binary and 0 0 is the value. So, the first combination is 0 0 and we know that for the select line having the value of 0 0 that is S 1 equal to 0 and S 0 equal to 0 we have to assign output Y as the I 0. So, that is why it is represented as it is. So, it is a vector notation. So, by using the indexing we are accessing the I 0 in this case. So, we have written Y equal to input underscore lines in inside the square bracket the index is 0 for I 0 right. So, and so on. So, for in for the input combination 1 1 what should be the output Y? The output Y should be 3 right I 3. So, that is why it is written as Y is equal to input underscore lines inside the square bracket 3. So, this case will end with the end case keyword whereas, the module will be completed with the end module keyword. So, this is the verilog module definition for 4 S to 1 multiplexer. Now, let us discuss the test bench for 4 S to 1 multiplexer for verifying its correctness. So, it will also be a module starting with the module keyword this is the name of the test bench that we have given test marks 4 1. Now, here the roles of the inputs and outputs will be reversed than its verilog definition. So, here the inputs will be defined as a reg data type. So, reg inside bracket 1 colon 0 select lines the meaning is that select lines is nothing but a vector having the two bits and it is defined as a reg data type. Similarly, output Y similarly, input lines are defined as a vector of 4 bits using the reg data type and output is defined as the wire data type using wire keyword. So, here we are instantiating our 4 S to 1 multiplexer. So, MUX 4 1 space MO MO is the name of the object and inside the bracket we are providing the list of input and outputs. Then we are going to write the initial begin statement. So, this initial will start the initial block and there are multiple inputs that we have to provide. So, since there are multiple statement we are going to enclose them inside the begin and end block. So, and here you can see the first input combination is. So, only few combinations are shown because of the space limitation you can take in your actual program you can take all possible input combination and verify the correctness of your module. So, the input lines in the first line are defined as 4 bit binary number. So, 4 dash B 0 0 0 0 and select lines are defined as since it is a 2 bit binary number 2 dash B 0 0 and I have given the delay of 100 units. So, I have given 4 combinations you can take all possible combinations. So, this begin will end using the end keyword whereas, the module definition of our test bench will end with the end module keyword. So, before going to the actual simulation pause the video for 1 minute and write down the answer of the given question. I hope you have written the answer. So, the third bit is the MSB since the input vector is declared as input space. So, input is the keyword in this case inside the square bracket 3 colon 0 input lines the meaning here is that the third bit will be the MSB bit whereas, the 0th bit will be the LSB bit. Now, let us see the simulation I have already written the program. So, this is the module definition that we have discussed in the slides this is the test bench that we have discussed the first job is to compile the program. So, go to compile select test max 4 1 dot v compile. So, just check whether your compile is successful or not and one can see that the compilation is successful. Then our next job is to go to work library go to test max 4 1 go to simulate. So, this window will open here then go to the we have to add the waveform. So, go to add 2 wave all items in region here you can see that the select lines as well as the input lines are vectors select lines have 2 bits whereas, the input lines have 4 bits and there is one output and the next job is to run and since I have only provided the 4 combinations in the input. So, only 4 combinations will be here. So, let us discuss one of the input combination. So, for the first input combination the select lines have the value of 0 0 whereas, the input lines have the value of all 0s and in this case since test select lines are 0 0. So, whatever is available at the i 0 that should go to y and since i 0 is equal to 0 in this case i 0 is equal to 0 in this case you can see y is also equal to 0. In the next combination the select lines have the value of 0 1. So, in this case whatever is available at the i 1 that should come at the y and in this case you can see y 1 input line that is i 1 is taking the value of 1. So, that is why y is also equal to 1 in this case and in the next in the last combination you can see that the select input is 1 1. So, whatever is available at the i 3 that should be available at y the i 3 in this case is represented as 1. So, that is why your output y should also be equal to 1 the same you can observe here. These are the references. Thank you very much.