 let me give you extend this master page ok now the master page is mapping master page ok it is also called l1 table ok the master table or l1 table it is actually mapping available virtual space we have ok 4GB of available virtual space this virtual space available virtual space of 4GB is 15 to 1 MB each ok of 4096 entries ok it varies from 5, 0 to 4095 so each of those 190 spaces are fitting to multiple 190 space and how this virtual spaces the virtual memory areas are considered is and where it is located is represented in the table ok so every every every 190 space of the virtual space has an entry in the table ok so this number of entries are 10 4095 ok and each of them occupies 4 bytes of space each entries in the table so totally there will be 16 kilobyte of l1 table so once we have a table which will make which will take care of the complete 4GB space that are available for the program memory then we can play around with that we can say that may be I can if you know you can have anywhere in this but the physical memory can be in a particular ok or same physical you know virtual space could be mapped to different location in the physical memory ok based on which process is running so for an example suppose user is you know I told you know this bottom spaces are always directly mapped so it may not go to MNU so it will be there will be a space in the physical memory the bottom some locations may be reserved to make sure that it is 1 to 1 mapping is there because always the vector table and wires are there in the bottom of the space which is a higher address so which will be not having a MNU of a physical space except for that anything that is on generate the virtual address is coming they will map to 1 of the entries in this and then now that the entry will decide whether it is directly know pointing to 1 empty space in the physical memory or it maps maps to it points to a table another table which is called 82 table and which you know use a MNU latch granularity in terms of access permission of that 1 empty space see each entry here of you know a set of 1 empty space in the virtual memory ok that 1 empty space could be directly mapped to 1 to 18 in the physical memory or it could be going towards you know with the entry entry in this case what happens is it is fitting to suppose if you are saying that 1 empty space then 1 empty will be having how many entries 124 entries so out of 124 entries I may decide to have only half of it pointing to the real physical memory and the rest of the entries may say that you should generate a fault that means that the space is not available or you can say that all the entries are available but they have different access permissions so effectively as a summary 11 master table has to be there in the system and it needs to have the 4096 entries and it should be physically there in the physical memory ok so that you will know when any of the addresses are generated whether it is a valid entry or not ok I will explain that is suppose another physical owner virtual address is not physically present we can make an entry here to say that generate a fault in this address and this address is generated so we have to make sure that all the available 30 value 2.2 addresses are addressed in the sense what needs to be done when that kind of address comes that should be handled so this 11 master table that is why it is built as a 4K entries ok 4K entries are 4K entries so it is 16K of that type and each are done taking care of 1MV of space ok 1024 KB of space size means 1MV of section so that 1MV physically can be there in the memory it could be not there at all then you will have a fault entry or you may have point 2 and have a table which may give a final granular details about that state 1MV section now let us not talk about L2 now focus is on L1 and that is what I am addressing now and just to a continuity state let me tell you how these values are mapping ok now you will understand why is this 4K and why is this 15K kilo beta part size and then you know that it is taking care of 1MV space now let me tell you in the fine table it is of course you know fine table means the size is 1KB size ok it is taking care of 1MV 1KB size ok so if a table ok the L2 table always 1MV for 1MV of space the extra memory space 1MV space ok if I say that each table entry takes care of 1KB of space how many will be there 1000 will be there right so 0 to 1023 entries will be there each have done taking care of 1KB of space 1KB of space size ok now 1KB of size I have I can also say that so 1KB of size means about the 1024 entries and I said that 1MV takes 4 bytes of space so it will be 4 kilo byte of space size ok the total L2 space size is the L2 table size L2 table size is 4 kilo byte ok now what happens if your space size is 4 it will be 4 consider the entries will be giving the same value will be having the same value of access permission right for cache behavior if it is a 64KB space size 64 consider the entries will be assigned with the same entry that means it will all have the same behavior in terms of one page has to have the same cache so if it is a 64KB of page size then we will have all the 64 entries of 1KB kilo byte space sizes will have the same attribute I will tell you how the attributes are entered in the page table but that is what how it is done so I hope this page table entries you will be you are able to understand now what happens to the course table course table means the page sizes are bigger it is either 4KB size or 64KB size which is also a L2 page but instead of 1KB this is changed to 4KB of size that means each entry in the page table of L2 page table corresponds to 4KB of size page size in that case 1NB space there will be how many 4KB of the entries will be there in 1NB 2NB space because one fourth of what you saw in this time table that is you see 2NB entries in the L2 table is the L2 is a course table pointing to a 4KB page size in that case how many what is the total size you will have if it is 256 entries into 4 bytes each it will correspond to 1KB of size so that L2 page table size will be 140 and similarly it also supports the 64KB pages that means you are 36 16 into 4 is 64 right so 16 consecutive entries in the L2 course table will have identical entries to support the 64KB pages similar to what I said about supporting a 4 or 64 in the time page table so I hope you understand the entries different entries what they correspond to let us go forward now there are 2 levels of page table L1 and L2 there is a single L1 page table known as L1 master page and that can have 2 types of page table entries one is it directly maps can connect to a 1NB space in the previous memory any space any part of the physical you know the same 1NB space okay there will be for every 1NB of virtual page there is a 1 entry in the L1 table may have pointing to another section with you know it is a 1NB of physical memory all this 1NB is somewhere it may be located that where it is located will be there in the page a value but it will point to a physical memory of 1NB or it can descend to point to another page 1NB of another 1NB of space in a virtual space may be having a 1NB which may point to L2 table it may point to a starting address of L2 table which we say has where that is located and how the behaviors are and what is the phase space of the particular section so the master L1 page table divides the total available 4G space into 1NB section available 4G virtual space is placed into 1NB sections so it will have 4096 page table entries and there is that many entries will be there but remember that the page tables are always on the boundaries of the sizes so what I mean by that suppose okay let me draw it suppose we have you know L1 master table master table itself has to be on 16 kb boundary I will explain this in the next session because the size is 16 kb similarly L2 5 table size is 4 kb so it has to be on 4 kb boundary and L2 4 table size is 1 kb so it has to be on 1 kb boundary okay what I mean by boundary address you all understand so let us go to this now now location of now as I told you it is on there I can locate it anywhere in the physical menu okay L1 table itself okay but it may it will be mapped one on one so there is no need of MMU to access it but it can be anywhere in the physical menu it may not be even the lower space it can be in the higher memory space also as long as it is mapped directly without MMU you can access the table let us assume that it is on the lower part of the memory typically OS and all tables are lying in the lower end 0 is here now what is the size of L1 table it is 16 kb correct now 16 kb occupies how many bits of addresses you said you know that 1 kb takes 10 bits correct 10 bits of address so 4 kb will be and the 2 bits 16 kb will be 14 bits of address space so the first the lower 14 bits will be 0 because anything after that only the addresses because it is on the boundaries of 16 kb so starting from maybe 4000 heads why 4000 the first 3 nibbles will be 12 bits and then rest of the these 2 bits also are 0 so 14 bits are taken care of so starting from 4 any bit any value pattern you can use in the higher values to locate that 16 kb of L1 page table why do we need a register like this because this we can be accessed using the co-processor and the hardware MMU okay MMU while accessing the L1 table it can easily use this register somewhere and then you can use that address along with the page whatever address you know which is space is coming based on the address it can index into the table that is why we need to index into the table okay so for that we need to know where the table is starting then so the starting address could be physically anywhere so that is stored in the register it can't be anywhere else it has to be in a co-processor register when you whenever it wants to access the L1 table that is why you are seeing that it is on 15 kb boundary so it is lower 14 bits are 0 I hope this is clear to you now let us see the location of L1 must be set to set by writing into this register so once we decide like where we want to keep the L1 page table that address can be written in this register then what happens automatically MMU when it is translating the address it will get the base address of the L1 and then based on the physical address that is coming from the processor it will index into this table and to find out what is the mapping for that particular visual address in the presentation so the CT between CT register holds the translation table base address this is called translation table base register according to the location of the master L1 table which can be written which is also same as physical address I told you that to access the page table we cannot use the MMU so it is same as the physical address L1 needs to be located on 16 kb boundary in memory where L1 table space is also 16 kb so one sample instruction is like this so what is this MCR we can have some value either R1, R2 or anything which is actually having a lower 14 bits having 0 and then remaining bits are having some value address which is pointing at the physical location physical memory location where the L1 table is talking and what are these registers this is the CT register and then we are telling that whatever is the register is having the value take the lower bits bits and then use them to access the page table who will be accessing the page table the MMU so we are we are setting up but entry page table entries are filled up by the wire so it has to keep somewhere in the location main memory and then it has to say where it has kept the page 1 page L1 table in the physical memory that is all now once this register is pointing at the starting of the register of the page then the remaining bits can be accessed based on this location and then you may have to multiply by 4 because each entry is going to be taking 4 bytes so the location the entry is accessed if now I will show you each entry correspond to what but if suppose the entry has a lower it means a section entry that means this 190 space what is this 3 3 is the third 190 space in the virtual memory first 190 where it is pointing at is given by this entry another 190 this is the virtual space another this is after 190 this 190 where this is located whether it is a pointing to the referred to a L2 table and then pointing there or directly a section entry will be where it is located also will be mentioned here so this entry is shown so that means the fourth 190 hmm that is 0 to 1 and 0 to 3 starting from this 4 this space 4 and this space is what is a section entry so this address will say this physical address which maps to 4 and 4 you know these 3 to 4 in this space is maps to which part of the physical address is given by this space okay that is why you see that 20 bits are offset is there because within the 190 190 is what 20 bits will correspond to 190 space so it will index into this 190 so this is how it is mapped I hope this is clear to you now let us see what are the part of the entry see it could be a section entry that means what it actually says where is that 190 is located in this space and then it will have only one access permission because all the 190 section is treated as the only entry so it will have access permission here and the domain is the another level of control and then what are the degrees of pattern and then the lower if it is if the entry has as a lower to this then the MME will consider it to be a point into a 190 section directly it does not point into another entry space entry but if it is a 0 1 or 1 1 that it corresponds to a course space entry which I told you that to L2 tables of size different sizes and course table is actually 4 kb of page sizes so offset will be so the 4 kb of page size next how many page size what is the page size of the course table it is 1 kb correct we saw that if the page size is increases if the page size is increased then the table size will come down so it is 1 kb size so it is matched on to some location which is the 1 kb boundary so actually these entries give where the L2 table size it is a starting address of the L2 table then within that how those 190 spaces access permissions are given you have to go into access the L2 table it is only giving the base address of course table if the L2 table is a fine table then the lower which will be having 1 1 and this is fine table it is a 4 1 kb pages 1 kb pages then how many entries because there will be 4 kilo 4 k entries will be there because it is corresponding to 1 nb 1 kb is corresponding to 1 nb and how many entries it will be there but it is actually 4 by 3 so 4 kilo by it of the time okay so that is why it has to be on a 4 kb boundary so 12 which will be not in the earlier this is the starting address of the L2 point page table starting address okay because it is on a 12 bit boundary because the size is 4 kb so if the page size is small the size will be more if page size is bigger the size of the page will be small so accordingly the size of this is occupied so these are starting address will be different now why this is required with all this 0 it indicates that that virtual space of 1 nb is not mapped to any valid space in the system see if you can represent all 4 gb okay if your valid space is critical memory then you do not need an MME at all right you have all the critical memory of 1 4 gb that is not the practical case all 4 gb is not meant to be represented in the physical space so but virtual space will have all 4 gb so we have to have entry whichever is the hole where there are no memory available in the system you have to make an entry like this so that in case if arm process is generated such an address it will be caught that means it will if a fault happens then MME will be generated data about a free space to pack that data so this is clear to you so this is the 1 nb session okay and this is the 4 gb boundary this is of course L2 space table size is more the table size will be that number of entries will be less so the table size will be automatically less that is the 4 gb boundary because the size is 4 1 gb and if it is 5 gb it is the 4 gb of size it will be on 4 gb boundary okay the fault will be generated that is what is here but why there is nothing entry here no entry here it is actually not finding to any section or it is not finding to any table so as soon as the MME looks at this it is a don't care MME does not even look at this entry in this space now that it is where there is no valid entry there is no which space is not nothing typical so MME generates a fault okay good now there are 2 different components to manage the task primary control is domain so in this space domain is here domain is 4 bits are allocated for that I am explaining the 4 bits where is the access permission bit so domain control basic access to the virtual memory by isolating one area of memory from another and carrying a common virtual memory map so this hole as I told you this l1 page table has is matching the whole 4 gb of virtual memory into some spaces in the entries in the l1 master table so it has actually each area of domain we can give a different domain and then control it differently when domain is assigned to a section we must obey the domain access rights domain access rights are assigned to another register these are domain access rights okay I will tell you this register is having a 0 to 15 16 domains are given see in the page table entry you have only to say that a 1 mb section which domain it belongs to okay it may belong to domain d4 or it may belong to d11 you have only to say which domain it belongs to a particular 1 mb section but what that particular section refers to what is its access rights are is given in this bit so each of them are occupying 2 bits I will explain you what are the differences in this that could be there so you will know that how this domain can control a particular section of the memory so this controls the course of it to access the sections of the register memory now these are the entries okay if it is the 1 1 access is uncontrolled that means that section can be accessed by a engineering privilege mode or in an user mode but 1 0 is unpredictable okay it is not defined 0 1 means access control by permission values set in ptm so if it was a 11 page table okay it is a section if the domain says it is 0 1 then if you remember there was a AP field also in the L1 master table until AP access permission so as per the access permission the control will be access permission to that 1 mb of section will be controlled by the AP field in that particular ptm okay so or it could be a L2 table this will also have a domain which is mapped to this then it will go by the access permission given in the particular ptm otherwise it is an uncontrolled access so it is required sometimes to have a uncontrolled access to all the sections so we can use this particular domain entries to achieve that okay because once you change one domain because I have so many entries in the and then I want to control all the access using the domain entry I do not have to go to every ptg entry to change those because I would have given the same domain suppose I have given domain access initially to say that please go by what the ptg says okay that is one way domain so suppose if I have given a domain note for all these entries domain has d13 okay so then what happens if the domain value says it is 13th domain then that will be here will know there will be so many entries with the domain 13 in the page table all of them will fall under so if I come here and change initially I have given uncontrolled and then later on I make it to 01 what happens it will all be controlled by the ap then suddenly I want to decide that don't go to ptg access permission I want to have uncontrolled access to all the pages in the system I can I need to do only a change in this particular domain 13 I will make it 11 I write it to introduce in this scope as the 11 then what happens the page table entries are not considered all okay they will remain there but they are not considered for access permission and we will have uncontrolled access so OS can have a control on multiple pages by just changing the domain entries here okay it means little bit of thinking to relate to it please remember first access to a ptg page table is seen and then based on the domain what it is said okay we could have represented one of the 15 domains we could have given and then based on the domain entry a page table access permission are considered so all the entries you know any anyone as far as A2 will have both domain as far as the page table entry access permission will be there whether to consider this access permission in the page table entry or to have uncontrolled access is what the domain is deciding I can put some domain values in some set of pages and then if I come and give those values to either 0 1 to 1 1 or 1 1 to 0 1 then I can have access to all the pages with one minor change okay this is what is the need of the domain so one program can be a client of some domain and a manager of some other domain and have no access to the remaining domain so program it will say it could be given as a different domain and that control also you can have okay that is what about L1 page table and domain now let me tell you what L2 as I explained to you these entries I have already explained so let me go to that when L1 is acting as a direction okay so if you recall the lower L2 page will say whether it is the L2 course table or client table not entry or it is a section entry so if it is one of these two entries then it is a it is directly to L2 table so L1 Pt contains a pointer to either and L2 course table or L2 client table it could be one of them not course it could be one of them so both pages represent one entry of internal memory and one entry in L2 course Pt points to 480 page pages and L2 client table 1 page pages so as I told you the entry here in course table course table page pages in client page table it will be one table of page sizes so when a higher page sizes are to be supported similar entries are stored in multiple pages as I told you earlier these higher sizes are represented by having a similar entry so if you want to have a course table page okay of no write text write back text and then buffering we want to have all the course table entries and all of them have the same access permission so that is what we are saying we can do that so an example 480 pages can find L2 table has 4 similar one page entry similarly 64 pages it will have here 64 entries similar entries that is it okay a large page entry defines the attributes of 64 pages okay there is a large page that is 64 kb of page frame is for large as small pages are 4 kb page frame the 4 page kb you know frame is here okay and then a tiny page is called 1 kb page frame this is the time entry in L2 table the 4 page entry generates a page point of that access and then access okay now let me explain this up to this point okay one ng of space okay this is 20 bit so one ng of space so whatever is below that out that using this register okay we access the table and then try to state that one ng of space whether it is pointing to a physical location okay or it is pointing to some directly it may be pointing to a physical location or it may point to a L2 page entry based on this entry uh L2 page table okay and of 4 sides 4 sides because 1 0 is the 0 1 is meant for 4 spaces that means what 4 means 4 kb of size so 4 kb of size means once we get an entry from this this points to an you know index here and then we can get the base address of the table from here okay and then index we are getting it from the remaining address because this one ng space only is divided into 4 kb right so that this will be this portion corresponds to 4 kb so this will be an offset will make you access the particular entry entry and then then we will know this 4 kb is mapped to this location while looking at this value which will be anywhere any values here anywhere in the physical memory we will get that particular address and then you add that offset value to access a particular page so effectively in the virtual space wherever this 4 kb is lying okay may be mapped to you know to be placed anywhere else in the physical memory and then it will not only say where this 4 kb is lying but also this table entry we are not getting this I will show you this will be giving you access permissions to the entry okay so why do we need only for this co-passer and then we do not need a co-passer entry here because we are getting the table base address from this page table entry so each of those entries in the master table if it is pointing to another x2 table it will have the physical address where it is then you know this are all physical addresses okay whatever you are getting is physical address but it is not in the memory here it is directly mapped to physical address so you get the you get to access the x2 page from there you get the actual physical address from there and then add the offset value to access the exact particular location in that particular page okay I hope this is clear to you if you want to look at this slide look at what is happening and then all the explanation that I have given you so it will be able to internalize this particular page okay let me explain some more so each of the L2 page table entries can be of this if it is a large page okay uhh it will be 64 table size L2 page table size will be 64 kb because if it is a large uhh a huge page means 64 kb of page size so that 64 kb of page size you need to keep 16 bit not needed only the higher address value so you will use this physical address to access that particular page once that 64 kb page is accessed they access permissions are given here they are given 4 different access permissions you get that 64 kb you know uhh okay so here how many bits are there 16 bit right for a first one 64 kb of page that 64 kb of page is split into 4 area by giving this access permissions there so you will be able to control it as the even though it is 16 kb you will be able to control it as the minor minority of 4 okay now what happens to the small page the page size is small 4 kb page so that is why you are saying that 4 kb although the 4 kb also you have different access permissions for different so you can decide to have within the 4 kb page all the 4 kb you will we have the same access permissions different access permissions based on the value so ap0 corresponds to this location as similarly ap1 can be belonging to one star okay but this can decide a code this data this may have a stack then you can define the access permissions according to the weather where what you are placing in each program and then where exactly they are located you can give it in this base address so complete access control is there for a particular page of size 4 kb and even though the page size is 4 kb you have a finer access permission you can give the same access permission to all the pages 4 kb page 4 kb page will behave the same way tiny pages you do not have any any more final dimension other than more than 4 kb so all 4 kb page is given same access permission so you see that only 1 mp is there okay they are not gone to the extent of splitting into some more 5 to 12 bytes or something so all 1 kb of size you can give the same access permission and then the behavior cache behavior so all these entries are again similar to l1 page table or l1 is based on the lower okay and then the the exact physical address is given here based on the page size the physical address length will be defined 4 kb page size you will have 4 kb because the offset is coming from the directly from the original address generated by the only you want to know where exactly located so that is the base address is given for a page and then rest of it is used for access permission or it is not part of the address okay it is only this part is actually is built by the offset coming from the processor address so remaining is page part if it is 0 0 if it is 0 0 there is no physical memory present for the address so pt holds the base address of page frame and then the entry also includes 4 steps of application with and the cache and write buffer attributes for the page so each of them will be mapped into a from the lower address okay I hope this is clear to you so let us see that the access permission which are similar to what is done in CPU rewrite privilege mode and then these are more different combinations can be there and then the cache behavior and data behavior is combination of these two which is the not cached or not preferred not that kind of code and the cached and write through if it is cached only you have to say whether it is the write through or write back if it is not cached you have to only say whether it is buffered or not buffered okay so this is how the control goes so MMU finally after initializing all the registers we may have to enable those cached no and then MMU okay that is the first state finally and they are located in this particular coprocessor address and then we can have instruction cache enabled on the table and we is another which I have not told earlier so far because I was saying the vector can be only at this location that for some system we cannot keep memory in this address and we want to keep some cache for something or some other memory in this sub higher address then we can locate the input of the table at a higher address that is choice the system designer and only they have take that up setting the we need it so these are all supported only in this processor not at the value of the coprocessor okay so this is how we have to finally do this to enable after programming the MMU registers and tables are built and then the you have to so how we can do this a typical system is like this so kernel region fixed address what do I mean by fixed address directly to the physical address so there is one on one mapping so NME is not needed to access any of them so page status can be accessed and any shared code or data can be accessed and then system code that is OS code is here and then the rest of the task physical location is here but their task reading is in this address all of them are mapped to the same physical address but they will have a different page table entries to point to different locations so here they are mapped fixed address so whatever address we generate it is mapped to the same location okay there is no NME required for accessing this because some of the physical peripherals we do not need to use we do not want to use any new we want to directly access them that also come to that okay so dynamic addresses this is the task region is always going to the page table so that we can enable particular task that happens I mean point in time so this is a typical example I want you to go through the look where the actual implementation of this is given in the ARM system development which will make it more clear to you okay what is the order in which we do define the fixed area of the system software regions and the page table this enables to access them without the help of NME this is the number that what I told you define the virtual memory maps this is what you have to do to set up the NME define virtual memory maps for each task and then locate the regions listed in step phone and do okay this is the physical memory map we have to decide where you want to map your individual memory and then define and locate the page table and where you want to place those page tables and then define the data session needed or entries needed for the regions and page tables these structures are implemented implementation dependent however a general form of this process can be a good starting point so this is implementation dependent why I call it as implementation dependent because the physical memory where it is in the memory is it will vary from 16 to 65 so you may decide to have a page table you may decide to have a task running some other locations so these physical addresses are different accordingly the NME or page table will be in the same so initially the NME and caches and write worker and then enable them and then what you do you have to have a OS context because it will be transparent from one task to the other okay that is all we have completed all the NME related things I hope this was great view this is only one slide to tell you what is the writing of the memory at least can be present to provide a role attention memory that can be used by the processor without unpredictability of cache why I say that cache will bring unpredictability because of the kind of control flow there particularly the entry whether it is there in the cache or not is not in our component completely it depends on the flow of the program okay so because of that what happens if you do not want some loadings to be affected by the cache behavior we do not we can say that you know that part of the memory may not be cached okay and you know we can keep it as a tightly coupled memory where the cache may not be coming into play it will be directly accessed and any write that means the memory will be directly going to the memory it will not be going through the cache so that is the scenario so such a memory can be used to hold critical like in the proteins and real time processor we do not want you know to access the interface handling some cache features happening and then memory access happening we want directly to access the memory and it should be available so this thing is used to where in the dependency of cache this would be highly understandable in addition it can be used to hold cache-cached data data is used to provide the possibility for not well sensitive to cache typical data structures such as interrupt cache and four banks of data and four banks of instruction each bank must be programmed to be in different locations in the memory map so I am not going into detail because that will have another lengthy discussion but it is not if you know that there exists a TSM and we can configure a core data TSM using some registers and you may have to see the literature to know more about it and this we have come to the end of memory management so we talked about you know we understand and you know what NMU is going to do then which memory translation looker sector for and then I explain you about what are the NMU and how they can be located in the memory and how different access permissions can be configured in them this is a very important part I wanted to look at this lecture again to know multiple times and then we can read the book also especially the book on developer side that book will be good to understand them and then look at the examples also to have a plan and I am very happy this is the book I was going to I am very happy to share this information with you hope it was useful and wish you all the very best in your further reading of this particular topic bye bye