 So, the next important topic and probably the most important topic is the counters. There are lot of misconception about counters and so therefore, let us go through this very very carefully. What is a counter? A counter is essentially characterized by something called a state transition diagram. Now, so this counter has got state number 1, state number 2, state number 3 etcetera up to state number k and after state number k it is getting going back to state number 1. So, that is what this counter is doing and these all these states are distinct. So, one state 1 and state 2 and state 3 are all distinct states ok. Now, if we have a flip normally these states will be implemented as a bunch of flip flops as we as we already know. So, this there is a counter which has got outputs q 0, q 1, q 2 and so on and we name this. So, that q 0 we treat as an L S V q 1 as the next higher bit and so on just some conventions. So, this state is some particular combination of q 0, q 1, q 2. This next state is some other combination of q 0, q 1, q 2 and so on. Now, note that this q 2 is not necessarily a subsequent state. For example, if this is 0 0 this need not be 0 0 1 this could be 1 0 1. If this is 1 0 1 this need not be 1 1 0 this could be 0 1 1 or whatever. So, these states are actually not necessarily next to each other in terms of decimal numbers. They could be they could be just arbitrary. The important thing is that they are different from each other. So, the state 1 is different than state 2 is different than state 3 and so on. So, that is very important such a counter is which has got k states is called a modulo k counter and that is what is written over here. The counter k counter with k states is called a modulo k or mod k counter. Now, that is what this counter is and there is some other box here called the decoding logic and let us see what that does. A counter can be made with flip flops as we said. Each flip flop serving as a memory element with 2 states 0 or 1. If there are n flip flops in a counter there are 2 raise to n possible states distinct possible states since each flip flop can have either q equal to 0 or q equal to 1. So, therefore, with n flip flops it is possible to exclude we can actually make a counter with which is mod 2 raise to n but it is also possible to exclude some of these states. So, suppose we have 3 flip flops then the possible the number of possible states is 8 from that we can either make a mod 8 counter or mod 7 counter or mod 6 counter and so on. But of course, we cannot make a mod 9 counter from that. So, that is what is being said here. So, with n flip flops we can make a mod k counter with k less than or equal to 2 raise to n. For example, if you have a if you have 4 flip flops you can make a binary counter which counts from 0 to 1 to 2 to 15 and then back to 0 or you can make a decimal counter which counts from 0 to 1 to 2 to 9 and then back to 0. So, in the first case we have used 2 raise to n state in the second case we have used less than 2 raise to n state. Typically, a reset facility is also provided which can be used to force a certain state to initialize the counter and that is what we have shown over here. So, what is this decoding logic let us see let us take a look at that in detail. If you cannot read this let me read it out for you this is called this is saying counter and this is saying decoding counter or decoding logic and this diagram is for the same as before. So, here is an example of the decoding logic. For example, this counter outputs this example we have state number 1 2 3 4 5 6 7 8 and then back to 1. So, this is the mod 8 counter and we have some output which looks like this which is 1 here in state number 3 and again 1 in state number 3. So, this is what this decoding logic does. So, this decoding logic can be used to take these flip flop outputs as the input and produce a suitable pulse for example, here we have a pulse which goes high in the third state only and it is off otherwise. So, that is what the decoding logic does. So, decoding logic will help you to for example, you want to know which state the counter is in you can construct an appropriate decoding logic here and that will give you a suitable pulse which will tell you the state of that counter. So, very often we do not talk about this decoding logic, but it is good to inform the students that such a thing is there useful in actual systems. The binary ripple counter is something that we have all we are all familiar with as the first counter that we study. So, here again it is always good to draw a concrete waveforms here and explain this. So, in this case J and K are tied to 1 for each one of these flip flops and clock is fed to the first flip flop and the clock of the second one is actually derived from the q 0 the output of the first flip flop and the clock of the last flip flop is from the output of the previous one and so on. Now, because J and K is always 1 for this flip flop and the clock is directly applied here the output of this flip flop does not really depend on what these are doing and therefore, that is something we can draw immediately and that is what is shown over here. So, this is something that we can draw irrespective of what is happening to the other two flip flops. Now, this is serving as a clock to the second flip flop and therefore, we can proceed and draw this one irrespective of what is happening to the last flip flop. So, that is what we do here and then this is serving as a clock to the last flip flop and therefore, we can proceed and draw that output. So, that is why is it called an up counter because if you look at q 2 q 1 q 0 you have 0 0 1 then 0 0 1 and 0 1 0 and 0 1 1 etcetera and then after 1 1 1 it is back to 0 0 0 that is why it is essentially if you look at decimal numbers it is counting from 0 to 1 to 2 to 3 all the way up to 8 and then back to 0 not 8 7 7 and then back to 0 with a modulo 8 counter with 8 distinct states that is called binary because the sequence is binary it is called ripple because the clock actually ripples through these flip flops right because the clock is not connected to all of this flip flops, but the clock of the second one comes from the output of the first the clock of the third one comes from the output of the second and so on that is why the in a way the clock ripples through all of these flip flops that is why it is called a ripple counter. So, this is the actual q 2 q 1 q 0 diagram. Now, important to point out that the direct inputs sd and rd which are not shown are assumed to be inactive that means sd and rd are assumed to be 0 for all flip flops allowing normal operation of the flip flops ok a binary ripple counter this is continued. So, the counter has 8 states 0 0 0 all the way to 1 1 1 it is a mod 8 counter. So, it is important to connect this picture with the previous picture which we had in which we had this circle with various states and repetition after a certain state and so on and then actually explicitly state why this is a mod 8 up counter ok it is there are some other names and sometimes it is confusing for students who are looking at it for the first time. If the clock frequency is f c for example, the frequency at the q 0 q 1 q 2 outputs is f c by 2 you can see that here right if this you can see is f c this is f c by 2 this is f c by 4 and this is f c by 8 respectively. So, for this counter therefore, the divide by 2 divide by 4 and divide by 8 outputs are already available without requiring any decoding logic. If that was not the case and you wanted an f c by 2 operation then you would have to construct in decoding logic which will give you pulses of this kind. So, that is so this divide by k divide by whatever number that has to do with how the frequency of the clock is getting divided right. So, here you see that and it does not matter what the waveform actually looks like it just depends on what the frequency is ok. Now, this is the same as the previous circuit except we have replaced the clock with positive h triggered clock and that actually makes a big change because now it becomes a down counter. Now after 0 0 0 the first state that we have is 1 1 1 and the next one is 1 1 0 and so on and therefore, this becomes the down counter. You can go through all of these figures later it is I am sure all of you are familiar with this it is straight forward. So, homework sketch the waveforms homework for the students not for you sketch the waveforms and tabulate the counter states in each case. So, here we have actually pretty similar configurations except the clock here is now being is now being derived from Q bar of the previous stage and the difference between these two the top and bottom is that this is a positive h triggered clock here this is a negative h triggered clock and you will see that one of them is an up counter the other one is a down counter and so on. So, give this problems to your students and do that I was going to do that up down binary counters. So, you can since you already know what an up counter looks like what a down counter looks like you can make an up down binary ripple counter by providing a mode input that is shown over here and. So, essentially all you need to check is whether the Q is going to the next flip flop as a clock or Q bar is going to the next flip flop as a clock. In one case it will be an up counter the other case it will be a down counter all these waveforms etc are given here. So, you can figure this out when mode is one the counter counts up otherwise it counts down and these things actually let me just show this ready made circuits to you. So, there are some ready made circuit files here that you can use and in fact you can even show this in class you know just to demonstrate to the students that these actually the outputs will be as expected as they have worked out. So, there is a file called e 1 0 1 counter 3 ok. So, here is a counter ok. So, it is exactly the same circuit that we had in the slide. So, we have a mode input here that mode input is going to all of this top gates there is a mode bar which is going to this bottom gates. So, if mode is one then this Q is getting connected to clock here this Q is getting connected to the clock here and so on. If and this bottom gates then it will just produce 0 right if mode bar is one then this Q bar is getting connected to clock here Q bar here is getting connected to clock here and so on. So, let us run this let us see what mode is right now right now the mode value is 0. So, that that means it should do these are this will it will depend on whether these are positive h triggered or negative less let us run it and see what it does. So, this is the output this is the clock this is the Q 0 this is the Q 1 this is the Q 2 and you can clearly see the frequency division right the frequency here is some f c this is f c by 2 f c by 4 f c by 8. So, you have this divide by 2 divide by 4 divide by 8 counters readily available in a binary counter without constructing any decoding logic. Let us change the mode value now and see what happens let us look at this wave once again. So, it is counting down counting down right now right 0 0 0 1 1 1 then 1 1 0 then 1 0 1 and so on back to let us see this is back to 0 0 0. So, here we have 0 0 0 and add back to 1 1 1. So, it is counting down. So, if you change the mode input you will see that it counts up. So, let us make let us make the mode input 1 and run the program again. So, now it is counting up right. So, let us let us compare these two here after 0 0 0 the next state was 1 1 1 here after 0 0 the next state is 0 0 1 after that 0 1 0 and so on. So, this is this one is counting up the right one the left one is counting down. So, you can actually show these demonstrations to students in class convince them that these circuits will actually work as we discussed in class. So, let us continue with counters there are some other types of counters we want to see now all right. So, we have discussed this direct inputs to flip flops and in particular the set direct and D set direct these can be used actually to control your the sequence of the counter. For example, here in this example what we have is we have a binary counter, but when the counter reaches a certain stage we have taken some of these inputs some of the outputs of the counter and use that to reset these flip flops. So, as a result what happens is when this counter reaches a certain stage the reset input becomes active and that clears all the flip flops. So, this waveform you may not be able to see too well. So, let us actually see this SQL example and you will be able to see the waveform more clearly. So, let me share the desktop all right. So, the example I was talking about is also there in this distribution D 1 over 1 counter 5 yeah all right. So, what I hope you can see this very clearly. So, what we are doing here is this one is just the digital the logical level 1. So, that 1 is connected to j and k here that 1 is also connected to j and k j and k here. So, all of these flip flops are actually getting this 1 here right. Then there is a 0 this 0 is the logical 0 and that is connected to the set input of all of these. So, the set input is inactive for all of these things. The reset input is actually coming from this gate right and this gate is getting its input from q 1 and it is getting it from q 3. So, when the flip flop reaches the state when the counter reaches the state 1 0 1 0 that is the time this flip flop will force all of these this gate will force all of these flip flops to get this set to 0 0 0 0. So, after the state 1 0 1 1 0 0 1 the next state 1 0 1 0 will actually not will not be allowed by this gate. So, let us look at this results and see that it actually happens. So, here it is. So, this is 0 0 0 0 followed by 0 0 0 1 and so on. All the way up to 1 0 0 0 then 1 0 0 1. So, that is decimal 9 right. So, after decimal 9 what is happening is if you look at this let us expand this part. After decimal 9 what is happening is this there is a reset pulse getting created maybe let me expand it expanded further. So, you can see it carefully. So, there is a small reset pulse that is being produced by the gate and that is serving to reset all of this flip flops back to 0 0 0 0 0 and then the counter starts again counting up. So, that is how this works. Let us suppose we connect instead of q 3 here let me connect something else and then let us see what happens and these are good things to do in class. So, that the students develop a better understanding of this whole thing. So, let me instead of q 3 let me let me connect q 2 and I need to make some changes here. So, what I have done is I have connected now instead of q 3 I have connected q 2 and q 1 to this gate. So, what will happen now when the counter reaches the state 0 1 1 0 that will not be allowed by this gate anymore and immediately it will clear all of these flip flops. So, let us see if that happens. So, let us run this I need to just make a small change here let us run this now that was the previous one let us plot the new one. So, let us see what is happening now. So, we are starting with 0 0 0 0 once again then the next one 0 0 0 1 0 0 1 0 0 0 1 0 0 has come then 0 1 0 1 right after that we get 0 1 1 0, but then that is clearing all of this flip flops right. So, that state is not allowed not being allowed by this reset pulse and that is essentially clearing all the flip flops. So, that is the pulse that is being produced here that shows to reset everything. So, that is a small change you can actually make and demonstrate in class and that explains the functioning of this circuit. How do you get back to the A view? So, that is how a decayed counter works in fact this is called decayed only because it counts from 0 to 9 and then back to 0 and you can make it count similarly from 0 to 5 and back to 0 and so on and that is what we have just done. So, let us go ahead to the next counter. A synchronous counter. So, in a synchronous counter what happens is the clock goes to all of these clock inputs and in this case these AND gates are serving to connect q 0 of this 2 j and k of this one right and so therefore, let us see what it does let us just look at the waveforms. So, j 0 and k 0 are both equal to 1 j 1 and k 1 is equal to q 0 here j 2 and k 2 is q 1 and q 0 j 3 and k 3 is q 1 q 2 q 1 q 0 right and so therefore, the flip the second flip flop will change only when q 0 becomes 1. The third flip flop will change only when q 1 q 0 become 1 and so on. So, that is how this works as called synchronous because the same clock is now going to all 4 flip flops. The first output of course, does not depend on any of these following flip flops. So, that we can draw immediately as soon as the clock is given because j and k for that flip flop are always 1. Next one now we need to see when q 0 is is is 1 right now the second active edge comes q 0 q 0 has been 1. So, that serves as the j and k for this one. So, at this point j and the q this q 1 will toggle. So, then you can construct q 1 similarly when q 1 and q 0 are both 1 that is when this j and k are both 1 and that is when the this flip flop will toggle. So, that is what is happening there and so on. So, this is again a binary up counter, but it is a synchronous counter. It is in the remember in the binary ripple counter we had the q of this going to the clock of this one and so on. Here we are not doing that here the clock is going to all of these counters all of these flip flops. Now, we will consider the reverse problem that is we are given a particular sequence of states and we want to design a synchronous counter which will actually perform that job that is it will go through those states that we specify. Now, for that let us get back to the white board and see how that can be done. So, that and we will assume that we are using j k flip flops. So, this is the table for a j k flip flop if j is 0 k is 1 q n plus 1 is 0 same as q n q n bar. So, now, what we want to do is we want to look at the reverse problem this table is useful the one that we are drawing now is useful if you know what j and k are and if you want to predict the next state. Now, we want to look at the reverse problem the reverse problem is like this. So, given q n and q n plus 1 what values of j and k will make this possible. So, that is the reverse problem that we want to consider. So, let us make another table here. So, here we say q n q n plus 1 j and k. So, let us say our q n before the clock transition came the active clock is came was 0 and the next one we would also like it to be 0 and what values of j and k will make this possible that is the question. So, now, let us go back to this table. So, and let us see. So, we can get a 0 if j is 0 and k is 1 j is 0 k is 1 that is one possibility. The other possibility is to use this entry and that is because q n remember q n plus 1 and q n are actually the same. So, q n plus 1 is the same as q n in this case and therefore, we can even use this table and what is that entry that is j is equal to 0 k is equal to 0. So, this is this is actually these are the two sets of values for j and k which will allow a q n to go from 0 to 0. So, in other words since k does not is not mattering here we have j equal to 0 and k equal to x. So, k really does not matter whether it is 0 or 1 and both of these are allowing this to be achieved. Next we will consider q n equal to 0 and q n plus 1 equal to 1. So, if q n plus 1 is equal to 1 we can either use this entry here that means j is equal to 1 k equal to 0 or we can use or note that this is toggling or we can use this entry. So, we can use either that the first one or j equal to 1 k equal to 1. Now, if you look at these together j must be 1 and k does not matter what it is. So, j equal to 1 and k is x. Next we will look at q n equal to 1 and q n plus 1 equal to 0. So, how can that be achieved that can be achieved by either this entry here which is j equal to 0 k equal to 1 or it is again toggling or this entry here right. So, that is j equal to 1 k equal to 1. So, if you look at this k must be equal to 1 and j can be either 0 or 1 or that is x. How about 1 1 if q n is 1 was 1 and q n plus 1 is supposed to be 1 then we can either use this entry which is j equal to 1 k equal to 0 or we can use this entry here because your q n value is q n plus 1 is the same as q n here. So, we can use j equal to 0 k equal to 0 as well. Again if you look at these two together what we are getting is j equal to k equal to 0 and j equal to x right j does not matter 1 and 0. So, this is the reverse table which we can use in designing a counter. This is the table that we use to analyze a counter and the second table we use for designing a counter. So, let us see how that can be done because we are only talking about synchronous counters now. So, this slide essentially says what we have just discussed and it completes it fills up this table and of course, for all of this to happen you need a clock active edge and that is what is shown in this column here. So, here is an example. So, the example has got. So, the counter that we are supposed to design has got 5 states 0 maybe I will do this also on this paper. So, that you can see properly. So, let me just reproduce this problem on this paper. So, it is like this we are given states we there are 5 distinct states 1 2 3 4 5 and after that the counter repeats. So, we are back to state number 1 and 2 and so on. The q 2 q 1 q 0 values are given we are going to use a k flip flops the first state is given as 0 0 0 next state is given as 0 0 1 then after that is 0 1 0 after that is 0 1 1 then 1 0 0 and then 0 0 0 and then it repeats. So, we do not need to really reproduce the sequence again we just say repeats over here. So, now let us see how to do this systematically. For this purpose we need to reproduce the table that we have just discussed in the previous slide and that is given q n and q n plus 1 what are j and k. So, let me reproduce that paper that table here and based on that we can design this counter. So, we have already seen this. So, this is the table that we have for given q n and q n plus 1 what is j and k. So, let us see how to do this. So, first we see that the state is 0 0 0 and q 2 is changing from 0 to 0. So, what should j 2 be at that point j 2 and k 2 that we can look up from this table. So, q q 2 is going from 0 to 0. So, therefore, j 2 and k 2 can be 0 and x must be 0 and x q 1 is going from 0 to 0. So, j 1 k 1 must also be 0 and x q 0 is going from 0 to 1. Therefore, j 0 k 0 should be 0 to 1. So, look at this table here 1 x. So, that is how we can complete this table. This let us quickly do this and then we can or let me just do one more entry and then we can just go back to slides and I will show the completed table 0 0. So, we have. So, the next state now we have 0 0. So, this goes from this becomes 0 x 0 to 1 that is 1 x this goes from 1 to 0. So, that is x and 1. And so on. So, we proceed this proceed in this manner all the way up to this entry and then after that of course, we already after we cover this transition then we already we do not need to do anything further because then the counter will not enter any other state, but the same state will same cycle will continue. So, that is what we get for that is how we complete this table for j is the various j's and k's. So, let us go back to the document and see the completed table. So, this is what is showing that table filling process 1 by 1. So, that 1 by 1 is very important and so of course, it is a mechanical procedure once we understand what is being done. So, now what we have is the truth tables for j 0, k 0, j 1, k 1, j 2, k 2 in terms of q 0, q 1 and q 2. So, in fact you notice that there are many entries which are not even there in this. So, out of the 8 possible combinations we have only 5 possible combinations and therefore, states like 0 states like 1 1 1 for example, is not here not here in this table. So, what do we do about that state? For that state we treat j 2, k 2, j 1, k 1, j 0, k 0 as do not care because our counter is never going to enter that state and therefore, those become do not care conditions for us and in fact, we can use those to minimize our functions using corner maps. So, this is that is what this comment says here do not that we have not used the note that we have not tabulated the j and k values for those combinations of q 0, q 1, q 2 which do not occur in the state transition table. For example, q 2, q 1, q 0 equal to 1 1 0 that does not appear that does not appear in the state transition table and therefore, we treat those conditions as do not care condition and that is all that is listed in the next slide. So, I am not sure if you can see this reproduce this. So, let me just give an example of j 2 and k 2. What we are now doing is j 2 is a logical variable which is a function of q 2, q 1 and q 0, k 2 is another logical variable which is a function of q 2, q 1, q 0 and so on. So, we are going to minimize these functions with k maps. So, let me just drop for you the k map for j 2 and k 2 and then you will get an idea of what we are talking about. So, let us I will just reproduce all this is there in the slide. So, you can look it up later. So, let us say this is the map for j 2, this is the map for k 2. If the students go through the go through this exercise, they know not only sequential circuit but also corner maps. So, that is good to good it serves as a good exercise for the students. So, it turns out that this is 0, 1, x, x. Now, some of these x's are coming from the fact that the counter does not enter that particular state at all. For example, q 2, q 1 equal to 1, 1, q 0 equal to 1, 1 gives you this x and this state is never occurring in the state transition diagram and that is why we have put an x over here. Some of the other x's are actually because of the entries that we had in the previous slide. Anyway, so in this case this 1 can be combined with this x here and this will do you whatever j 2 equal to q 1, q 0, q 1, q 0 bar, q 1, q 0. Now, in this in case of k 2 you have 1 here and all others are x's and in fact, we can make all of these x's equal to 1 and you can just replace this whole thing by k 2 equal to 1. So, here is an example j 2 equal to q 1, q 0, k 2 equal to 1 should be applied to the flip flop 2. So, that it will do the desired job. That sort of completes our design procedure. We have j 2, k 2, k 1, k 1, k 0, k 0, the maps for all of those and then the minimal expressions for all of these. So, this is the summary. j 2 is q 1, q 0, j 2 is 1, j 1 is k 0, j 1 is q 0, j 0 is q 2 bar, k 0 is 1. All that follows from the corner maps. So, then we just make these connections. For example, j 2 we said is q 1, q 0. So, there is a q 1 here going to this gate, there is a q 0 which is going to this gate and that output is going to j 2 and so on. So, you make all of these connections and if you run this example, you will get the desired result. Let me see if I was equal circuit for this. Maybe I do not. But you can actually do this in with sequel and show that it actually works as desired. For one final topic and that is combination of counters and a good example of this is there is a commercial chip, I do not remember the name. It is a decade counter and that is implemented as a divide by 2 and divide by 5 counters. So, what is the combination of counters? We have two counters here, counter 1 which is mod k 1, counter 2 which is mod k 2, counter 1 is getting clock 1, counter 2 is getting clock 2. In general, the clock 1 and clock 2 can be independent. But in this case, we want to make these synchronous and let us see how we can do that. So, consider two counters, counter 1 mod k 1, counter 2 mod k 2 and each of them can be a ripple or a synchronous type that really does not matter. So, the type of these counters really does not matter in the discussion that is following. Since counter 1 has k 1 states and counter 2 has k 2 states, we can get a new counter with k 1 times k 2 states if appropriate synchronization is provided between the two clocks. There are two ways of doing it. One is derive clock 2 from clock 1 using some decoding logic if necessary. So, this clock 2 we can derive from this counter either clock 1 directly or we can use these outputs and derive clock 2 from there. Second option is, so that is here. So, there is a decoding logic. So, clock 1 is driving first counter, there is a decoding logic which is providing a clock 2 to the second counter. That is one option. Second option is to derive the drive the two counters with the same clock. That is what is done here. So, this is counter 1, this is counter 2 and we are now driving them with the same clock. In both cases, you will get a counter which has a modulo k 1, k 2. So, here is an example. There is a mod 2 counter just a single flip flop which is toggling between 0 and 1 with j 0 and with j and k equal to 1. Here is a mod 5 counter which we have just designed and that is going from 0 0 0 to whatever state and repeating after every 5 states. Now, we can combine this mod 2 and mod 5 counters to make a mod 10 counter. And there are two options again like we said. Option A in which the clock for the second counter is derived from the first. Option B in which the common clock is used to drive both of these counters. So, these are the two options possible. And here there are some results which are shown. This is approach A. Actually, the results are sort of self-explanatory and we will not really go through that. But, you should take a more detailed look at this example and see what exactly is happening. Why you are getting 10 states now from this modulo 2 and modulo 5 counters and what are those 10 states that you can actually make a table and see. This is approach B in which the same clock is connected now to both these counters. This is counter 1 and this is counter 2. And again you will get 10 different states and after 10 states the count will repeat. And you should actually look at this in more detail and see what is the difference between approach A and approach B in terms of the waveforms. They are both equivalent in terms of the modulo number because the modulo number is 10 in both cases. But, the details like what is q 2 q 1 q 0 and the fourth one will determine will depend on what configuration you use. Some example, some homework kind of problems show that by connecting the q bar output of the mod 2 counter to the clock input of the mod 5 counter, we get a decade counter counting up from 0 0 0 0 to 1 0 0 1. So, this is something that the students can actually do on paper and then verify their results with simulation. So, I think that is the sort of end of this particular presentation. And this is more or less where we end our discussion on sequential circuits in our course E 1 0 1. And then of course then there are advanced courses for digital system design, but that is not at the basic electronic level. So, I think the scope of this course essentially whatever we covered would be adequate. So, now what we want to do is I just wanted to show you one 555 example because after you cover sequential circuits RS flip flop and so on. It is then good to cover the 555 timer because by this time the students would have done RC circuits and op-amps and comparators and so on. And then 555 is a good combination is a good chip that you can take up at this point. So, let me just show you and then we will go to the next presentation where we want to cover talk about RC circuits. So, let me share the desktop. So, this particular animation is available on the web and just go to the sequential web page and we will find it over there. So, there is an oscillator using 555 that is a good example to take up. Unfortunately the font is a little too big here and so you may not be able to see everything at the same time. But briefly what this does is you can specify the values of R A and R B here and C and then you can compute the waveforms first and that computation is done here the plots are shown here. Also the times T 1 and T 2 which are I think T 1 is this and T 2 is this time that is computed and the frequency of the clock frequency of the output will be computed. And then we can actually start the animation and C and you can use this animation to explain what is happening inside the 555 timer. But before we do that let us just look at this plot. So, what is this plot showing this plot is. So, this point is of course sitting at 2 V cc by 3 and this point is sitting at this node is sitting at V cc by 3 and this comparators are simply comparing this common voltage V c with 2 V cc by 3 and V cc by 3. So, that is what is being shown over here. So, when the V c the capacitor voltage exceeds 2 V cc by 3 your reset input becomes 1 to the flip flop and this goes when this goes below V cc by 3 your set input becomes 1 and that is of course very crucial in understanding this particular circuit that is why these things this R and S plots are actually shown explicitly. So, now let us see what happens when you start animation of this. So, let me pause this at this point. So, what is happening here right now is that the output is 0, output is 0 the Q therefore, Q bar is 1 this which is closed and therefore, this capacitor is now discharging through this path here and that is what is being shown here. Now, when you come to this point right what is happening is your capacitor voltage is falling just below V cc by 3 and your therefore, your S has become 1 R is still 0 and the output of Q output Q of the flip flop is going from 0 to 1. If the output goes from 0 to 1 Q bar goes from 1 to 0 this which opens and all that is happening because this V c has fallen below V cc by 3 let us continue with the animation. Now, this charging starts let me pause it on this phase the switch is open and the capacitor is now getting charged by V cc towards 5 volts and that is what is shown over here and during this time note that R and S are both 0 and therefore, the output that does not change it remains 1 volt let us continue. So, this story continues up to this point at that transition and this point now what has happened is this switch is now closed and capacitor has started discharging again. So, you can actually show sort of when you teach 5 by 5 oscillators you can use this and show the students what is actually happening inside the 5 by 5 timer circuit. There is also another one on mono stable there is also another applet on mono stable using 5 by 5 that is generation of say of a single pulse. So, it is very similar to the last one. So, here again given these values of R and C you can compute that T the pulse width and it shows this graph here. Now, in this case again this node is sitting at 2 V cc by 3 and that is sitting at V cc by 3, but now they are being compared with different things. So, this one is being compared with trigger and this one is being compared with V cc that is why we have shown this R and S separately. So, the S input of the flip flop becomes one if the trigger goes below V cc by 3 and R input goes one if the V c of the capacitor the capacitor voltage goes above 2 V cc by 3. So, that is so there is a difference between the first circuit and this circuit. So, then the animation is pretty similar. So, let us continue let us start. So, that is what happens there during this time when the trigger is high when the trigger has not yet become active. The situation is that Q is 0 Q bar is 1 the switch is closed and the capacitor is directly connected to ground through the switch and therefore, the switch resistance is so small that all this discharging happens instantaneously. So, let us continue and at this point we can pause. Now, at this point what has happened is the trigger has become low. So, therefore, this S is now going to become 1 because now we are going to go to this point S is going to become 1 R is still 0 and that is going to set this flip flop from 0 to 1. If Q goes from 0 to 1 Q bar is going to go from 1 to 0 and this switch is going to open if this switch opens let us see what happens next. If this switch opens then of course, the capacitor now starts charging towards 5 volts and this goes on until this point and all this time of course, your R and S are both 0. At this point the V C has actually gone above has gone beyond 2 V C C by 3 making R equal to 1 and S is still 0 and therefore, this flip flop is now going to get reset from 1 to 0 and the switch is the Q bar is going to become 0 to 1. So, the switch is going to close all that is showing is shown in this figure and we can continue and of course, the rest of the story is already explained earlier and so on. So, these are updates that you can use in when you are teaching mono stable and A stable application of 5 by 5. So, I think we can stop here and maybe I can just take a couple of questions if there are any questions and then we can break for T. Yeah, the first question is what is the difference between NAND latch and NOR latch they are actually very similar. In fact, the first two entries in that table were the same as we saw. So, R equal to 1 S equal to 0 and R equal to 0 S equal to 1 will give you the identical outputs. The difference is which of the states gives you the previous states. So, in the NAND latch R equal to 1 S equal to 1 gives you the previous state. In the NOR latch R equal to 0 S equal to 0 gives you the previous state and that of course, is very easy to figure out from the configuration. And of course, the other they also differ in which of the states is which of the input combinations is not allowed. So, in the NAND latch R equal to 0 S equal to 0 is not allowed in the NOR latch R equal to 1 S equal to 1 is not allowed. So, that is the answer to the first question. Jaichand Rajanthri College. Hello sir, whatever circuit you are showing it on the screen that is up down a binary ripple counter. In between two JK flip flops we can observe two AND gates and one OR. How can we derive it at that sir? Is there any procedure? Your question is not quite clear to me, but how can you derive what is inside the JK flip flop is that what you are trying to say? No sir, in between two flip flops there is two AND gate and one OR. How can we derive at that sir? At that circuit. Okay, you are talking about this particular circuit, the up down binary ripple counter. So, the logic actually is very simple. Essentially what we want to do is we want to connect either Q as the clock here to the next stage or we want to connect Q bar as the clock. So, what we do is we create a mode signal and then that mode is 1 and we create a mode bar signal. So, if this mode is the top gate gets a 1 then the bottom gate will get a 0. So, let us just take the case where mode is 1. If the mode is 1 then the bottom gate will produce a 0 here and the 0 OR, this is simply just putting these two together and if this is 0 then this OR gate is actually not doing anything but passing this output to the clock. And what is the output of this one? The input of this gate is 1. So, the output of this gate is the same as this Q here and that is being passed to the clock of the next gate. Similarly, if your mode is 0 then the output from Q bar here will get passed through these two gates to the clock of the next gate. So, that is the logic actually is quite simple. In fact, you can just derive it using Karnaugh map or whatever but it is so simple that you do not really need to use Karnaugh map in this case. Amruta, Bangalore. Hello, good morning sir. Sir, I have one question regarding whether ADPC or shift register converts the spatial domain to a temporal domain. The question is whether a shift register converts the spatial domain into a temporal domain. In a way it does. Now, the example that we have shown when we loaded some bits into a shift register in parallel. So, you can think of that as being in space. So, when we load that is happening in space for example and then after that when you actually shift these bits that shift is you can think of that as a temporal shift. So, that interpretation is correct. So, we will take the rest of the questions after 12.30 since now we have a tea break. See you later.