 Hello and welcome to this presentation of the STM32L4 system configuration controller. Please note that this presentation has been written for STM32L47X48X devices. Key differences with other devices are indicated at the end of the presentation unless otherwise specified. STM32L4 devices feature a set of configuration registers. The system configuration controller gives access to the following features. Remapping memory areas to address zero. Managing the external interrupt line connection to the GPIOs. Certain robustness features. SRAM2 write protection and arrays. Floating point unit interrupts. Firewall control. And finally the configuration of the 20mA high drive IOs used for I2C fast mode plus. Pictured here is the four gigabyte linear address mapping of the STM32L4. The flash memory is up to one megabyte in a dual bank configuration. The FB mode mitt determines the address mapping of banks one and two as shown. It also determines which bank is alias to address zero. Which is the start of the vector table as seen by the Cortex-M4 core. The SRAM total size is 128 kilobytes. It is split into two parts. SRAM1 is 96 kilobytes starting from address 20 million hex. And SRAM2 is 32 kilobytes starting from address 10 million hex. SRAM1 is located in the usual ARM memory space for RAM. While SRAM2 can be directly accessed through data code and instruction code buses with zero weight states and can be used for code execution. The memory remap at address zero allows you to boost up performance thanks to instruction and data bus access instead of using the system bus. The memory remap at address zero is selected using the mem mode bits in the system configuration remap register. They allow you to select either the main flash memory or the system flash memory. The FMC bank one which addresses NOR or PSRAM, the SRAM1 or the quad SPI. The FB mode bit in the system configuration remap register allows you to swap flash memory banks one and two which allows you to boot either in bank one or in bank two. Here we have the STM32L4's bus matrix. The bus masters are shown on top and the Cortex-M4 core and the two DMA controllers communicate with the bus slaves shown on the right via the circled intersections. The flash memory is read through the accelerator. Cortex-M4 instructions are fetched through the instruction bus and literal pools are read through the data bus. The SRAM1 is accessed by default by the system bus and can be accessed through I-bus and D-bus when it is remapped at address zero shown by the dark blue circles in order to increase performance. SRAM2 is always accessed through the I-bus and D-bus allowing zero weight state code execution. The quad SPI and FMC banks can be read and executed through the system bus by default and can be remapped at zero to increase performance. The two DMAs can access all memories and peripherals. Different bus masters are able to access different memories and peripherals simultaneously via the bus matrix enabling high performance compute operations. There are three boot modes which are selected by the boot zero pin and an option bit named N-boot 1. When the boot zero pin is at low level, the SM32L4 boots from the user flash memory which is aliased at address zero. This is the standard method of booting the STM32L4. When the boot zero pin is at a high level, the N-boot 1 bit determines the boot mode. The default option bit setting is high, enabling the boot loader in the system memory portion of the flash memory. The other option is booting from the SRAM1 memory region which may be used for debugging purposes. When the selected boot is the user flash memory, the STM32L4 boots from bank 1 if the option bit BFB2 is zero which is the default value. If the BFB2 option bit is set to 1, the STM32L4 boots from the flash memory bank 2 as long as its first address is a valid SRAM address. Otherwise, it boots from bank 1. This check ensures a valid vector table. The on-chip boot loader allows the user to program the flash memory through a serial communications peripheral. The supported protocols are USART, USB, CAN, SPI, and I2C. The 32 kilobytes of SRAM2 is particularly suitable for performance, integrity and safety, and low power. The SRAM2 is accessed through the data and instruction buses without any remapping, which enables code execution at zero weight states. The SRAM2 supports parity check. The data bus width is 36 bits because 4 bits are available for parity check, 1 bit per byte, in order to increase memory robustness, as required for instance by class B or SIL standards. Class B and SIL are safety standards. Class B is for home appliances and SIL is for the safety integrity level. The parity bits are computed and stored when writing into the SRAM. Then they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the break input of the timers. Note that the SRAM2 parity check is disabled by default. The SRAM2 content can optionally be retained in standby. The SRAM2 is also suitable for secure applications. The SRAM2 can be write protected with a 1 kilobyte granularity. The SRAM2 can also be readout protected via the RDP option byte. When protected, the SRAM2 cannot be read or written by the JTAG or serial wire debug port and when the boot in system flash or boot in SRAM is selected. The SRAM2 is erased when the readout protection is changed from level 1 to level 0. Please refer to the system memory protections training for further details. The SRAM2 can be erased by software by setting the SRAM2 ER bit in the SRAM2 system configuration control and status register. The SRAM2 can also be erased with the system reset depending on the option bit SRAM2 RST in the user option bytes. The system configuration register 2 contains the control and status bits linked to safety and robustness such as the SRAM2 parity error flag and the control bits to direct some error detection events to the timers break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events include a flash error code correction event, a power voltage detector event, SRAM2 parity error event and the Cortex-M4 hard fault. The system configuration controller manages the selection of the GPIO to the external interrupt or event signal which is used as a synchronous external interrupt or event with wake up from stop capability. Configuration register 1 contains the floating point unit interrupt control bits. It also contains the I2C fast mode plus 20 milliamp drive enable control bits. Four IOs can be configured with high drive mode even if they are not used as I2C alternate functions. They can be used to drive LEDs for instance. The IO analog switch voltage booster is also selected here as well as the firewall. Here we compare code execution performance at 80 MHz while running the EEMBC CoreMark benchmark. The maximum performance is reached when the code is executed in SRAM2 with data located in SRAM1. It is also possible to reach maximum performance with code in SRAM1 and data in SRAM2 if the SRAM1 is remapped at address 0. When executing from flash memory at 80 MHz the maximum CoreMark performance is reached when the ART accelerator is enabled and there is almost no loss of performance due to the flash access time requiring 4 states at 80 MHz. Enabling the prefetch buffer yields a slightly higher score, 3.3 CoreMark per MHz. In addition to this training you can refer to the reset and clock control, power controller, interrupts, flash and system memory protections, timers and I2C trainings. For more details please refer to application notes AN2606 STM32 microcontroller system memory boot mode and AN4435 guidelines for obtaining ULCSA IEC 60335 class B certification in any STM32 application. This slide presents the key differences between baseline STM32 L47X for 8X devices and other devices. Multi-layer AHV matrix is bigger for STM32 L49X for AX devices including new master DMA2D chromart accelerator for graphic and splitting FMC quad SPI slave into two separated slaves in order to increase bandwidth in case of FMC working in parallel to quad SPI. On STM32 L41X for 2X for 3X for 4X for 5X and for 6X devices there is no FMC slave and the flash memory is single bank. The SRAM sizes are different for each device and are listed here. On STM32 L4 derivatives the SRAM2 is aliased to offer a continuous address space with SRAM1. On STM32 L4 derivatives the boot mode is selected either with the N-boot 1 option bit and pin boot 0 or with the N-boot 0 option bit depending on the value of the NSW boot 0 option bit in the flash OPTR register as shown in the table. A flash empty check mechanism is implemented to force the boot from system memory instead of the main flash memory if the first flash memory location is not programmed. This feature is only available on derivative products of the STM32 L4 series. On STM32 L4 derivatives it is possible to boot from additional peripherals as listed in this slide.