 Hello, and welcome to this presentation of the STM32 independent watchdog. It covers the main features of this peripheral, which can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The independent watchdog is used to detect and resolve malfunctions due to software failure. It triggers a reset sequence when the counter reaches the timeout value. Since its clock is an independent 32 kHz low-speed internal RC oscillator, or LSI, it remains active even if the main clock fails. Once enabled, it can only be disabled by a reset. One of the main benefits for applications is its ability to run independently from the main clock. Also, the IWDG can be configured through hardware or software using option bytes. When the IWDG counter can be frozen during standby or stop mode. The IWDG features a 12-bit free-running down counter. It is clocked by an independent low-speed internal RC oscillator at 32 kHz. When the IWDG is activated, a reset is generated if the down counter reaches zero, or when the down counter is reloaded outside the window, if this option is enabled. The IWDG registers are located in the core voltage domain, while its functions are in the VDD voltage domain. This architecture makes it possible for the IWDG to continue operating in stop and standby modes. The 8-bit prescaler is used to divide the LSI oscillator frequency. When the IWDG is started, the 12-bit counter starts counting down from the reset value of 0xFFF. To refresh the IWDG counter, the key value 0xAAAAA must be written in the key register to reload the counter value. If the down counter reaches the end of the count value, 0x000, a system reset is generated. If the window option is enabled, the counter must be refreshed inside the window, otherwise a system reset is generated. The IWDG hardware is enabled by the device's option bytes. If enabled, the watchdog automatically starts at power on. To prevent any reset, the key register must be refreshed at regular intervals before the counter reaches zero, and within the window, if this option has been selected. The IWDG software start is configured in a few steps. The first step is to write the key register with value 0x000CCCC, which starts the watchdog. Then remove IWDG register protection by writing 0x00055555 to unlock the key. Set the IWDG prescaler in the IWDGPR register by selecting the prescaler divider feeding the counter clock. Write the reload register IWDGRLR to define the value to be loaded in the watchdog counter. After accessing the previous registers, it is necessary to wait for the IWDG SR bits to be reset in order to confirm that the registers have been updated. Two options are now available. Enable or disable the IWDG window option. To enable the window option, write the window value in the IWDGWINR register. Otherwise, refresh the counter by writing 0x000AAAA in the key register to disable the window option. The IWDG timebase is prescaled from the LSI clock at 32 kHz. The IWDGPR prescaler register can divide the LSI clock frequency by 4 up to 256. The watchdog counter reload value is a 12-bit value written in the IWDGRLR register. A formula can be used to determine the IWDG timeout. The IWDG time is based on the LSI period and its prescaler, as well as the selected watchdog counter reload value. In the parameter limits, the IWDG timeout value can be between 125 microseconds up to 32.8 seconds. Once a reset is generated by the IWDG peripheral, the corresponding flag, IWDGRSTF, is set in the RCC CSR register to inform the source of the reset. When the microcontroller enters debug mode, core halted, the IWDG counter either continues to work normally or stops, depending on the dbg IWDG stop configuration bit in the dbg module, mcu apb1 freeze register 1. The IWDG can be active in all running and low power modes.