 Hello everyone welcome to advanced digital synthesis this will be the second part of unit 1 in which we will study in detail about the MOS transistor the outline of this presentation is we will study about the MOS capacitor in detail we will look at the IV characteristics of NMOS and PMOS we will look at how different how to encounter different capacitances in a MOS circuit we will understand various capacitances associated with it we look at the two major capacitance types of capacitances gate and diffusion we will look at a very interesting application of MOS in terms of power transistors we look at how to estimate the RC delay of a CMOS circuit and then we will go and we will go and see what are the non-ideal effects in MOS the first part is obviously the ideal equations of MOS in the latter part we will see the various effects that make MOS deviate from this ideal behavior so till now in the last lecture we saw the application of MOS as an ideal switch that was just an introduction so we saw how the switch behavior can be utilized to construct gates now the transistor in on page will pass a finite amount of current which will depend on the terminal voltages what is the VDD for example we will see how this current depends on the voltage and on the various parameters related to the MOS the transistor gate source drain all exhibit some amount of capacitance with respect to ground now since I is equal to CDV by DT that means the capacitance so we rearrange the equation to calculate the time in terms of CNI and variation with voltage so the constant here CNI they actually determine the speed of the gate what this means in other terms is that the effect of changing input the changing input can be described by Delta V here the effect of changing input takes some finite amount of time to get translated into the output let us say in case of an inverter an input rising would cause input rising from 0 to let us say VDD would cause the output to fall from VDD to 0 this change in effect this change in output will depend on the capacitances of MOS and plus the current and hence we say that it takes a finite amount of time for input to reflect on the output we will also see what a degraded level means that means we say that NMOS is passes a strong 0 but a weak one in other terms NMOS passes of a degraded level when it passes VDD we will see what that actually means the symbols below are the most common that these two symbols on the left side are the common symbols used for MOS NMOS the this one the right one with an arrow represents the substrate connection if it needs to be explicitly shown similarly that the right most two symbols are for PMOS so a MOS capacitor works in majorly three modes one is the accumulation the depletion and the inversion these three regions are defined by the voltage on the gate and the voltage on the drain we will see each of these three regions in detail let us go to the next slide okay now let us look at look briefly at some of the terminal voltages we say that the we denote the voltage on gate to be VG voltage on source to be VS voltage on drain to be VD for for discussion sake let us first assume the voltage on source to be 0 although source and drain are symmetric they can be used interchangeably but we assume that source is the terminal at lower voltage that is why we say we always assume that VDS should be greater than 0 greater than or equal to 0 so in this case let us say VGS is equal to VG minus VS so if VS is 0 then VGS is simply VG we get to drain voltage is VG minus VD we drain the sources VD minus VS or VGS minus VD both are true now n MOS we assume for now that n MOS substrate is grounded that means VS and the body both are at 0 voltage for the for the sake of discussion for now we will see how variation varying both VS and VB or voltage of the body will affect the operation but for now let us assume the source and body both to be at 0 there are three distinct regions of operation cut off linear and saturation let us look at each one of them okay we say that n MOS is in cut off when VGS that is the difference of voltage between gate and source is less than is actually significantly less than the threshold voltage of the VN transistor so the threshold voltage of the diode it is very similar to the threshold voltage of a diode let me yes so the gate so the the substrate please note that substrate is a P type material in case of n MOS so the negative voltage or a voltage which is less than less than the threshold voltage of this junction attracts holes in the substrate towards oxide the holes will accumulate towards the surface or in other words the electrons here will be pushed down the electrons here will be pushed down this means that there will be no current so we say the n MOS is in cut off region now what happens when we start increasing VGS and once VGS comes close to VT yeah so once VGS starts approaching VT the the voltage on or in other words the voltage on the gate starts increasing to a positive value it starts repelling holes in the substrate that means now the electrons are attracted slowly towards the surface or the holes are holes started to go deep down the substrate due to this very similar to a PN junction diode the region which is very close to the junction is devoid of any careers the electric field is directed from gate to substrate a small depletion region forms this is very very similar to the PN junction diode I would suggest that if you want to go into the the formation of depletion region into detail please refer to the PN junction diode in your theory books the explanation is similar it is very very same now let us look at so the thing to remember here is that VGS if it is less than or almost equal to VT the n MOS remains in cut off it does not conduct any current so as soon as VGS goes beyond VT the electrons in in application to the electric field to the significant electric field start accumulating towards the towards the junction in the area here the flow of electron is from source to drain now assume a small positive voltage on drain so due to the electric field between drain and source and the electric field between gate and source okay the electric field between gate and source results into the electrons coming closer to the junction the electric field between gate and source propels the electrons towards drain resulting into a current which is called IDS or current between drain and source it is very very similar to a linear resistor however in this case we are assuming that the drain voltage is small right we will come to that so the definition of small here is that VDS should be less than VGS minus VT in this case this region is called accumulation region where sorry this region is called inversion region where the why inversion because the substrate being P type and the careers are electrons that is why it is called inversion region now what happens so in this in this region a small increase in VDS will correspondingly result into increase in IDS very similar to it behaves very similar to register so it is a linear region that is why we call it linear because it somehow mimics the ohm's law now what happens when we start increasing we start we start increasing VGS or VDS to such that the condition occurs where VDS is equal to VGS minus VT now when VDS approaches VGS minus VT the region here which is which is very close to drain the region which is very close to drain this part the inversion layer gets pinched off what what pinch off means is that the inversion layer shows the inversion layer will could be wider closer to source and it will start decreasing in width as so as close as it is it goes to the drain this is because the drain voltage this is caused by the drain voltage the difference in drain and gate gate voltage in other words the higher the voltage on VD the more electrons are pulled for the region in closer to drain would would start getting devoid of electrons this causes this region to pinch off and we call this this to be the boundary of saturation why saturation I will come to that in the next slide why we call it saturation so the condition to remember here is that VGS should be greater than VT so VGS minus VT would be positive value and VDS would be equal to VGS minus VT or this voltage VGS minus VT is also called VDSAT this is the voltage at which the NMOS starts going into saturation of course the thing to again remember here is that VDS and VB are assumed to be 0 for now. Now what happens when VGS VDS starts increasing beyond this saturation value so when VDS goes beyond VDSAT or which is VDS minus VT VGS minus VT the pinch off starts coming starts coming closer to the source this means that the pinched off region know the channel no longer reaches drain the condition is VDS greater than VGS minus VT conduction is how a question might arise here that that there is no channel here so how does the conduction takes place the conduction is possible by the drift mechanism of electrons so the higher voltage as a drain pulls electrons quite fast the electrons will travel very fast from the pinched off region to drain but there will known not be any accumulation of electrons in this area so the conduction still takes place but the the channel current but the the current here is almost independent of the drain voltage so even a slightly higher voltage on drain over and above the VDSAT will not affect the drain current by a big amount for let us say for now we assume that the drain current would remain constant in the saturation condition we will see how this is not exactly true this is an ideal case but but yeah it is good to start off at the ideal case to understand the functionality better so we say that in ideal case the drain current is linearly dependent on the drain voltage whenever the NMOS is in linear region and it saturates when VDS approaches VDSAT if VDS is increased beyond VDSAT the drain current remains constant so combining all three regions we can make an IV curve of this device IV curves a curve means that we plot the voltage versus current and see how the current is affected by the voltage we will see the IV characteristics in one of the latest slides now let us see let us try to quantify it let us try to quantify how the current depends on the voltage in the linear region and in the saturation region so current depends on the charge and the time so we answer two questions here how much charge is in the channel and secondly how far the charge is moving now the MOS capacitor looks like a parallel plate capacitor the gate and the channel forming two ends of the capacitor while the oxide forming the dielectric so the charge in the channel so just focus on the figure here the CG is nothing but the gate capacitance so the charge in the channel Q is equal to CV very famous equation the capacitance of a parallel plate capacitor is or CG the gate capacitance is epsilon O X which is the oxide parameter WL is the area with just imagine it being a three dimensional structure the area of this this rectangle is WL and divided by the thickness of this oxide so we say we define one more variable called one more rather constant called C X which is epsilon O X by T of P O X now this C OX is technology dependent what it means is that a particular foundry for a part this epsilon O X depends on the type of material so for example for silicon dioxide this is the most famous dielectric material in VLSI fabrication it is a good insulator epsilon O X being 3.9 with oxide thickness is also technology specific I mean for a particular technology there will be a particular thickness so this can be treated to be C OX can be treated as a constant for a particular technology so the CG is C OX WL the voltage is the voltage at a particular point be at a particular point inside the channel we assume that we assume the voltage to be at the half day point which is so the voltage from drain to sources VDS since it is a linear region we assume the voltage to be at the middle to be VDS by 2 and the voltage that matters that that pulls the charge is that forms the results in forming the charge is actually the gate to this region since we are talking about capacitance is at these two points it will be VGS minus VDS by 2 minus VT you always do not ever forget to take into account VT because VT is the voltage that is required to overcome the threshold of the threshold of the junction so it should always be subtracted from VGS so we now we got the value of C and the V now so the first thing we sought to define was how much charge is there that we saw in the last slide Q is equal to CB we calculated the value of C and the value of V now we come to the second question is how much time it takes the charge is carried by electrons the carrier velocity of electrons is proportional to the electric field the lateral electric field between source and drain so we just go back and pause and think that what causes the charge to build up is the gate voltage that is why in the last slide we saw that the gate voltage is which is responsible for setting up of the charge is calculated in terms of VGS now the speed at which the the so the gate the gate voltage will first from the inversion channel the drain voltage will help the electrons in conducting so these the carrier velocity will depend on the VDS now V is equal to mu E where mu is the mobility of the electrons and the electric field is if you go back to the basic the electric field is V by the length at the through which the electric field is the voltage divided by the length of the channel so the time it for a carrier to cross channel T is equal to L by V time is equal to distance upon speed and this is not any special special equation very basic equation so now we know both both things we know we know this the value of C we know the value of T now IDS is nothing but the charge divided by the time so we plug in all the values we calculated earlier so this the equation comes to be mu C ox W by L VGS minus VT minus VDS by 2 into VDS you can verify this by plugging in all the things we calculated earlier into this equation IDS is equal to Q channel by T we define one constant which is beta mu C ox W by L now we discussed earlier that C ox is technology dependent W by L are I would not say they are technology dependent but they are fixed for a particular we when we design let us say an inverter we have to fix the value of W by L for NMOS and for the PMOS here the purpose of defining beta to be constant is to study the effect of the change of voltage on IDS assuming the all these parameters mu C ox W by L are constant for the sake of drawing the IV curve now what happens when the transistor goes into saturation so we see that whenever the the drain the VGD that is or VD is greater than VGS minus VT or whenever VDS is greater than VDS sat which and pinches of near drain now as we assumed earlier or we saw earlier the diagram that increase in drain voltage will no longer increase current so now IDS in case of linear was this so what we do is we replace VD by the value of VDS sat which is VDS minus VT and we just rearrange the equation so after rearranging the result is that IDS is beta by 2 VGS minus VT square so we see that there is a square relationship of voltage on IDS in case of saturation combining all three equations the ideal MOS transistor can be represented by shockless first-order transistor model these these equations you can call them shockless first-order or ideal transistor equation anything goes fine the three regions being let us recap first VGS if it is less than VT the NMOS will not conduct the current would be 0 and the transistor is set to be in cutoff second case as we start increasing VGS but VDS is still less than VDS sat the current would be beta VGS minus VT minus VDS by 2 into VDS so we see a dependence of IDS on VDS in linear region when we start when the voltage or on drain goes beyond VDS sat the IDS becomes independent of VDS and in turn only depends on this square of VGS minus VT so this is an example of a particular NMOS device with in 0.6 micrometer process with TX being 100 angstrom mu that is the mobility of electrons being 350 cm square by VC VS the VT being 0.7 volts if you remember the VT of a PN junction diode the most famous text book value is 0.6 so if you see the VT is very close to that now we have plotted IDS versus VDS at different values of different values of VDS now the W by L is used to be is used as 4 by 2 lambda, lambda if you go back to the first lecture lambda is nothing but the feature size by 2, the feature size being channel length so the here the beta is calculated and the values plugged in so let us go through this IV characteristics if you notice the region the first part of the curve it is it is very similar to the ohms law ohms law curve that means it is a linear region where ID is increasing with increase in drain voltage these different curves correspond to the different values of VGS so as VGS keeps increasing the current also keeps increasing and remains linear when whenever VDS till the boundary where VDS is equal to VDSat for a particular VGS if we start increasing drain voltage the current becomes constant since VGS is fixed and in the saturation region VDS ID does not depend on VDS so current becomes constant with increasing value of VDS TMOS IV would be very similar to NMOS IV curve the only difference being that voltages are and doping are inverted one important point to consider here is the mobility of holes the mobility of holes is typically 2 to 3x lower than that of electrons and this is the value 120 cm square in an AMI 0.6 nanometer process so for a PMOS to conduct the same amount of current as an NMOS it should be the PMOS should be made wider as discussed in the first class for let us say for discussion sake we assume that that the mobility of electrons is twice the mobility of holes so we would make PMOS to be twice as wide as NMOS to conduct the same amount of current. What I would recommend is that you should plot the IV characteristics try and plot the IV characteristics of PMOS it is the curve and verify that the curve looks very similar to NMOS and we have I am not showing the PMOS IV here it is left as a take home assignment for you guys now let us look at one very interesting till now what we have discussed VT appears so much in the equations we see that whenever VGS is less than VT that the transistor does not conduct so let us look at VT VT is a very very important parameter in device fabrication it controls it determines a lot of things we will see what VT is and how does it affect the characteristics of a transistor so we saw that a positive VGS will result into a depletion region and ultimately into the inversion layer being informed so VT is the voltage at which the minimum voltage at which the MOS device begins to conduct so what does VT depend on we till now we have been using VT as sort of a constant in the equations but it is sort of constant it depends on the gate material what material is the gate made of usually it is poly silicon nowadays what is the gate insulation material the most popular is silicon dioxide what is the gate insulator thickness what is the voltage between source and substrate now till now we have been assuming the source and substrate values to be 0 we say that for calculation of the ideal IV characteristic equations we assume the voltage at source to be 0 and the voltage at substrate to be 0 as well VT is a function of the voltage difference between source and substrate we will see we will see how does it affect in later slides and channel doping how VT is now for a particular technology for a particular foundry usually gate material gate insulation material and thickness would be constant the top three would be constant for a particular technology but still there will be devices on a particular chip some of them will exhibit high VT some of them will exhibit average VT and some of them will exhibit lower VT this is not by accident this is many times it is intentional to change the VT how the VT is changed is by varying the doping concentration of insulation this is the first one is the most popular way of tweaking the VT of a particular device it is also it can also be changed or tweaked by using a different insulating material for the gate to increase permittivity but this is again changing the insulating material is not easy because it will change the whole fabrication process so that is why I say that the insulating material is technology and fabrication lab depending so the first one that is by varying the doping concentration is the most popular way of changing the VT of a device now what happens when VT changes what happens when VT increases what happens when VT decreases so if you remember the okay let us let us look at this equation VGS which is the equation of current in saturation when VT increases IDS decreases so we say that a higher VT now a decrease in IDS would mean the device getting slower so increase in VT will result into a slower device a decrease in VT will result into a faster device that is why I say that devices with all three types of VT that is high VT standard VT and low VT are important for digital design since these devices have so the low VT will be fastest the standard VT will be standard the high VT will be slowest correspondingly the VT also determines the power we will come to that later but let me state here that a high VT which is a slower device would exhibit low leakage power so for designs that are very power sensitive and not much performance is expected out of them will use high VT devices similarly low VT devices would be used for very high performance digital designs where power might not be of a big concern so that is why all three flavors are presented to their designs we will see the power thing later but just remember that increase in VT will make the device slower but less power hungry similarly decrease in VT will result into faster devices but they will consume more power so we will just review what factors affect the current the factors affecting current are WL ratio and how wide and how long is the channel the threshold voltage VT the thickness of the gate insulated TOC which is contained in beta the dielectric constant again contained in beta the carrier mobility again contained in beta so now so we what we have seen till now is the effect of the different the gate voltage the drain voltage or rather to be more precise the difference between gate and source that is VGS the dependence of the the current on VGS and VDS now let us see what sort of capacitances are exhibited by a MOS transistor so in fact in practice any two conductors that are separated by an insulator have capacitance they will exhibit some amount of capacitance in case of MOS transistor the gate to channel capacitance is very very important because this is the thing that causes that creates the channel charge which is necessary for the operation of the MOS however the source and drain they are also good conductors that is their enclosed regions they are they exhibit some capacitance to the body why because they have reverse bios diodes to the body these are called diffusion capacitances because they are associated with the diffusion regions in source and drain and these are not desirable okay let us look at the gates that gate capacitance is this view that so we say that we saw that the CGS is epsilon O X WL by T ox now here the C ox again the the equation is rearranged to define a parameter called C per micron that is capacitance per micron micron of the of the MOS transistor that is the value is given to be typically to come to parent per micrometer this might not be very true for today's some micron devices but yeah so just just to reiterate the gate capacitance is very very important since this is the one that causes the charge to build up in the channel now diffusion capacitance we denote two values CSB that is the capacitance of source with respect to body CDB the capacitance of drain with respect to body these two capacitances are undesirable also called parasitic so whenever you encounter a term parasitic in VLSI design it means anything which is undesirable it can be parasitic capacitance or parasitic resistance why undesirable because they make the device slower now the capacitance a parallel grade capacitance depends on the area and perimeter so the the way they are the capacitance is decreased is by using small diffusion nodes is by so this capacitance is as very comparable to gate capacitance for a contact the diffusion if the diffusion is uncontacted it decreases and also varies the process so this figure shows three different layout techniques in the first the A we see okay we see that first of all this is these these are diffusion regions the pink ones the black ones are contacted the fusion regions so the first one will show a lot of lot of undesirable capacitance in case of V the diffusion regions are combined together and contacted so this will show comparatively lesser parasitic capacitance capacitance compared to A because the diffusion is made smaller the diffusion node is made smaller in the third case the contact is removed from the from the diffusion region and since the contact is removed the width can also be decreased that is the node can still be made smaller so C will have still less parasitic capacitance we will not go into much detail about these layout techniques some may be applicable to some circuits some may not be applicable so this is meant for a different course all together but this gives just an idea of that how good layout practices can decrease the capacitance the part of the undesirable capacitances right now this is a figure which shows all the capacitance inside a MOS we have seen earlier that we have seen CSB and CDB which are the the junction capacitances source to bulk and print to bulk these being the parasitic capacitances then other ones are oxide capacitances that is the C the gate to channel bulk which is this one CGB is nothing but CG the desired capacitance that forms a charge now what happens that if an ideal transistor will have no overlapping region between the diffusion and the oxide so in a self-aligned process in an ideal process there will be no overlap between the diffusion that is the two M-class regions let me go back to the figures yeah so yeah so in an ideal transistor the limit at which the diffusion ends will have no overlap with the oxide layer here so there is a real overlap at these two but in a practical process this is not possible there is some amount of overlap between the diffusion and the oxide this overlap causes this overlap causes two more parasitic capacitances oxide capacitances which are gained to drain overlap and gate and gate to drain overlap and gate to source overlap so we see CGB and CGS they are also type of oxide capacitances just so we see that there are three kinds of oxide capacitances and two kinds of junction capacitances exhibited in biomass out of these five the gate to source is most desirable rest of them are parasitics so the better the fabrication technique the better the layout technique the less will be the the gather undesirable capacitance is exhibited by a MOS so we saw that in linear mode the let us see the value what is the typical value of how does the value of these gate capacitance compare in linear and saturation mode now in linear mode if you go back and remember that the channel is spans the complete length from source to drain it is equally so we say that the capacitance is equally split between source and drain so the CGS which is the capacitance between gate and source we say that they are equally divided so we divide half and half from CGS and CGD so the total channel capacitance as we saw earlier is CG is COXWL so L effective is nothing but L in this case the complete length however in saturation mode we see that the channel is being draw so actually in in saturation mode the capacitance of the the oxide capacitance goes lower because the the capacitance exhibited by gate to drain is 0 why 0 because there is no channel here similarly it is approximated that CGS becomes 2 by 3 of the of COXWL and the total therefore the total is sum of CGD and CGS which is 2 by 3 of COXWL L effective nothing but L so we see that the gate capacitance and saturation mode is lower than the capacitance exhibited in the linear mode okay now we see not till now we have been assuming that the voltage on source is 0 the source is grounded what is source is greater than 0 a very good example is a transistor which is trying to pass VDD so let's see a transistor where the gate and drain are both connected to VDD I can I can say this is drain or this source doesn't matter the two terminals are connected to VDD one of them being gate let's see what happens now gate is VDD the voltage on source if it is greater than VDD minus VDD VVGS that is the difference of voltage between gate and source will be less than VT and the transistor will turn itself off I will repeat if the voltage on source goes beyond VG VDD minus VT the VGS will stop being greater than VT the threshold voltage and the transistor will enter cutoff region this is why we say that the voltage here at the source cannot be greater than VDD minus VT which means that if you use a pass transistor in the design and try to pass a 1 using NMOS the NMOS will not pass VDD it will not pass voltage higher than VDD minus VT which is that is why it is called a degraded one logic level 1 is represented by VDD since the pass transistor is able to pass only VDD minus VT is called a degraded one in other words we say that NMOS passes a strong 0 but a weak 1 that is why in earlier circuits we saw that NMOS is used for the pull down logic not for pull up in most designs NMOS is only used for pull down network since it it passes a strong 0 correspondingly NMOS will pass a strong 1 but it will pass a voltage which is no lower than its threshold voltage that is VPP that is why NMOS is used in the pull up network because it passes a strong 1 but a weak 0. Now what happens when we use the pass transistor circuits to form form any kind of any kind of design so let us see this this circuit using NMOS on the top so NMOS if it is gate in one terminal is tied to VDD the other terminal will remain VDD minus VT let us see a series of pass transistors so the first one here passes VDD minus VT but the second one the second one passes VDD minus VT again because it is the gate is tied to VDD but the other terminal is not VDD actually it is less than it is actually VDD minus VTN so it so please verify using the equations of VGS being greater than VT for the NMOS to operate in the on mode and verify that the voltage at the end of the circuit will remain VDD minus VT. There is a separate configuration here so if you see that where we connect the output of one pass transistor to the gate of another in the first case the source of one transistor was connected to the brain of other similarly they were connected in series but here the source of one transistor is connected as a gate now the gate voltage should be greater than VT I mean the difference between the VGA should be greater than VT for a transistor to operate in the on mode so we see that this transistor here will exhibit a 2 VT drop because the voltage on gate is decreased by VT already please please again request you to go back to the equations and verify that that this indeed is the case so pass transistor is a is a very popular logic family which is used to define gates it is not used everywhere because of this precise reason that it it does not pass a strong one we will see what happens if you do not pass a strong one what are the disadvantages similarly if we use PMOS as a pull down device we see that the voltage at source will not be 0 it will be the V it will be VTP the absolute value is used because VTP is negative so let us say VTP is minus 0.7 volts the voltage here would be 0.7 volts positive 0.7 now we we saw that the we saw the ideal ideal transistor equations we saw that we saw that shockly model we saw we saw this shockly model equations obviously they are ideal being ideal equations they are not very accurate for modern transistors they are too complicated for hand analysis all the all such analysis where we want to see the voltage effect on the on the current and all that is usually done using spice it is not it is not using them using hand because these equations are not linear and they they are too much complicated for using hand analysis but but for for study sake let us let us devise a technique where we treat a transistor as a resistor as we saw that in linear mode it actually exhibits such functionality where IDS linearly varies with VDS so what we could say is that using Ohm's law we say that IDS is equal to VDS by R where R is the average value across switching of the digital gate obviously again and this is idealist model and it is inaccurate to predict current at a given time but still this model is good enough to predict the delay of a bit not the actual delay but a delay value in terms of RNC which can be compared across gate and across different layout techniques so this is a very useful tool where you can quantify that a particular gate design what kind of delay it will exhibit let us see how is it is done so we call this model the RC delay model so what we do is we say that a MOS can be represented by a ideal switch plus a capacitance and an on-resistance whenever the switch is off obviously the resistance is infinite whenever the switch is on there is some finite on resistance we say that let us say the N MOS has resistance R and the capacitance C a P MOS will have a similar a similar unit P MOS will have a similar capacitance C but we will have an on-resistance which is twice that of N MOS because the mobility is the mobility of holes is half so unit N MOS will have a resistance R capacitance C unit P MOS will have a resistance 2R and capacitance C capacitance is proportional to bit as the width increases the capacitance increases but the resistance if you remember is inversely proportional to bit so the width increases the R decreases now look carefully at the figure below of the N MOS gate drain source and K represents the width of the N MOS assume the length being same of all the P MOS and N MOS design and the assume the width to be K K the factor simpler fact so now this using the RC delay model we convert this N MOS into a switch an ideal switch which exhibits capacitance drain capacitance KC we saw that the C is proportional to width so if width factor is K we say that the drain capacitance is KC again the source capacitance is KC the gate capacitance is KC plus there is a non-resistance R by K since R is inversely proportional to bit similarly for for P MOS thus capacitance is the main same but the resistance becomes double of N MOS now let us analyze the design and see how how the delay can be estimated these are some values of C and R for a particular technology there is a very old technology so you can you can these are not important for for modern technologies we will just talk in terms of R and C now what does a unit transistor mean it may refer to a minimum contacted devices a minimum contacted device will be 4 by 2 lambda since lambda is features size by 2 it does not does not matter what what width what what kind of what how much wide device we use for your analysis as long as your consistent if all your devices in just the circuit you are analyzing are consistent then you don't need to be concerned about what is the width of the unit transistor let us estimate the delay of an inverter using this RC delay model it says that estimate the delay of a fan out of home the fan out of one means one inverter is connected to another inverter so it is an inverter pair both the inverters are of are of same type that is the P MOS is twice as wide as N MOS so we convert this into an RC delay model so P since N MOS width is 1 so all the N MOS capacitances will be seen the P MOS width is 2 so all the capacitances will be 2 C the R of N MOS and P MOS would be same because again P MOS is twice as resistive as N MOS and since it has width of 2 so the resistance becomes R now this case this particular case assumes that so we are we are estimating the delay of delay at point Y you are not estimating delay at the end of the second meter we are estimating delay at point Y so how much capacitance would Y see why would see the only the gate capacitance because it is connected to the two gate terminals of this inverter the gate capacitance similarly if you see Y here it will see C at N MOS and 2 C at P MOS similarly we we okay we look at the case where P MOS is open and N MOS is closed so when N MOS is closed and P MOS is open whenever the capacitance are in parallel they add up so the capacitance at Y will become 2 C plus C 3 C plus the inverter here so this part is open the P MOS is open this will go away it will see 2 C from here it will see the C from N MOS and the R from N MOS this C does not matter because it is connected to both so we see that in effect whenever this transistor the fan out of inverter fan out of one inverter when P MOS is open the delay is 6 RC that is what I said is that using this RC delay model we can estimate the delay of a particular design obviously the delay values we are not concerned about so let us say we are making a complex gate there can be multiple ways of the varying that way using some logic families now we can estimate the how much delay will that gate take the area we would know a gross area we will know by the transistor form and a delay we can estimate on paper using this RC delay this is useful to compare different types of circuit designs what I would request is that all of you to go back and estimate the delay of few basic designs let us say 2 input 9 gate 2 input and gate we will explore this area in detail when we come to the the calculation of propagation delay using this will be very useful there now till now we we saw that we saw the ideal equations of MOS and the shock lifter started transistor models now let us see what are the non-ideal effects that is the the effects we see in the real transistor what are these effects and how do they affect this this I V curve now this is the plot of a 180 nanometer TSNC process using the ideal model where the value of beta VT and VDD are given this is the this curve which is very similar to the curve we saw here the ideal curve on the next slide we would see the same process the same process would mean same beta VT and VDD values but the model here used is not the ideal model but a spice model now please note that a spice model is much much more complex it is much more complex and it mimics a real very close to real transistor functionality after fabrication so the spice models are the golden standard for for analyzing the MOS circuits both digital and analog and these represent the actual transistor behavior on silicon now we see this curve and we try to notice what is different between these curves and the curve and the ideal curve we saw on this slide this is the ideal curve and this is the the actual curve of the device what we see is less on current so if we see the ideas here go still 250 or let us say for VGS 1.8 the ideas lies between 200 and 50 micro ampere however on the previous slide the ideas is much higher lies between 300 and 400 so we see less on current we see no square law that means the current here in saturation is increasing it is it is not constant as by the ideal model now we will see what physical effects cause this first thing we assume the carrier velocity which is proportional to the E field the lateral E field which is VDS by L but at fields higher fields that which are present in any transistor the fields are higher because the L is very very low in present transistors the L is of the order of nanometers so let us say for a for a nanometer device the L will be 40 nanometer this mean this is the reason why the drain voltage and the gate voltage these have continued to reduce over technology shrinking other because the electric fields have been becoming so much stronger so you can go back to your paper and see that what if the L is let us say 180 nanometer and VDD is 1 let us say 1.8 volt how does that compare to L being 40 nanometer and VDD being let us say 1 volt you will see notice that the electric field strength has been going that is why we have to pull VDD down still the electric field is high enough to saturate the carrier velocity why because what happens is that at high electric fields the carriers will scatter off atoms and velocity will reach a value which is called the saturation the saturated velocity V SAT is mentioned here for electrons and for holes you see that the electrons are are faster than than holes so a better model we took V is V as E mu VDS by L but this is a better better model mu E LAT E by 1 plus E LAT by ESAT so the V saturation is defined to be mu into ESAT this is the curve of the carrier velocity with respect to the electric field we see that it it starts off linearly but again it kinds of saturate at some point whatever V increases this means that for the whenever transistor is on in idle model we saw that it exhibits a square relationship but here the velocity is saturated current it increases with VDD it does not increase the VDD square so the square relationship is no more true you can you can verify this by plugging in the value of V so you will come to this equation so we see that the velocity saturation what it means is that the on current will not follow square relationship it will kind of it will follow the linear relationship but real transistors are partially the velocity saturated they do not exhibit either the first order effect or the second order effect they follow an effect which is somewhere between 1 and 2 so we say that IDS is proportional to VDD based to the power alpha where alpha is a value an empirical value between 1 and 2 this is called the alpha power model so the shocklay model is an order 2 model the alpha power model so the graph here shows the simulated means the the spice value which is the most accurate it shows alpha and the shocklay you see that there is so much difference between the shocklay and the simulated but alpha comes quite close to the simulated model so the equations these are the equations for for the alpha power model for IDS where ID sat is defined and satisfied now another effect is called channel and modulation which forces the transistor into the non ID territory we saw that there is a depletion region and if we increase the width of we saw that the inversion region the the area that has filled with with carriers it pinches off if we increase the VDS so the effective length of the channel earlier we would take we are assuming in linear region we saw that the complete channel is available but in saturation region the length of the channel available is less than the full length because of the pin drop region so the L effective is L minus LD where LD is the length of the the depletion region the area where which is devoid of electrons the shorter L effective gives more current so IDS will increase with VDS even in saturation in ideal model we saw that IDS does not depend on VDS in saturation but here because of the channel and modulation the IDS will still increase in saturation mode with increasing VDS because increasing VDS causes L effective to decrease so this is the equation which takes care of this please remember this is again just a model just a modeling of this effect so what here is done is that this is the equation of the transistor in saturation added to this to capture the effect of VDS increasing VDS we have added one more factor called 1 plus lambda VDS lambda is channel length modulation coefficient please do not confuse it with the future size lambda we have been discussing before there is a separate lambda it is again an empirical value which is calculated to fit the Arabic characteristics so this effect 1 plus lambda VDS captures the vector of increasing VDS due to channel and there is lot of literature available on this so if anybody wants to look into detail I can go through that the purpose of this chapter is to introduce you to the non-ideal characteristics and to show you that how the ID of how the IDS varies with VDS in an actual there is one more factor called body effect now all along we have been saying that the substrate of the MOS is tied to zero the body is grounded for an MOS or P MOS of this need to be tied to be but what if the source voltage increases because source is connected to the channel that means what if the voltage difference so we assume that the voltage at source and the voltage at bulk are both 0 so VDS that is difference of voltage between body and source is 0 what if the source is in the the source as voltage is not 0 but positive that we saw we saw one case in in terms of past transistor the voltage at source was not 0 so this affects the VT of the device we saw earlier during the discussion of the VT and there was one point where it was said that the VT depends on the voltage difference between bulk and source so this is the part where we study them so VT is the gate voltage I said it in word channel but VT increases if source voltage increases because source is connected to the channel increase in VT with VS is called the body effect now let us see how it is captured in the equation so again we define a constant called VT 0 which is nothing but the VT of the device considering VBS to be 0 plus we define a factor here which is body effect on coefficient and this body effect coefficient is so here we see the definition of the body effect coefficient I believe that you would be studying this effect in more detail in your device physics so this is just a recap of that so phi s is surface potential at threshold so see the VSB is captured here so if VSB is 0 VT is nothing but VT 0 however if VSB is positive VT tends to increase this all depends on the doping concentration and the influencing carrier carrier concentration that is why I say that if you want to revise this in detail you should go back to a device physics book which has much more detail about this about the VT changing with respect to the body effect so we saw we saw three effects we saw the body effect which changes VT we saw the channel and modulation effect which means which what it does is that it will make ideas increase let us recap a bit so we saw three effects which are the three non ideal effects the first non ideal effect was the velocity saturation the carrier velocity saturates this means the on current is less as compared to the ideal model second thing we saw was a channel and modulation which means the the current increases in case of saturation with increasing VDA third thing we saw was the body effect which results into an increased VT and we discussed earlier that increased VT will be a lower current now what happens we also were all this while we were saying that a transistor that is in current of region will not exhibit any current but the simulated results if we expand that part of the graph where the transistor was in cutoff we see there is some even though very less but there is some current and the current does not go to 0 in cutoff we see this is a very very important factor in in today's micro electronics this is called a leakage current so we see what is what are the sources of this leakage current one is the subspecial current conduction which is which says that the transistor cannot abruptly turn on and off it will take a finite amount of time to switch from on to off and there is a conduction during that period there is a junction leakage that we say that the transistor is cut off because we diode the reverse diode but even a reverse diode diode due to the minor minority carrier conduction exhibits some junction leakage then there is a gate leakage that is the with the gate dry dialectics becoming thinner and thinner as a technology progressive there will be an effect of gate of electrons turning through the gate dielectric which is called gate leakage now substantial leakage is the biggest source in modern chemistry this is the equation for substantial leakage I will not go into details of this again you can report your device for this what it means what what what it means is that as the technology progresses the devices get smaller and smaller they start exhibiting more and more details current and in earlier technologies let's say 0.6 micrometer 0.1 micrometer etc the leakage current was not important because it was not even analyzed it was not even taken into care during the design of a circuit it was not a not a majority factor but now with so small devices all these three factors the sub-threshold conduction the junction leakage the gate leakage all these three are increasing resulting into these becoming majority factors and we have to also think about so you can use that there will be a transistor but let's say the the gate is at VDD or something or let's say the gate at 0 voltage and MOS transistor we assume that it is off it is not connecting current but actually it is conducting a small amount of current and let's say there are billions of transistors doing the same thing when the chip is off so the billions of transistors will contribute a significant amount of current and it is a very very important factor now because lot of these semiconductors are used for battery powered devices right so there is one more factor called drain induced barrier lowering which says that the drain voltage also affects VT so we saw that the VT being affected by the difference of voltage between source and bulk here this effect also in this effect the drain voltage also affects VT so VT is VT minus eta VDS so this means that high drain voltage causes sub threshold country leakage to increase right so there is a there is a note on junction leakage again the junction leakage will depend on the area and perimeter of the particular region we are not going to detail of this now we talked about gate leakage that the carriers tallying through the very thin offsides as I said earlier that negative it was negligible for older processes but it is becoming critically important now since the the oxides are becoming thinner and thinner now let's see a small note about the temperature sensitivity of this device so whenever temperature increases it reduces the mobility of electrons and holes it reduces VT so let's try to fill in the gaps here what happens to Ion with temperature so increasing temperature reduces mobility reduces VT reduce mobility means a lower Ion so Ion will decrease the temperature if we reduce VT so the threshold is getting reduced yes it will affect the ID ID might increase but the mobility factor here is more dominant than the reduced VT so Ion will decrease still decrease with temperature but I often increase because I of which is the the leakage current depends on VT higher the VT lower the leakage current lower the VT higher the leakage current now so what happens if the transistors are not ideal they are still still behaving as it is they still allow us to make very complicated designs but what do these effects matter for they are important because of the supply they what they determine is a supply voltage choice we will see the logical effort in more detail they determine the power consumption they determine what logic families can be used for example can we use past transistors or not they matter for the temperature of operation so whenever devices are fabricated not all devices on a chip are identical VSI fabrication is one of the most sophisticated and one of the most complex manufacturing techniques on this planet what it also means is that let's say for a particular technology for let's say 40 nanometer it the fabrication will set the feature size to be 40 nanometer but not all devices on that chip will exhibit a 40 nanometer channel some will have 41 42 so it will exhibit a Gaussian curve a normal curve where the average value will be at 40 but a lot of devices will be larger than 40 lot of devices will be smaller than 40 this type of effect is called parameter variation parameters have uncertainty in parameters for example L effective VT T ox of NMOS and PMOS they vary around typical values I talked about channel L effective nothing but channel length so a device if it has a shorter L effective if it has a low VT and if it has a thin oxide it will become faster so in NMOS with a shorter L a lower VT and thin oxide will become faster you can verify it going back to the equations slow will be a slow device would be opposite that is an increased V2 a longer L effective and a thicker oxide not all parameters are independent for NMOS and PMOS that means some parameters can be linked that is let us say if a process is showing an increased channel length for NMOS it might also show increased channel length of NMOS but some of the factors can be independent between NMOS and NMOS so a graph here shows that NMOS a process can so we use two variable notation for the device speed on on a particular process we can say that a particular part a particular chip manufactured can exhibit slow-slow which means NMOS slow PMOS slow can be fast slow between NMOS is fast and PMOS is slow it can be fast fast that means both NMOS and PMOS are exhibiting fast behavior or it can be slow fast that is PMOS being slow and NMOS being fast but apart from NMOS and PMOS the VDD and T will also vary in time and space we will come to this later in detail but let us let us discuss this for for a short time we will see in detail why VDD and T will also vary in time and space let us assume for now that VDD on a chip is not let us say you apply a VDD on the chip chip pin or VDD of 1.0 volt the VDD will not remain it will not all the devices will not the same see the same VDD some will see they will all see lower than 1 volt but how much lower depends on the devices based on so if VDD is with some device let us say we compare two devices two NMOS thunderstorms one NMOS is seeing let us say 0.95 other NMOS is seeing let us say 0.9 so the NMOS which is seeing 0.95 which is seeing a higher VDD will be faster similarly let us say two NMOS are two transistors are placed far from each other one is seeing a higher temperature one is seeing a lower temperature the device that is seeing a lower temperature will be fast so here there is a table which says what will be the fast so let us say a typical voltage is 1.8 and typical temperature is 70 now at let us say a device a particular device if it sees 0 C it will become so a fast device if it for example if the voltage is higher and the temperature is lower that the chip will be faster if voltage is lower and a temperature is higher the chip will be slower so what we do is when we we call these process corners that is the process corners define the worst case operating conditions for a particular chip we cannot let us say we manufacture a chip we give it to a customer we have to tell him that okay this is the temperature range in which you can operate the chip what is the if the chip is meant for space applications the temperatures can go below 0 what if they are used in in devices that has switched on all the time let us say mobile phone the temperatures will go very high they can go quite high so we have to define a temperature range for a particular chip we will define a voltage for a particular chip these are these two are the specifications but when verifying the chip we will verify the chip at the worst case corners and obviously if the chip works in all the corner cases it should work in the middle it should work for any combination of this corners because these corners represent the extreme cases of the chip operating conditions so we define 4 4 parameters we define in more speed in more speed voltage and temperature a combination of all these will define whether the corner is fast slow or typical let us see let us see this let see how does the combination of all these corners affect some of the parameters so let us say during the design I want to the cycle time here is nothing but the frequency of operation which means the performance of the chip let us say I manufacture I design a processor and I want to see the effect of all these 4 parameters that is nMOS feed PMOS feed the voltage in the temperature on the performance so if nMOS becomes faster so let us see this table the cycle time the cycle time the performance of the chip will be worst when the devices are slow that is nMOS and PMOS are slow the VTT is less than the ideal that is slow and the temperatures again on the higher side that is the devices becomes slow so I would want to check the performance of my device at the worst case corner the worst case corner here means all the nMOS PMOS VTT and temperature being on the worst case time what about power power will be more whenever the devices are fast that is with they have low VT when the VVD is higher because power again depends on VVD and when the temperature is on the lower side so we say that we want to test power of the chip at a corner where all these parameters are at the F value that is the result of faster device similarly for sub threshold leakage I would want the extreme case would be the nMOS and PMOS are faster VDD is more but the temperature is on the higher side as you saw earlier that a higher temperature causes more leakage there is no need to fret a lot about these these corner information if it is not clear at this point of time this will become very very clear when we look at unit 3 4 and 5 but please remember that these process corners are that a fabrication process is not ideal that is all the there are hundreds of parameters and most of these parameters exhibit an average value and a normal curve kind of distribution what it means is that not all the devices on a chip are will perform equivalently that is not all nMOS will be similar all nMOS will be faster or all the PMOS will be slower some will be slower some will be faster how do we incorporate this in our digital design is the thing that we will see in unit 3 4 and 5 now at the end of this chapter I would want all of you to do some assignments which would be useful in making the concepts clear I would recommend that all that all of you if you are not already familiar with spice use some spice tool start getting familiar with it and plot the nMOS and PMOS IV curves one of the example of spice tools is L2 spice so L2 spice is a freely available spice analysis tool from linear technologies it has lot of PMOS and nMOS models but if you want to so you can use that to design this to curve the to analyze the PMOS and nMOS transfer and plot the IV curve you could also use the ASU has something called a PTA model these are the transistor models that go as low as I guess which are more representative of today's technology so what you could do is you could download the let's say you could download the 65 nanometer models from the PTA website and try to plug in these models into a spice tool so that you will be able to instantiate these transistors which which conform to this spice model so please note that in spice let's say a nMOS will always have four terminals but its characteristics will depend on what model it's linked to for example it can be linked to a that the model names are let's say B sin something it can be linked to a B sin version 3 or it can be linked to a PTM 65 nanometer so depending on on what model what spice model it's linked to it will exhibit those kinds of IV curves and you have to be very careful about the VDD so if you are using an older technology the VDD can go as big as 10 volts but when you are using PTM models please be careful that the VDD values will not should not exceed 1 volt you should also so when you plot these these curves you will also should also note the non idle characteristics whatever we discuss that is the leakage current in the cutoff region you will see the increasing IDS and so on so you should all verify the you should all look carefully at the IV curve and verify that you are in fact observing the non idle characteristics if you are not observing the non idle characteristics there is definitely something wrong with the system so it is the assignments would be very very useful in making the complex here what whatever we discussed in this chapter next chapter so this was all about MOS theory next chapter onwards we will start discussing about different types of digital design techniques we will see different logic families and so on thanks a lot