 Hello everyone, welcome to this session on flip-flop design. In the today's session we are going to learn how to design D flip-flop using JK flip-flop. So, at the end of this session you will be able to discuss the operation of D flip-flop, discuss the general model used for flip-flop conversion or design and you will be able to design D flip-flop using other flip-flops. So, let us understand what is the D flip-flop? It is also called as a delay flip-flop or data flip-flop. So, in D flip-flop output goes to the same state that is present on the D input at every clock edge. So, normally D flip-flops are used to pass data from its input to output at every clock cycle edges. So, D flip-flop is able to hold 1 bit data either you can store 1 or 0. So, because of this behavior the D flip-flop is also called as a register. So, data at input D is delayed 1 clock pulse from getting to the output. So, here 2 symbols are shown. The first symbol is a positive edge triggered D flip-flop whereas, the second symbol shown here is a negative edge triggered D flip-flop. So, in the case of positive edge triggered D flip-flop Q changes its state on the positive edges of clock signal whereas, a negative edge triggered D flip-flop Q changes its state on the negative edges of the clock signal. On the right hand side D flip-flop function table is shown in which input output relations are listed in a tabular form. So, you will see that on the clock edges. So, Q goes to the same state that is present on the D input. So, if D is 0 the state of Q after the clock edge is 0. If D is 1 then state of the output after the clock edge is 1. So, when Q is 0 this state is called as a reset state when Q is equal to 1 then that state is called as a set state. You can also imagine this as a storing 0 and storing 1 respectively. So, between the clock edges the flip-flop will not respond to your D input. So, in this case last value of Q will be stored in the D flip-flop. So, this is the function table of your D flip-flop. Now, let us understand the general model which is we are going to use for flip-flop conversion you can say or flip-flop design. So, this is the block diagram of flip-flop conversion in which you will see that a given flip-flop is shown along with next state logic. So, next state logic is a combinational circuit which accepts external inputs as well as present state of your given flip-flop in terms of Q and Q bar to generate excitation inputs required for your given flip-flop. So, excitation inputs must be provided to the given flip-flop to obtain the definite next state and new flip-flop which you are going to design inherits the triggering mechanism of the old flip-flop because so by default the new flip-flop will inherits the triggering mechanism of the given flip-flop for the design. So, this block diagram we are going to use for designing our D flip-flop using JK flip-flop. So, we need to go through some steps. So, first we are going we are going to modify this general model which we have discussed in the last slide for given specifications. For example, here flip-flop given is JK flip-flop and we are asked to design D flip-flop with the help of JK flip-flop. So, we will modify our general model according to this specifications. So, here next state logic accepts D input along with your present state of J and K flip-flop and this next state logic will generate the excitation inputs for our JK flip-flop. Now, go to let us go to the next step for the conversion we require conversion or sometimes it is also called as a state synthesis table which we are going to use to generate excitation inputs for the given flip-flop. So, this conversion table is derived from the characteristic table of D flip-flop and the excitation table of JK flip-flop. So, please pause your video here and write down the characteristic table of D flip-flop and the excitation of excitation table of JK flip-flop. So, this is the D flip-flop characteristic table which we have derived from the function table. So, here you will see that your output of flip-flop follows the D input. So, D is 0 then Qt plus 1 is 0 when D is 1 Qt plus 1 is 1. So, irrespective of old state of your flip-flop. Now, this is the JK flip-flop excitation table. So, excitation table tells you the required inputs if you want particular state for your flip-flop. So, for 0 to 0 JK should be 0x 0 to 1 if you want to change state from 0 to 1 of a JK flip-flop then input you should apply is 1x. X here denotes is either 0 or 1 then 1 to 0 your JK should be x 1 and for 1 to 1 your JK input should be x 0. Now, let us use these two tables to derive the conversion table for our design. So, JK flip-flop excitation table identifies the JK input combinations as we have discussed right now required for Qt to Qt plus 1 transitions as for the characteristic table of D flip-flop. So, this third table is the convergent table which is required for us for the design. So, here the first three columns are nothing but our D flip-flop characteristic table. We added two extra columns and these two extra columns are nothing but your J and K inputs of the given flip-flop. So, we will here decide the J and K values according to the characteristic table of your D flip-flop. So, 0 to 0 transition JK should be 0x 1 to 0 JK should be x 1 0 to 1 JK should be 1x and 1 to 1 JK should be x 0. So, now, let us use a K map to derive the expressions for J and K because next state logic is a combinational logic. We will use K map for getting the simplified expressions for J and K. So, let us derive the expression for J and K. So, from this table we will use D and Qt as inputs and we will derive the expressions for J and K. So, after putting these four values 0x 1x in the K map you will get J is equal to D expression. Similarly, let us derive the expression for K. So, again we will use this K column we will map these K column values on the K map and we will get K is equal to D bar. So, now we have our expressions for J and K which is J is equal to D and K is equal to D bar. Now, let us we will redraw our modified generalized diagram for flip-flop conversion. So, we will implement our hardware in the last step. So, we will draw the final logic diagram with the next state logic expression derived in the step 3. So, in the step 3 we have derived J is equal to D and K is equal to D bar. So, you required a JK flip-flop along with the inverter connected in between J and K input terminals. This is how you can design a D flip-flop using JK flip-flop. These are the references you can go through. Thank you.