 Hello, and welcome to this presentation of the STM32F7 flexible memory controller. It covers all the features of this interface, which is used to connect external memories such as NorFlash, NANDFlash, SRAM, PSRAM, and SDRAM. The FMC controller integrated in STM32F7 products provides external memory support through three memory controllers. The NorFlash PSRAM controller, the SDRAM controller, and the NAND memory controller. This enables the CPU to communicate with external memories, including Nor and NANDFlash memories, PSRAM, SRAM, and SDRAM. This interface is fully configurable, allowing easy connection with external memories or other parallel interfaces. The benefits of the FMC controller include not only RAM and flash memory space extension, but also the ability to interface seamlessly with most LCD controllers, which support Intel 8080 and Motorola 6800 modes. This LCD parallel interface capacity makes it easy to build cost-effective graphic applications using LCD modules containing embedded controllers or high-performance solutions using external controllers with dedicated acceleration. The FMC controller offers four independent banks to support separate external memories. Each bank has an independent chip select and an independent configuration. Each bank features programmable timings, a configurable 8, 16, or 32-bit data bus, and can access memory in asynchronous or burst mode for synchronous memory, such as NorFlash and PSRAM. Synchronous memory can be accessed at a maximum frequency of HCLK divided by 2. The FMC controller supports a wide variety of devices and memories. It interfaces with static memory mapped, including static random access memory or SRAM, read-only memory or ROM, Nor or one NAND flash memory and PSRAM. The FMC also interfaces with NAND flash memories and supports error code correction or ECC for up to 8 bytes of data read or written. Three interrupt sources can be configured to generate an interrupt when a rising edge, falling edge, or high level is detected on the NAND flash-ready busy signal. It also interfaces with synchronous DRAM or SDRAM memories. Furthermore, the FMC interfaces with parallel LCD modules, supporting the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to various LCD interfaces. The external memory space is divided into fixed size banks of 256 megabytes each. Four external memory banks are dedicated to the FSMC. Bank 1 is connected to the Nor PSRAM controller. Bank 3 is connected to the NAND controller and banks 5 and 6 are connected to SDRAM. Bank 2 is used for SDRAM bank remap and Bank 4 is reserved. Bank 1 is used to address up to four Nor flash memories or PSRAM devices. This bank is split into four Nor or PSRAM sub-banks of 64 megabytes each with four dedicated chip selects to interface with. Eight or 16-bit synchronous or asynchronous Nor flash in multiplexed or non-multiplexed mode. Eight or 16-bit asynchronous SRAM and ROM. And eight or 16-bit synchronous or asynchronous PSRAM memories. The FSMC outputs a unique chip select signal to each bank and performs only one access at a time to an external device. The external memories are connected either to the Nor PSRAM controller or the NAND controller and share address, data and control signals. The Nor PSRAM controller allows the configuration of various timing parameters for the supported memories. Address setup phase, duration of the first access phase. Address hold phase, duration of the middle phase of the access cycle. Data setup phase, duration of the second access phase. Bus turnaround phase, duration of the bus turnaround phase. Clock divide ratio, number of AHB clock cycles or HCLK within one memory clock cycle or CLK. And data latency, number of clock cycles to be issued to the memory before the first data transfer access mode. Bank three is used to interface with the NAND flash memory. It is divided into two memory spaces. Common memory space and attribute memory space. Both spaces are similar. The common memory space is for all NAND flash read and write accesses except when writing the last address byte to the NAND flash device where the CPU must write to the attribute memory space. This allows you to implement the pre-weight functionality needed by certain NAND flash memories by writing the last address byte with different timings. Each memory space is subdivided into three sections. Data section, 64 kilobytes, used to read or write data from NAND flash memory. Command section, 64 kilobytes, used to send a command to NAND flash memory. And address section, 128 kilobytes, used to specify the NAND flash memory address. The FMC generates the appropriate signals to drive NAND flash memory. The address, data, and control signals are shared with the NOR-PSRAM controller. The command latch enable or CLE and address latch enable or ALE signals of the NAND flash memory device are driven by address signals from the FNC controller connected to address line 16 and address line 17, respectively. The ALE is active when writing to the address section and the CLE is active when writing to the command section. The FMC NAND memory controller includes support for the following features. Error code correction, the ECC algorithm can perform one-bit error correction and two-bit error detection per 256 to 8,192 bytes read or written from or to the NAND flash memory. It is based on the Hamming coding algorithm. Three interrupt sources can be enabled to detect a rising edge, falling edge, or level on ready or busy signal output from NAND flash memory. Weight feature management. The controller waits for the NAND flash memory to be ready before starting a new access. The MPU memory attribute of the FMC NAND bank must be configured as a device. Each common and attribute memory space can be configured with different timings for the NAND flashes command, address write, and data read write accesses. The attribute memory space is used for the last address write access if the timing must differ from that of previous accesses in case of ready, busy management. Otherwise, only common space is needed. Four parameters are used to define the number of HCLK cycles for the different phases of any NAND flash access. Setup time, wait time, hold time, and data bus high Z time. The NAND controller offers three interrupt sources, rising edge, falling edge, and high level detection on the FSMC INT pin when it is connected to the ready, busy signal from the NAND flash memory. Banks five and six are used to interface with SD RAM memory. Each bank can address up to 256 megabytes of memory. The two banks can be used to interface with two SD RAM devices. The FMC generates the appropriate signals to drive SD RAM memory. The address and data are shared with the NOR PS RAM controller. The bank address signals FMC BA0 and FMC BA1 are shared with FMC A14 and FMC 815 respectively. The SD RAM controller has dedicated signals. SD CLK, SD RAM clock. SD CKE0, SD RAM bank one clock enabled. SD CKE1, SD RAM bank two clock enabled. SD NE0, SD RAM bank one chip enabled. SD NE1, SD RAM bank two chip enabled. NRAS, row address strobe. NCAS, column address strobe. And SDN WEN, write enable. The FMC controller offers two independent SD RAM banks to support separate external memories. Each bank has an independent chip select and an independent configuration. Each SD RAM bank can support memory devices with up to four internal banks. The device size is programmable with up to 13 bits for address row and up to 11 bits for address column. SD RAM can be addressed at maximum frequency of HCLK divided by two. Each bank features programmable timings and a configurable 8, 16 or 32 bit data bus. Multibank ping pong access allows us to perform consecutive write accesses to different banks. Consequently, it avoids bank pre-charge and row activation when the row is already activated in the accessed bank. The SD RAM controller adds a cashable read FIFO with a depth of 632 bit lines. The read FIFO is used when the read burst is enabled and allows us to anticipate the next read accesses during CAS latencies. For energy saving, the SD RAM controller can be configured in one of two low power modes, self refresh or power down mode. When in self refresh mode, the SD RAM retains data without external clocking. The device can remain in self refresh mode as long as requested by the application. The device exits self refresh mode when an SD RAM device is selected, read write operation requested, or when mode bits are set to 0000, normal mode. The device cannot remain in the power down state longer than the refresh period because no refresh operations are performed in this mode. Consequently, the SD RAM controller carries out the refresh operation. The device exits power down mode when mode bits are set to 0000, normal mode. The SD RAM controller can issue different commands to the SD RAM devices. The commands are issued by software to initialize the SD RAM device or to switch the device mode. The commands can be delivered to the two banks simultaneously using configure target bank bits, CTB1 and CTB2 in the FMC SDCMR register. The table shows the supported commands. This slide presents the SD RAM initialization procedure to implement in firmware. The FMC is active in run and sleep modes. An FMC interrupt can cause the device to exit sleep mode. The device is not able to perform any communication in stop and standby modes. It is important to ensure that all transmissions are completed before the FMC controller is disabled or the domain or system is switched down to stop or standby modes. To retain external SD RAM memory data while in stop or standby modes, it can be put in the self-refresh mode prior to entering stop or standby modes. Graphic applications require low power management together with a high quality user interface. This can be achieved using the STM32F7 to connect the display thanks to the LCD TFT controller. In addition, the FMC or Quad SPI interface may be used to access an external flash memory containing all of the graphical content needed such as background images, high resolution icons or fonts to support multiple languages. The internal RAM can be extended thanks to the FMC by connecting an SD RAM memory used as a frame buffer for the LTDC controller. Additional audio data for ring tones can also benefit from the large space offered by the external flash memory. Here is a list of peripherals related to the FMC interface. Users should be familiar with all the relationships between these peripherals to correctly configure and use the FMC controller.