 Hello everyone, in this session of unit file we will talk about crosstalk and noise, crosstalk and noise are very real tricks and for these these are my category and STA tool like prime time also gives us the functionality of setting crosstalk and noise. So we will first see what does noise mean, what does crosstalk mean and how prime time what methods does time-time apply to take crosstalk and noise problem and what are the reasons behind noise and crosstalk of this and why is it a newer phenomena then, so earlier in in technology dating back to 19 nanometer or 150 nanometer, very I mean crosstalk and noise was very minimal and even 13 nanometer and with larger technology and bigger technology we did not even check for it. So what is changing in lower technologies and what is calling to become a boundary to take these big C. So noise is something which is called by crosstalk, so the reason why the noise plays an important role in the micro is that, okay look at this trigger first. So earlier earlier technologies you had the metal layers were further apart and the means the it was the packing density was there for number of metal layers and number of metal layers have been improved a bit. So now the metal layers are packed close and close together what this means is that, so to compare two technologies, the metal layers are nearer there and what it means is that because of the increasing number of metal layers higher routing density, so these are important keywords here, the increasing number of metal layers higher routing density, we are now packing because of the lower feature size of the transistor we are now able to pack more and more transistor what this means is that, okay yes we are improving the number of devices, we are improving the number of function on a particular device, but the metal layer we are not scaling according to that according to moves right and the scale according to moves the, but metal layers do not scale that height right, so but because of the increasing number of devices and increasing number of function on a scale, the routing density is now huge that is compared to let us say two or three people and the, so this means that the metal layers are coming closer and closer together, when the metal layer is coming closer together, the capacitance between them now cannot be improved earlier it used to be minimal, earlier the coupling capacitance, coupling capacitance between two metal layers, earlier this capacitance used to be minimal and used to be actually very small when compared to the capacitance of the net with respect to the law, now these capacitance are not trivial, one more effect is that they are lower supply voltage, lower supply voltage means the noise effect let us say a 0.1 volt of noise and the supply voltage of 1.2 will not make that big a difference as it will do to a supply voltage at 0.9, right, so lower supply voltages means that now the lights are not going to noise, also the waveforms are faster because the frequencies we are targeting are more now the CPU frequencies are increasing like everything, the desktop CPUs have gone, the normal thing we have gone so on. So, there are faster waveforms now due to have increases all these effects, they are causing noise and crosstalk to be a dominant factor now, so this is one example where you have this net 1, net 2 and net 3, now between net 1 and net 2 you have a coupling cap of C C 1 and C C 4, the C C 3 is connected from N 2 to N 3, so C C 1 and C C 4 is the coupling capacitance between N 2 and N 2, if you talk about net N 2 and N 3 you have C C 2 plus C C 5, similarly N 1 and N 3 you can calculate so these capacitance is now coupling capacitance are now not negligible when compared to the cap with respect to ground, so the cap with respect to ground is responsible for the increasing delay right, the negative is responsible for the negative, it adds to the load at the output point of the terminal, but the coupling capacitance what it does is that it will cause an effect which is called again called crosstalk, is that the signal change here will affect the signal value here, so noise and crosstalk they both are the effect the causing effect is same, but noise is some we will differentiate between noise and crosstalk but so this is the effect that the coupling capacitance is following in fact a signal being on one net will cause something to happen on the other end, if the coupling capacitance is not there it will not happen, so since the coupling capacitance is becoming more and more significant these effects are more and more pronounced now, so effect of crosstalk, so crosstalk is you can say the crosstalk is happening, but the non-trivial coupling capacitance and there are two effects, one is noise other is crosstalked, what is noise, noise so in both the cases in both the noise and crosstalk delay there is one aggressor line, aggressor line means the one that is changing its value, now in the case where victim line, so now this aggressor line is changing its value and it has a coupling capacitance with respect to a victim line, so in this case let us say for example, I can see that n 1 is aggressor n 1 is changing its value, n 2 is holding its value and n 2 is practically one of the now if the change on the aggressor effects the logical value on the static signal and if it can cause a cause a noise as well as the logical failure then this is the point now right, what it means let us say the buffer here let us say the buffer here the the buffer here is driving a 0 and this the signal on n 1 changes the problem to 1, now if the one here causes a bump here and if this bump this bump because this the aggressor is changing to 1 it can cause the voltage at n 2 to write to a certain value and if this bump is greater than the noise margin of this buffer this buffer here then it can change the logical value ideally the logical value there also would be 0 at the end of the buffer 2 here, but if this bump here gets this buffer is the height of it is greater than the noise margin of this buffer then the logic value at the end of this buffer will not remain 0 it will again show up on this is called noise. So, noise is the case where the aggressor line is changing its value on the victim is stopped right, crosstalk delay is the effect where aggressor line is changing its value and victim line is also changing its value the effect here is that the victim the aggressor will force the victim line delay now the delay when you talk about delay we mean that there is some change in value right that is that is what delay is for for example, a buffer delay is nothing, but into change to output change the time to now in this case the victim net is also changing its value. Now, this cross this effect can make this change in value a bit later or a bit later or a bit earlier. So, it can cause the delay to be more or less right. So, aggressor is see this figure here aggressor is switching rising or falling victim is switching rising or falling there is a coupling capacitance of C there. So, instead of this waveform this kind of waveform instead of this kind of waveform due to delay the waveform can be like this. So, this is so in this case it is causing the waveform to be delayed. So, it will increase this delay increase the latency right. So, these are the two sets. So, the the cause is same the cause is non-trivial coupling capacitance and it can affecting two ways one in terms of delay second in terms of noise right. Now, let us discuss more about cross swap glitch glitch is glitch or noise is the same thing we use them in touching nearly for for noise analysis. So, steady state signal again remember that glitch is caused on a steady statement right the net which is holding its value and if a glitch is observed on that net because of the coupling capacitance to the aggressor this effect is called glitching or annoying. A steady state signal net can have glitch positive or negative due to charge transfer by the switching aggressor to the coupling capacitance. A positive glitch induced by cross swap from a so see here that this this NAND gate here is changing its value. So, it it is an aggressor net there is a coupling capacitance C C with respect to the victim net the 0 to 1 here can cause a rising glitch a positive glitch at this net because of the charge sharing net at the victim net. The NAND 2 cell switches and charges its output net labeled aggressor some of the charge is also transferred to the victim through the coupling capacitance and the virtual positive glitch right. Now, what is one thing that is most important is the magnitude of the glitch and the magnitude of the glitch is that how big is the glitch is it big enough to cause a logical failure or is it small enough this this is very important factor in the configuration because it still enables the prime time tool to check whether the noise is below or above the noise margin of the assistant. Now, it is dependent on a variety of factors one obviously on the coupling capacitance the greater the coupling capacitance the greater the charge sharing and greater the magnitude. The transition of the aggressor net the faster is the slew at aggressor net the larger the magnitude of the glitch the faster is the slew means the driver is very strong. So, usually strong drivers big drivers are very big aggressors also because they cause a very fast transmission this you can say that whether the faster transmission is the cause or the the underlying cause is actually the higher drive strength of the aggressor. The victim net grounding capacitor the smaller the grounded capacitance of the victim net the larger the magnitude of the glitch. So, you can say that it is it is dependent on the ratio of coupling capacitor the ground capacitance. If the coupling cap is much more than the ground capacitance it will be more affected by the noise. If the ground capacitance is more obviously the ground capacitance is more it will help in diminishing the effect of noise right. Then the victim net drive strength again the ratio we are talking about the ratio of the aggressor drive strength to the victim net drive strength. Usually noise problems occur for cases where the victim net is a weak driver like X 1 or X 2 and the aggressor is a strong driver like X 8 or X 3. So, the types of glitches are rise and fall glitches and overshoot and undershoot glitches. When the rising aggressor couples to a victim net which is steady high and steady high means it is almost a VPD and there is a glitch which takes the victim net above its VPD value it is called an overshoot. Again noise that takes a victim net already at 0 to something below 0 it is for under truth. So, this figure will tell everything with them if it is high maintained high aggressor rises there will be overshoot glitch this is VPD this value is VPD this overshoot glitch takes it beyond VPD. If victim is falling it might take aggressor down with it it will take aggressor down with it and this will be fall glitch fall glitches then victim is 1 and the noise causes it to fall below 1 or below VPD. Again if the victim is steady state low aggressor rises it will cause a rise bump this is called the rise glitch. If the victim is low aggressor falls both case aggressor falls it might take it below 0 it is for under truth right. So, 4 glitches overshoot is beyond VDD or beyond. So, overshoot and undershoot are come in the category of beyond rail noise volume these are called beyond rail. Overshoot goes beyond VDD rail undershoot goes below VDD below 0 rail below ground rail other ones are rise and fall simpler than all this right. Now so, let us say a glitch let us go to the figure here. Now a very important factor in which is which calculation is the calculation first and then see whether it can propagate. So, for example for example, let us see here first thing that the tool will do it will calculate the glitch let us say N 1 is aggressor and tool is different. It will calculate the glitch it can do and then it will evaluate whether this glitch can propagate through this buffer. So, the slide here is will make us understand how this happens. So, the glitch caused by coupling from an aggressor can propagate through the cell depending on the fan out cell and the glitch attributes such as glitch height and glitch width. So, there are two analysis that are performed here one is the DC noise analysis. So, DC noise thresholds this this analysis only examines the glitch magnitude only from the router. So, just take into account what is the glitch height height means what is the maximum value. So, there are two things with respect to a long with respect to a glitch see this. Let us see the rise glitch this is the maximum value up to which the glitch the bump goes. So, this is called the magnitude of the glitch the magnitude of the glitch is the maximum rise or drop in the voltage value the width of the glitch is how much time how much while the glitch is what is the amount of time during which this glitch is active we have two effects it. So, the DC analysis only depends on the magnitude on the height of the bump the AC analysis examines other attributes such as the glitch width and the fan out cell what is the form of the output. So, let us see what all both these analysis do. So, please remember usually when you work in time time when you start noise. In most of the cases you will not have to do anything you just have to enable all this data the noise thresholds and all that we can usually come from the library the format the library still. The non-linear delay model is only for delay is not for noise the just because there is a separate now the more popular model is CCS the constant current source model. Now, the constant current source model supports all three things it supports delay it supports power it supports more. So, if you are reading a CCS enabled library then the noise data is already present there noise thresholds are present there the current waveforms are there. So, reading after reading this library time time can do we really do noise analysis right. The only there are some cells and amount of macros for which you will have to define the noise model may be, but otherwise if the noise analysis does not need a lot of testing of the device, but it is time consuming again if people use this. So, the DC margin is a check if you remember the the most the most famous waveform of an inverter output output V out versus V in waveform. Now, wherever the unity there is a unity slope on these two points we calculate two values VOH min, VIL max, VOL max and VIL min. Now, let us say this buffer is at a receiving end it is the it is into the fan out of a victim. Now, the two things are important here one is VIL max another thing is VIL min. So, DC margins are based on VIL and VIL are steady state noise limit. These can be used to filter whether and determine whether a bridge can propagate to the fan out cell or not right let us see. So, anything that is on the lower side any voltage that is greater than VIH min can cause a bridge to propagate on the higher side if it is lower than VOH min it can cause a bridge to propagate right. So, DC noise margin can also be fixed to the same limit for all next of the design. This is this slide is telling us that if the noise values are not coming from the noise values are not coming from the noise values then you can assign some values and assign them to all the next. Now, let us say I say that ok I calculate the noise or I somehow get the noise VIH and VIL values for a particular inverter. I can use the same value for all the next design I can say that let us say I say that VIH let us say for our 1 volt technology I say that both have 0.1 or 0.2 lecture. So, any bound which is greater than 0.2 will only propagate I can set this value I can set a command perfect noise model of this value for all the next design. So, this will check if the margin value is not coming from the value I can calculate a conservative value and apply to all that that is what it is recommending that one can set the largest tolerable noise above which noise can be propagated to the cell right. So, typically this check ensures that this level is less than VIL max and greater than VIH min. So, the question is that will this propagate will this height particular height of the glitch will propagate to a particular form. So, there is a VDD and what we have done is that between VDD and VSS we have plotted two values of VIL max and VIH min. Now, VIL max means now this among all these cells that we are using what is the maximum VIL for all the among all the VIL values this is VIL model. This is not actually conservative analysis this is you are choosing just some value you are choosing just some maximum value to be conservative you have to actually choose a minimum value right because you want that prime time should not filter out any noise that is greater than the that is more than the least noise model among all these right. Do not worry about it when you do noise analysis most another probability you will have a standard cell that way that you have individual noise margin data for all this right. So, this is the case for the case where you do not have the noise margin data model you are fine. So, in this case this is the one method lobby of a problem with one model. Whatever be the case how crimson analyzer is thatthere will be a line of VIH min and VIL max any glitch below VDD that is not that does not touches VIH min is ok. Similarly, any glitch beyond VSS that does not go beyond VIL max is safe these will be filtered out by some now if you remember in unit 1 unit 1 and 2 we talked about the CMOS we were comparing we were comparing CMOS technology with other technology with the ratio of logic with the domino model and so on. And we found out that the CMOS circuit is very good in terms of handling loss and it is the case it is the most superior in terms of handling loss the complementary CMOS right. So, any glitches which are this is noise margins when I say that it is most competent handling noise which means that the values the noise margins are very good. So, most of the glitches are filtered out by the phase boundary right a small any small glitch which is below the limit will not propagate at the output of the problem at any glitch which is higher than this are potentially hazardous they have they can effectively they can let us say now this goes to a this goes to a plot resection and let us say there is a noise of this time and this resection let us say that divide. So, you have a noise of this time. So, if the input is this there will be bump here and this will cause the plot to reset it is very very dangerous right that is why prime time will apply a filtering criteria based on the noise margin on the filter noise margin and it will filter out all the noise which is below this moment right. Now, not all not all glitches if magnitude greater than DC noise margin can change the output of the cell the bit is also important that means, if the the glitch is very narrow if it is very quickly it goes to the bump if there is a very narrow bump. So, the slides talk about the difference between these two cases where there is a narrow bump and draw it again. Now, let us say there is a the height of the bump is same, but one bump is narrow, but one bump is wide. So, not all narrow bumps will go through the cell and some of the wider obviously, the wider bump will go through because it allows sufficient time for task to properly input not all narrow bumps will go through. So, the bit of the glitch is also important consideration a narrow glitch cell input will normally not cause an impact. However, DC noise margin uses only a constant worst case value. So, DC noise margin does not take into account the bit of the noise. So, idea noise analysis algorithms let us say 3-4 years back use only the bit use only the height of the noise bump to propagate the glitch, but nowadays prime time it also it uses AC analysis and also takes into account the bit of the glitch. So, this is what AC threshold is all about look at this does not this slide does not show dark and white shades, but I will point it out the dark shade region represents the good or acceptable input. This is the the darker shade where the so there is a DC noise margin and then we are we have plotted the glitch height. So, this is the glitch height on which we have plotted the DC noise margin and now there is a glitch width also. So, these this area belongs to the glitches that have lower widths. So, this is the safe area. So, as the glitch height keys are increasing the safe area becomes narrower and narrower. That means, now we are worried about the area of the glitch. So, the glitches if it is narrow, but it is too tall the area will be more. If it is even if it is shorter, but it is more wide the area will be more. So, it becomes shorter it stops martyring after below the DC noise margin that means, any noise any noise if it is highest value is less than the DC noise margin will be picked up, but more than this if any noise is greater than DC noise margin. Now, we have to also think about the width of the small if the width is more if the width is more glitch width is more you are now going into area of potentially hazardous glitch. If the width is less you are more into safe area what it means is that now there are two conditions that need to be satisfied for a glitch to propagate one it is maximum value should be greater than the DC noise margin this value here and it should be wider beyond some surface. The width is dependent on the AC analysis and therefore, it is a time consuming analysis and we will see what all DC will do to do AC analysis. But this thing should be clear that the height and width are both important right the height obviously, should be beyond the noise margin the width is a separate case if it is too low it would not affect if it is wide enough it will affect right. Now, now let us see the case where the the output cap is lower or high now let us say there is an input without an output load a positive glitch at this input now this bit is being caused by some other example right some other and if there is no load here that means, the cap resistance to ground is almost non-existent. So, it will have the maximum effect of the load right assume in all the three cases that the glitch input is greater than the DC noise margin and it will cause a glitch with the inverter output. If the inverter is driving some output load. So, the glitch effect will be smaller if it is driving a higher load the glitch effect will be smaller it might be non-existent. This is because now the this capacitance keeps on increasing and it keeps on going beyond the coupling capacitor. So, this is the reason why it is now not a good practice to leave the output of the output it can cause a big noise on this on this net and although it would not affect any logic value at a first glance because it is not driving anything, but this glitch now can cause some other effect some other coupling capacitors that is why we will always make sure that any cell should not should not the output should not be hanging it should be the grounded or or the cell removed right. Now, there can be more than one aggressors because a net has a lot of surrounding net and it can have more than it can have 2 3 4 5 aggressors. Now, when multiple nets are switching concurrently the effect is compounded due to multiple aggressors this is one effect where there is coupling capacitor this is the case where there is only single aggressor. So, now what complete accurate analysis what 30 minus 2 is that it should also so, not all let us say a net has 4 aggressors. Now, what is the condition of noise noise condition is that the victim net should be something and the aggressor should be switching. Now, do we assume that all aggressors are sitting at one time or do we assume that one aggressor is sitting at one time assumption our assumption will change the noise calculation if all the aggressors are sitting at one time and if they are switching in one single direction. So, here two things are important the timing of the city and the logic level from which they are sitting if all the aggressors are switching at one time and at one direction it will cause the maximum gain all other cases will be less worse than this. So, what what does time time do now please note that time time is the timing tool at each because of the for example, you talk about register to register time path it knows when the nets between these two registers are sitting and what is the the baseline had the baseline had is clock to do. So, as you may cross it is a zero writing that zero it knows about all the nets in that time path it has to think with respect to the clock at what delay they are switching at after what time it has to this is called a timing window arrival timing window. So, prime time being a timing tool at each node it knows what is the arrival timing window and it will use that arriving timing window all this is to determine the magnitude of noise. Let us see this example. Now, let us say there are four aggressors with different glitch heights the glitch heights being 0.11, 0.1, 0.09, 0.2, these design terms of voltage and being a timing tool prime time has the timing window information for example, 0.1, 0.10, 0.11, 0.8, 0.5, 0.4, 0.5, 0.6, 0.7, 0.5, 0.5, 0.9, 0.5, 0.5, 0.9. These are the visual behavior of the glitch. So, these are the visual behavior of the glitch. So, the result is 0.1, 0.5, 0.5, 0.6, 0.4, 0.7, 0.4, 0.5, 0.9, 0.5, 0.5, 0.4. Now, what is the possibility value of the glitch? between 3 and 4 only A 3 is switching so, 0.2 between 4 both A 3 and A 4 are switching so, it is 0.32. So, this example is not talking about the direction of the glitch that is it is not worried about whether they are rising or falling it is assuming that all the transition are happening in the same direction. So, this is how time time does a timing window based on correction and it is obviously the most accurate you cannot assume arbitrary timing window. The timing window is depend on the clock the clock relationships for example, if the clock are reaching here then if the tool lets if the aggressor and which is are asynchronous to each other in terms of clock domain. Suppose A is on clock domain A let us say the aggressor is on clock domain A victim is on clock domain B and if clock domain A and clock domain B are all asynchronous values then the timing window will be incident that is asynchronous means that the signal can switch at any time, but if both the nets are in synchronous domain that is if all the four are in synchronous domain or all the four are working in the same clock and the victim is also in the same clock then proper timing window and which is should be done by the tool this is the accurate way of doing things this is why noise and cross talk becomes so complex in terms of complete resources right. It needs to store the timing window at each and every node it needs to calculate the glitch on cross talk for all the spaces that is why when you start enabling noise and cross talk in the form of the run times become huge right. So, this is how the timing window correlation is going again there is something again we I said that actually the three sets that are taking into consideration of the problem window. Second is these function correlation versus the timing correlation second is the function correlation and based on this it will calculate whether the base will propagate or not. So, this slide was timing correlation this is function correlation for multiple aggressors again it needs to know that now the next one N1 has coupling with N2 N3 N3 N4 N4 is a assume N4 is a assume that N4 is constant now N4 although it has coupling with N1 it is constant the constant net cannot cause any noise or cross talk on the other net this effect should be discarded right N2 is a net that is part of debug bus, but if the chip is in function mode this will also be constant. So, N2 set is also not there this is where PT needs to know about the function values. So, if you have set some case analysis on N4 if you have set some case if you do some case analysis now case analysis propagates if you do some case analysis N2 is also grounded or tied to VDD then these effects are not taken into consideration right. So, if N3 carries some critical data and so N3 can only be termed as a aggressor for this N1. So, prime time needs to know the it will use the same or fundamentals it will use for delay calculation it will propagate case analysis for noise also make sure that none of the constant net is an aggressor plays an aggressor it will also take care about it will also calculate the timing and dose and worry about whom going. So, this was all about noise. So, important things first thing to know what is the definition of noise the victim net is static it is not changing aggressor is switching what is important here is coupling capacitance of the all three type of coupling capacitance and the capacitance of the victim that is put around the dry strength of the aggressor and dry strength of the victim these are the causes that can magnify or reduce the noise then how does noise propagate DC noise analysis which we worry about the bump the height of the bump the AC noise analysis in addition to the height of the bump we are also worrying about the width of the bump last important factor timing correlation and function correlation. So, prime time consider see now how the how much data now state to have to has to comprehend now it has to comprehend the noise margin it has to take into account the coupling capacitance it has to take to DC analysis AC analysis timing correlation function correlation this is why for a even for a small chip the tool like prime time needs a machine to be be a prime 15 be be a prime because the amount of data is huge there are millions of nets that millions of coupling capacitance. So, now let us talk about the so we were talking about noise apart from noise there is also a case of delay the delay meaning that aggressor is switching and victim is also switching now based on the the direction of switching the victim net can be delayed the victim transition can be delayed or made to become earlier this is called the delay. So, ok this is the same example where the aggressor has some coupling capacitance with net. Now, now different scenarios the capacitors charge required from driving cell can be different. Now, let us see this case where there is the capacitance the coupling cap is CC the grounded cap is CG aggressor and victim. Now, when aggressor net is steady the driving cell from N 1 net provides the charge for CG and CC to be charged to be DD. Aggressor is steady the victim rise rising, but now it has also CC in place. So, it will lead it will charge both CC and CG to be DD. Aggressor net is switches in the same direction the driving cell is aided by the aggressor switching in the same direction. If this is switching in the same direction as the time of this switching if the timing will go up here then aggressor is helping is helping to be DD to switch to be DD. So, it will it will help in the delay part that means, the delay will be less now. Case one is when aggressor is silent it is not switching there will be some delay x, but when aggressor is switching in the same direction it will help this help the victim and now the delay will be less than x that the the driving cell aided by aggressor switching the capacitors by driving is DD. If the slow of the aggressor net is faster than that of N 1 the actual charge required can even be smaller than CP DD and it will help the delay will be less than x. If the aggressor is switching in opposite direction the coupling cap is charged from minus to be DD to be DD and the charge and coupling capacitor changes by 2 into CC DD before and after combination right this will not help this will make the delay more it will make this has to now work as CD because it is switching in the opposite direction. So, the delay will be more than x. So, this is called positive and negative cross talk the example is here the charge required for the coupling capacitance is larger when coupling net and victim net are switching in opposite direction. The aggressor net is switching in opposite direction increases the amount of charge required. So, this is an example of positive cross talk where this is this is falling this is falling here and this is rising the effect is that earlier if it is in the ideal case this was the base form the dotted line was the base form, but when the aggressor is switching in the opposite direction there is a delay because of the charge chain at CC. CC needs to be charged from the charge changes 2 into CC to be DD. So, this causes a delay and therefore, signal which was arriving earlier is now a delay this is called positive cross talk right positive why positive because it is resulting into a increased delay. Negative cross talk whenever the switching is in the same direction this is the ideal waveform dotted one, but it will make it will make the switching a bit early this is called negative cross talk delay why because it is making the delay less. So, it is a negative cross talk delay. So, cross talk can either increase the delay or reduce the delay. Now, this is noise was separate noise was separate than delay although timing in the information is coming from the delay right, but noise is resulting into the incorrect logic, but cross talk now affects us at the full timing type is in that because the delay to the next can be either more or less than the ideal case. Again this delay depends on the timing window same timing in window information that is used for noise is used for cross talk delay. You again you have a 1 a 2 and a 3 and there is a bit in there bin 1 a 1 and a 2 they are switching at the same time bin 2 has the 2 has a 1 a switching whether only a 1 a switching b 3 only a 3 switching. So, we have the values here 0.1 2 0.1 4 and 0.3. So, in bin 1 the effect is the cluster delay in practice 0.26 bin 2 has only a 1 0.1 4 then 3 has only a 3. So, the same timing window information that was used for noise is also used for cross talk right. So, this is the timing window information now see now the here in this case the victim net is static. So, this is a noise gain. So, any switching here any switching at early arrivals will only cause noise it will not not cause cross talk delay, but now the victim is switching it is switching and any switching here then any switching of aggressor here when victim is switching will now cause since it is switching in the opposite direction it will cause it to delay delay starter. Now please remember the delay is usually from 50 percent threshold, but now the 50 percent threshold moves to the right. So, there is more delay again if the aggressor switch is late it will only cause noise. So, this actually this diagram here nicely captures the difference between algorithm with if the victim is static it is noise which are these two cases here 1 and 2. If the victim is changing aggressor is also always changing aggressor means aggressor means that there is some value change if the aggressor net is static it is more aggressor power right. So, any change in aggressor if it happens when victim is static is noise whenever victim is changing value then aggressor will cause it to either change late or change earlier this will effect the delay. So, please be very very clear about what is noise and what is cross talk. So, timing verification now noise is separate analysis, but now cross talk comes into R set up holdable because the delays are effective any time any physical effect that causes the delay to change will change your timing analysis right will make it more difficult for you. Timing verification using cross talk delay this is computed for every single internet in fact it is a net effect not a cell effect. So, there are four texts here positive rise delay, rises move forward in time, negative rise delay, rises move backward in time, positive point delay. So, in effect there are two rises for this two different transmission direction. So, it is either positive or negative, positive means delay is more negative means delay is less. Now, what do you think what is time time do not? It will calculate cross talk, but now it will assume the worst case always like a OCD it assume that in better case the data path is delayed as more delay. In whole it assume that the data path is less delayed same happens in cross talk. In better analysis it will make the launch clock path worse than it was earlier before. It will make the data path still worse what it means is that any cross talk in better check any cross talk calculation will delay this more delay the launch clock path and the data path clock path more it will never reduce the delay on data path or launch clock path it will make the delay more. So, now over and above OCD the cross talk will add delay to the set up launch clock path and the data capture on the clock capture path it will reduce delay right. So, again let us let us summarize the figure here the setup and let us assume that launch clock path sees positive cross talk delay, data is launch date data path sees positive positive positive. So, that it takes longer for the data to be the destination capture clock path sees negative cross talk right. So, assume a so again there is a common clock point I will tell you what how this affects the analysis later, but again apply the same principle if you were trying time your job is to always assume the worst case right what is the worst case for setup the data getting delayed and the capture clock coming earlier this is the worst case for setup. Similarly for hold the worst partition is when the launch clock comes later when the launch clock comes earlier capture comes later. So, launch clock path and the data path will have negative cross talk delay and the capture will have positive cross talk delay right. So, this this slide just lists that that capture clock has positive launch and data have negative this reverse of what happened in setup right. So, again when we talk about noise and cross talk we have to take care of the computational complexity a large animated design is really too complex to allow every coupling capacitance to be analyzed this is the key here. It is not possible for prime time to analyze every coupling capacitance with reasonable turn around time. So, there are some settings to make this analysis more practical. So, there are some some techniques one is the hierarchical design other is the filtering. So, what hierarchical design means is that now let us say a chip has 20 blocks 20 individual function blocks and at the chip level these blocks are just paste together. So, synthesis also would need you to synthesize every blocks effectively because a full chip synthesis might not be a good idea because again it will take a large amount of time right. So, usually what it does is done in that industry that all 20 blocks will be synthesized separately and then switch to the top level ok. For cross talk also we will do noise and noise analysis and cross talk analysis individually at each block level we can do that. So, this would mean that this can only happen. So, hierarchical design assuming that for large design. So, we can do that noise analysis and cross talk analysis at the hierarchical design that means all 20 would be done separately. This can only hold through when this implies that there is no coupling between signals inside a hierarchical block and signal outside the block. This is true for the case where all 20 blocks have separate layout. So, ideally so that you just working through that first you define what is a function block. So, I say a chip has 20 blocks let us say how we have CPU it has a memory controller. So, memory controller and CPU they all are function is separate block although they have obviously some communication between them, but consider memory controller now memory controller is separate function block it also would be separate layout block. It usually does the case it is a separate function block it is a separate mode block. So, it would be synthesized separately the timing the function timing would be closed at a block level also plus all the noise and cross talk data would be analyzed at the block level at the memory controlling level and not at the chip level. Now, this memory controller layout synthesized separate it will not have any coupling with your CPU or CPU because they are set located in a different part of chip. So, this is what it says there this implies that hierarchical analysis implies that there is no coupling between signal inside hierarchical block and signal outside the block. Now, at chip level you can say that you can say that all my function layout blocks are blocked off and do the coupling analysis only for signal at the top level right. Many things might be confusing here what I said, but when you work in industry when you talk about you know you will know that you will understand how to do that. Now, again so this third is that this also this goes on the setting point that signal net should not be routed close to the boundary at the block because if the signal net in a hierarchical block or routed close to the boundary then the signal outside the boundary at the top level will start affecting and the assumption that there is no coupling between the block and the outside of the block does not work right. Second is filtering of coupling capacitor in this the filtering is that filtering I usually the prime time will carry out obviously, there are some variables to control the filter process. So, if you filter out there is a variable that controls that how a smaller value of coupling cap can be filtered out for example, below 1 times of error you can filter out the coupling cap. More important than the absolute value is the coupling ratio. If you say net with small coupling ratio coupling ratio is the ratio between the grounded cap and the coupling cap. If the coupling ratio is very small they can be filtered out they can be used for analysis lumping small aggressors together multiple aggressors with small contribution can be mapped to one large virtual aggressor. This is just this other filtering is being done at the coupling cap level right. First two were done at the coupling cap level third is done at the calculation level that means the prime time sees that there are lot of small aggressors it will make a virtual large aggressor and it will make a lumped aggressor. So, this exact subset of switching aggressors can be determined by the statistical methods. Let us not worry too much about the statistical methods. So, how do we enable noise in crosstalk? First important thing when we read parasitic from a step we have to include this switch keep capacitive coupling. This tells otherwise prime time with ignored the capacitive coupling and no noise data knows no crosstalk. Then report timing has a crosstalk switch report delay calibration has a crosstalk switch you can use one of crosstalk switch. All usually all delay reporting commands will now have a crosstalk data switch where it will tell you in addition to the delay which will tell what is the crosstalk. This is the timing report with the crosstalk delay apart from so you have seen the path column you have seen the incremental column now there is a delta column also. So, see that this is the non-strat this is the non-strat these values are positive. So, this is the setup report why because it is a max it is an asynchronous default group with the reset path. So, in the data path you will always see for setup in data path you will always see positive value not negative value. Apart from transition there is also deep trans which means that so crosstalk effects both if you also delay the treatment and it will also make the transition work. So, it tells what is the D-trans what is the delta transition this is the delta time. So, this delta time is added to the path this delta transition is added to the actual transition. So, the delay will become worse the transition has become worse. So, you can spend some more time in the following report usually the only special thing here is the delta and the D-trans this is the only new thing. Now, let us talk about clock relationships. So, now see we talked about timing windows we saw how noise and crosstalk analysis is affected by timing window we saw few examples where there are more than one of them. Now, the timing windows depend a lot on clock in fact, clock is being so if you have multiple clock then your clock relationships will affect the timing windows. Now, I mentioned before in the in all the different that let us say now these two clocks clock 1 and clock 2 are false to each other where it is just to each other. Now, there are multiple ways of defining this one is the set clock groups. If you are doing noise and crosstalk analysis do not use set false path to set false path between two clocks use set clock groups this is the prime time requirement set clock groups set prime time exactly what is the relationship. So, there are three situations asynchronous logically exclusive physically exclusive asynchronous means that both the clocks they are asynchronous to each other, but they are both existing on the tip what it means that now let us say assume clock 1 and clock assume there is no much there forget about this this structure here assume that there are two clocks coming from separate separate sources clock 1 clock 2 this is let us say this is clock 2 and this is clock 1 and now clock 1 clock 2 if they are there are two clocks which are existing on the tip at the same time they can come from different PLL for example and there are two nets there are two nets two nets which have a coupling cap and one is driven by let us say this is aggressor it is driven by clock 1 this is within this is given by clock 2. If they are asynchronous to each other it will assume an infinite timing window on one prime time why because they are asynchronous data on one has no synchronous relation to put data on two. So, the aggressor will have an infinite timing window that means aggressor can come at any time. So, any transition on two will always be affected by this always this is what asynchronous does. Now, let us see second case logically excluded now you have this kind of the tip now clock 1 and clock 2 only one can occur at this point only one can come at this point right. So, beyond this point we have to set clock 1 and clock 2 is logically excluded what it tells fine fine is that clock 1 and clock 2 are logically exclusive which means that any crosstalks. So, now this x 4 is the coupling cap now if if clock 1 and clock 2 are asynchronous this would have an infinite timing window, but now there can be only two cases once at this point at this point either it is by clock 1 driven by clock 1 or driven by clock 2. So, when it is driven by clock 1 or clock 2 then there will be proper timing windows on this net on the aggressor net and mismatch there will be proper timing window calculation there will not be infinite timing window and effect of x 4 will be taken into account right, but effect of x 1 this now they cannot there can be a coupling cap between clock 1 and clock 2. So, this will analyze the x 1 effect also because it is, but now you want to you want to ignore you probably want to analyze x 1 also why because beyond this marks x 1 is before this mark the clock 1 and clock 2 exists before this marks right. Physically exclusive that is the case where there is a there is a the clock for example, is coming from out right and on the same clock port you can have two different clock. Let us say in one application you can apply one clock to the chip port another application for example, test mode you can apply on the clock of the chip port. Now these clocks are physically exclusive what it will tell prime time in that it will never do it will never launch on one clock and tap in another clock in terms of cross talk. So, the timing windows again will not be infinite there will not be any cross talk effect which is special to the two clocks being taken right they are physically exclusive they cannot exist to them right. Now see this if you want now this is the case this is slightly complex case where you want the effect of x 1 to be taken care. So, what do we do right we do something like this even if you do not understand this do not worry about it there is a clock 1 and clock 2 we create generated clocks here we create a generated clock GCLK 1 which is divided by one version of clock 1 we create a clock GCLK 2 which is a divide by one version of clock 2. Now we said GCLK 1 and GCLK 2 to be logically exclusive. So, there will not be any infinite timing window, but clock 1 and clock 2 are asynchronous they are not logically exclusive now. Logically exclusive part is now shifted to GCLK 1 and GCLK 2. PLK 1 and CLK 2 are still asynchronous. So, cross talk checking will happen here. So, even if you do not understand do not worry, but take one the gist is that the clock relationships I will just summarize this the clock relationships are very important for noise and cross talk really calculation. If you are using if you are doing noise and cross talk really calculation use that clock this command. Third important point be very sure about whether the clock are either logically exclusive or physically exclusive this is the summing actually I should have a slide of summary here and probably at this data, but ok. So, we we we studied about as the last slide. So, we talked about the noise and the cross talk both cause are caused by the same effect same physical effect noise is the case where victim is static cross talk is the case where victim is switching and the cross talk causes the victim net to have a worse or a better function and worse or a better delay. So, this is the delay part this will affect the full time in exactly similar manner as you see for setup which the launch part the clock part and the data part will be delayed by more will be more have more delay the capture clock part will have less delay it will be the other way round for whole analysis. Again we see that you need to be very good at understanding clock relationship for noise even for timing for timing and for noise input for for signal integrity this is the noise and cross talk combined together this is called signal integrity. Signal integrity is another term for cross talk right. So, for if you are doing signal integrity analysis you have to be very very sure that you have to use that clock books command or defining the clock relationship in time. It was all for noise and signal integrity I will not we will not have a lab of this because again we need very good back end data to do lab. So, I try something if I am able to come up with a lab I will improve this obviously, but as of now I do not have any lab for noise and signal integrity this is because it is like advanced topic when you consider the limits of this course. In the last session of unit size this was the second last lecture session of unit size. In the last session of unit size we will study about the I will give you some introduction about the statistical analysis. Thank you.