 Hello everyone, myself Sanjay Uttgay, Assistant Professor, Department of Electronics Engineering, Valchand Institute of Technology, Solapur. Today, we are going to discuss on Ring counters, application of shift registers. Learning outcome. At the end of this session, students will be able to describe various types of shift registers and their applications. Outline. Introduction to shift register. Types of shift register. S.I.S.O. Serial in, serial out. S.I.P.O. P.I.S.O. P.I.P.O. Question. Answer. Ring counter. References. Group of flip-flops. Shift register. In the previous discussion, we discussed a one-bit memory cell that is a flip-flop. Flip-flop is a storage device used to store a one-bit of information. To increase the capacity of stirring, we can make a group of these flip-flops. So, the circuit is called as a shift register. Shift register is implemented using flip-flops and conventional logic circuit. Number of flip-flops required is equal to the number of bits in the binary world. This sequential device loads the data present on its input and then moves or shifts it to its output once every clock cycle. Hence the name shift register. It means that, as I told you, a shift register is a group of flip-flops. So, the binary information, binary bit can be shifted from one flip-flop to another, either from left towards right side or from right towards left side. Types of shift registers, they are classified upon the way in which data are entered and data to be retrieved. And they are serial in, serial out, S-I-S-O, serial in, parallel out, S-I-P-O, parallel in, serial out, P-I-S-O. And last one, parallel into, parallel out, P-I-P-O. Before going to the serial in into serial out, let us take an example. If we shift the data one bit towards left side, the binary number will get multiplied by two. And if we shift the data binary bit towards right side, the number will get divided by two. So, this is what the purpose of shifting the data, either towards left side, one bit left side, or number of bits on towards right side. The first one, serial into, serial out, the data is shifted serial in and out of the register. One bit at a time in either a left or right direction under clock control. To shift four bits, it requires four clock pulses. So, this is the circuit diagram for a four-bit serial in, serial out shift register. If you look at this FFA, where loading the data at the FFA input side called as serial data in. The clock pulse is given simultaneously to all field clock, FFA, FB, FFC and FFD. Output of first field clock is given to the, as an input to the next field clock. So, QA will be act as a DB, then QB is given to DC, then QC is given to DD as an input. So, data is retried at the FFD output QD, this is serial out. For example, if you will want to load the data 0101, here 0101, I must enter this one which is the LSB. This one is the LSB, the first bit information to be loaded while shifting from left to right side is the LSB. So, at the arrival of the clock, first clock pulse 1 will be loaded, so here it will 10000. In the next clock pulse 0 will be loaded, so QB will be 1, QA will be 0 and these two QC, QD will be 0. At the arrival of third clock pulse, this again FFA, QA will be 1, QB 0, QC 1, 0. At the arrival of the fourth clock pulse, QA will be 0, QB will be 1, QC will be 0 and QD will be 1. Hence, at the end of the fourth clock pulse, the information available will be QA 0, QB 1, QC 0, QD 1. It means that for serial in and serial out, it requires four clock pulses. This is a timing diagram, serial into serial out, SISO. First clock pulse, the first bit information is loaded. In the second clock pulse, this one is shifted to the next flip-flop output. This is the second bit information, this one is third and this one is the fourth. So, at the end of the clock pulse, the information available will be 0101. Serial into parallel out. The register is loaded with serial data one bit at a time with the stored data being available at the output in parallel form. The output is taken simultaneously across individual outputs of all flip-flops. So, here is the diagram. Here serial in means when loading the data in the serial form which requires four clock pulses and we are retrieving the data simultaneously, that is QA, QB, QC, QD. These outputs of all these four flip-flops are available at the same instant. But for loading the data in serial form, we must require four clock pulses. This serial into parallel out. So, at the arrival of every clock pulse, this T1, T2, T3, T4, we are loading the data as 1011. This is the serial in input 1011. So, at the arrival of the clock pulse, the data available at the QA, QB, QC, it will be 1011. Parallel into serial out. Here again, the input is the in parallel form. The output is taken in the serial manner. So, it's a really interesting diagram with a multicolor parallel in where loading the data, the shifting and the loading is distributed by this input, shift load. If this signal is zero, this load, it will become one. So, this one is given to AND gates B1, B2, B3. It means that if this signal is zero, B1, B2, B3, these three AND gates are enabled. These three AND gates are having another input as parallel inputs B1, B2, B3. It means that if this signal shift oblique load bar, if this is at zero, we can load the data in the parallel form. Now, look at this circuit. It's a combinational circuit with two AND gates, output of AND gates given to OR gate. So, output of keys were given to combinational circuit. Its output is given as D1 and similar for the remaining two. If it's one, if it's one, if this signal is equals to one, this A1, A1, A2, A3 AND gates are enabled. Due to this, data queues are loaded to D1. Similarly, Q1 is loaded to B2 and Q2 is loaded to B3. In other words, if shift is equal, if this signal shift oblique load bar, if it's one, the data can be shifted from left side towards right side. That is from ff0 to 1, 1, 2, 2, 2, 3. So, this is what the serial out. Parallel into parallel out. Parallel into parallel out. The parallel data is loaded simultaneously into the register and transferred together to their respective outputs by the same clock pulse. So, it's really interesting because the loading is done in parallel manner, whereas retrieving is also done in the parallel manner. Here, these are the parallel inputs Pd, Pc, Pb, Pa. The P stands for parallel in. So, in this manner, we can give the inputs as Pd, Pc, Pb, Pa to 4-bit PIPO triplock. Again, the clock is given simultaneously to all clock pulses. So, at the arrival of the first clock pulse, the data is loaded to ffA, ffB, ffC and ffD. And at the same time, the data is available at output of ffA, ffB, ffC, ffD simultaneously. It means that in parallel into parallel out, we need only one clock pulse to load the data and to retrieve the data. So, the time required for PIPO is very less as compared to other three types. Exercise assignment. What does it mean by parallel loading of a shape register? Options. All flip-flops are preset with data. Each flip-flop is loaded with data one at a time. Parallel shifting of data, none of the mentioned. The answer is all flip-flops are preset with data. Data is loaded simultaneously with the first clock pulse to all flip-flops. So, this is the answer. Ring counter. The most useful application of the shift register is the ring counter. This is basically a shift register shifting from left side towards right side. There is some modification in the basic circuit diagram of the shift register. In this, this Q0 output of the last flip-flop is given as an input to a first flip-flop. That means, Q0 is connected as a D0, D, this flip-flop. Again, the clock pulse connected is given simultaneously. Now, look carefully at the reset signal. This reset signal is given as a reset signal to this one, two and this three last three flip-flops. Whereas, this reset signal, this is not a reset signal to this flip-flop. But it will be a set signal. It means that when this signal is activated, one, two and these three flip-flops will give output as Q2, Q1, Q0 as zero. The only thing is, since this signal is connected as to the set signal, it means that at the arrival of the clock pulse due to setting of this, the Q3 will become one. This means that while giving the signal reset, clock is given, so output will be one, zero, zero, zero. At the arrival of the clock pulse, since this Q3 is one, so Q2 will become one. So, the status will be zero, one, zero, zero. Next clock pulse, it will be Q3, zero, Q2, zero, Q1, one, Q0. At the arrival of the next clock pulse, it will be Q3, zero, Q2, zero, Q1, zero, Q0, one. It means that a ring counter is a type of counter composed of flip-flops connected into a shift resistor. The pulse is injected by entering zero, zero, zero, one in the parallel form. In the earlier circuit diagram, we are using output Q0 given as a D input in the feedback manner, where we can inject the pulse by entering data in the parallel form. So, this is what ring counter, the injected pulse will go on circulating. This one, this will go on shifting towards left side. This is what we explained in the earlier diagram. So, these are the references. Thank you.