 अछ्सला मुलेगं स्ड्युदन्त, अव वसीम क्यम, इस से जी से तिज्टीझत लेक्चचीर, अशीरीज़ क्यम अप दिज्टीट लोगीग छैंग. कईसभी आप ज़ला आच्छी हूँँँँँँँँ. पिशन लेक्च्छर में हम बात के रहते है, 16-bit ALU को इंप्लमेंत करने की. जो प्रब्लम हमारे सामने आया था, जब आप 4-bit के different chips अपस में कोनेख करते हैं, तो केरी-bit है, वो एक 4-bit chip से, तुसे में जाएगा, तुसे से, तुसे से, स्प्रक्षन करने के लिए प्रफाम करने के लिए हमें कोई अलेदा स्प्रक्षन युनेड नहीं जाएगी, वोई जो 4-bit प्रल अडर है, उसी को युस करते हैं, करते क्या हैं, उसका जो A-input है, उसको उसी दरने देतें, जो B-input है, प्रल अडर का, उसके साथ हम एक सरकेट कूनेख करते हैं, अर गेट का, जो B-input को या तो इनवर्ट कर के प्रल अडर के इनपुट पे देते हैं, या उसी तना देर हैं. जो अगर हमने आद करने तो नमबस, तो वो जो सरकेट हैं, जो B-input पे लगाया, तो अपते आझती लिख सरकेट का, result आजाईगा. में में आप आवक चीन भेड अन, इद बेट, त्री वड, सक्झा� form the varying bes in the subject, you can implement the subject. कैसे इसी सरकेट को इसी सरकेट को आप आपस में जोडते जाएं, तो वो वो मः स्विख़ी ती आप तो ज्फाःीं थी बईगा. इसके बात आमने दिशकच्यों श्वोगी ती अर्ठ्माटिक लोगिक युनेत प्रेई. तो बँड़े पट़ा जीत़ जीतन कासगान मीक्रोप़ोलसी�र चैच tane keiat बनत क्रोपौँず करना ज Джैसे ची वोतबोल नकरे के आखः क Global आखन चतर room J decir pala क्रोफेर टॉक सीन पोथी हily medidas on the आच पूईike kar लोग के हैट केरी जन्रेटर के अध्वोट है, जो केरी इस अध्वोट हैं, वो आप कहाँ अताच करेंगे, बैसिक लिए वो हर फोर भित एल्यु की जो केरी एन उसके साथ अताच करेंगे. अध्वोट है, एन लोग के जन्वों के जन्वोट है।愚 BB usar �ㄹ�, �i or �y for Relächlich Rileyよaku skisi gases of each of these ALU�s are 4 betлемy. So, the output of AlU 0 gives bats 0 to 3. Similarly, output of AlU 1 gives-out the results for bats souffle to 7 and similarly for ball shot and value 0 and value 1. Now looking at the carry inputs, the pictures zero is carry out four, similarly the carry in to alu one is carry in for the output carry output from alu one is carry out eight, the carry in to alu two is carry in eight similarly the carry out from alu two is carry out twelve, the carry in to alu three is carry in twelve, from ALU 3 is carry out 16. Now in order to implement a 16 bit ALU the carry output of each ALU is connected to the carry in of the next ALU. So for example the carry out of ALU 0 is connected to the carry in of the ALU 1. Similarly the carry out of the ALU 1 is connected to the carry in of the ALU 2 and finally the carry-out of the ALU-2 is connected to the carry-in of the ALU-3. Now, the carry has to propagate through the ALU-0 through ALU-1, 2 and ultimately it reaches ALU-3. So, the last most significant ALU, the ALU-3 cannot perform an operation unless it has the carry-in 12. The carry-in 12 cannot reach ALU-3 unless the ALU-2 has generated a carry-out 12. Similarly, ALU-1 has to generate a carry-out 8 so that it reaches the carry-in of ALU-2. So therefore, the carry-out 16 from ALU-3 is delayed. This means the result of the arithmetic operation or the logical operation is going to be delayed. If you have a 32-bit ALU, you would be having 8 such gates connected to each other through their carry-outs and carry-ins. So, the last ALU which would be the 8th ALU would give a carry-out after a delay by a factor of 8. Now, to eliminate the carry propagate which propagates from one ALU unit to the next and to the next and to the next, we use the 381. 381 as we said before has two outputs, the group carry outputs. So, ALU-0 has the two outputs P-0 and G-0 the propagate, the carry propagate term and the carry generate term. Similarly, ALU-1 has the two terms P-1 and G-1 the propagate and the generate term similarly ALU-2 and 3 both have the P and G outputs. Now, P and G outputs are equivalent to the carry-4 output seen earlier. So, whenever these two bits are set, this indicates the carry-4 is there. Now, a look ahead carry generator is used. It has 8 inputs having the inputs G-0, G-1, G-2, G-3 and P-0, P-1, P-2 and P-3. So, the carry propagate and carry generate terms generated by each of the 4 ALUs are connected to the input of the look ahead carry generator, which are the carry terms generated by the look ahead carry generated generator on the basis of the generate terms and the propagate terms. Each of these carry outputs are connected to the carry ends of the appropriate ALUs. So, for example, C-1 carry out from the look ahead carry generator is connected to the C in 4 of ALU-1, the C-2 carry 2 output of the look ahead carry generator is connected to the C in 8 of ALU-2 and similarly the carry 3 output of the look ahead carry generator is connected to the C in 12 of the ALU-3. So, now ALU-3, the last arithmetic logic unit receives the carry after a gate delay of 2 instead of the carry having to propagate from ALU-0 through ALU-1 and ALU-2. Now, let us have a look at 16 bit ALU implementation based on 4 381 chips and 182 chip which is the look ahead carry generator chip. Now, looking at the diagram, we have used ALU-0, ALU-1, ALU-2 and ALU-3. So, ALU-0 adds or subtracts or performs arithmetic and logical operations on bits 0 to 3. Similarly, ALU-1 performs arithmetic logical operations on bits 4 to 7 and similarly ALU-2 and ALU-3 perform operations on the most significant 8 bits. The inputs of all these 4 ALUs are connected together shown through the thick lines and labeled A and B. Similarly, the outputs of each of these 4 ALU units are connected together. So, they give an output from bits 0 to 15. The 381 can perform up to 8 different operations. So, any of these 8 different operations are selected by the function select lines S0, S1 and S2. So, the function select lines S0, S1 and S2 of the 4 ALU circuits are connected together. So, let us suppose you need to perform a subtraction. So, all the 4 ALUs have to be configured to perform a subtraction. Similarly, if you need to perform a logical operation, all the 4 ALUs have to be configured to perform the logical operation. Each of the 4 ALUs have the carry generate term and the carry propagate term shown at the output and each output has bubbles. That means the G term and the P term are active low. The look ahead carry generator 74182 has 8 inputs G0, G1, G2, G3, P0, P1, P2, P3. They are all active low. The output is C1, C2 and C3. So, the G and P outputs of each of the ALUs are connected to the G and P inputs of the 182. C1, C2, C3 carry outputs are connected to the carry-ins of the appropriate ALUs. So, the carry 0 is directly connected to the carry-in of the first ALU, ALU 0. It is also connected to the input Cu of 182, the look ahead carry generator. The output C1 is connected to the carry-in of ALU 1. Similarly, carry 2 is connected to the carry-in of ALU 2. And similarly, carry 3 is connected to the carry-in of ALU 3. We have just looked at the implementation of a 16-bit ALU. We used 4 381 integrated circuits. We had connected them together. We have also used a look ahead carry generator to implement the 16-bit ALU. Now, let us have a look at the comparator unit. Comparator unit is another functional device. In the last lecture, if you remember, we had made a comparator circuit boolean expression. We had discussed a 2-bit comparator unit. That means, you have two numbers, two numbers of two bits each. When you compare, the comparator will compare the two numbers and compare the two bits. So, if both the numbers are equal, the output A is equal to B, then it is one, indicating that the two numbers are equal. Similarly, if A is greater than B, larger than B, ,ब लज़ दन बी , कमप्रोछ़का जो अदब्ष्ट है , A greater than b वो वान होजईगा. उसी तना अगर आ जो यो आत्पड़ है अगर a is less than b, खम्प्रेछ़ splashingड का जो अदब्ष्ट है, a less than b वो वान నౌల్న్ల్స్త్ర్స్త్త్లుగతాత్సర్వ్న్ నింిత్ల్మార్యాస్నాలికో�掌ండిఉవసా్మాత్లాలిదికోలా నారిలార్స్ కోవిలుసాలాలు. भी चूर भूबाः और लोँद्सougher a capability of the circuit? भी लिग दूदंमेने में जी और ततींग soft cannot be used आोर लाई लीग फक catalog of wrap एक लगसी वे Negrois bono is यह बवॉठा paraglider क्या तती दासे छागना दो Odys », कि मैं कचा �vs.. आपना बन काो तगा लग साथ द numer जो एक प्वरेट़र हम ने बताए है ते तो अगर हम तो तो थो तो भीध रेट वरेट़ करतेड़ है। धौ वे च्दकष्डम और तो, बर दीड़़्ीचन तो बचिन्च्टन, ने बताद़ कक में चलक यह तो तो तो ठीड़ में ठेदर है, let us discuss, why we need to have that extra logic to attach the two bit comparators. let us suppose you have, two numbers 8 and 9. 8 is in binary, how do we represent it? 1, 0, 0, 0. 9 is in binary, how do we represent it? 1, 0, 0, 1. now, both are 4 bit numbers, now when you compare them, आब अपृत की ंँई, बी, है। तो इसु अद प्रेटर युनेज तो डऱ चो। नहीं थब युनेज तो वद करेगा अद करेगा अदच़े युनेच खेूता साग फात हो। कैसे हमारे बास आगेगी ताला जो युनेच है। तो तो deep, now what i have done is that तो at the two most significant beds मेंनरेँ बट्सद आतोरी था बरता मेंही भी भमन rápता तो at the two most significant beds तो 2 बट्सागा मेंने यह सहये नहीं एक आनता समझे था तो at the finer output of भर थादner is मेंने लिस बट्सागा मेंने नहीं यह सह छ़क्य aerospaceि अखाद उसका a equals to b अपका 1 आजागा Indicating that a input is greater than b इस्तिना अगर अप तो नमबर्स 8 and 7 को खमप्रेर कर हैं 8 is 1 0 0 0 and 7 is 0 1 1 1 एक जो तुबट खमप्रेरतर है वो खमप्रेर करेगा 2 more significant bits So 8 is the 2 more significant bits of 8 is 1 0 And the 2 more significant bits of 7 are 0 and 1 तो पहला जो खमप्रेरतर है, वो खमप्रेर करेगा 1 0 को 0 1 से यो तुब इमीजगत्ली से that 8 is greater than 7 तुश्रे खमप्रेरतर की जो तुबट आनी परडाएस में So there are different possibilities Circuit ultimately क्या होगा? खमप्रेरतर जो पहला वाल खमप्रेरतर है जो 2 more significant bits को खमप्रेर कर है तुश्रा वाला खमप्रेर्रटर है जो लीई सिक्लिप्रेंगन बेट को खमपेर कर है उंके आपफ़ोट से आपपस में ओर गेड कीग खमप्रेर्रेटर से प्रेरडाएस में अब अपने आपनी आपनी जोगेगा जो दूश्रा वाला ग़ेखा पलने hai, पिस लिक्त्रजे�倫 में तीन ऐकट्�jsk्यों सेकक की ड़ािए देी vontade की तीटेclassions derive� The extra labor has three openings derived in the last lecture, आ गट़्र दें लच्द की फिरसब्रठ्त सेकष्समें, आ और ब ligne look at suggestions in different expressions derived, आ गेटर दें पी, बार पक, मिस Himtha learners gets to implement completing the changes with a般. � LineAL Lao, इसको में soft. b 1 a 0 b 0 and of course, the output is set to 1 when a is greater than b similarly the Boolean expression derived for a equals to b output was a 1 bar a 0 bar b 1 bar b 0 bar plus a 1 bar a 0 b 1 bar b 0 plus a 1 a 0 b 1 b 0 plus a 1 a 0 bar b 1 and b 0 bar is key to implementation again a single or gets used for a char and gets used for a and different inverters use for a is key implementation exclusive or exclusive nor gets a b key jasakti a small inputs weight are a 1 a 0 b 1 b 0 output a equals to b is set to 1 when the two numbers are equal finally, the Boolean expression derived for the a less than b output is a 1 bar b 1 plus a 1 bar a 0 bar b 0 plus a 0 bar b 1 b 0 this expression can be implemented using an or gate 3 and gates and 4 inverters the input to the circuit is again a 1 b 1 a 0 b 0 and the output a less than b is set to 1 when a number is less than number b. Now, let us look at the 4 bit comparator circuit implemented using 2 2 bit comparators. So, you have a 2 bit most significant comparator and a 2 bit least significant comparator represented by m and l respectively. The 2 most significant bits of the 4 bit number are compared by the most significant comparator and the least significant 2 bits of the 2 numbers are compared by the least significant 2 bit comparator. Now, let us consider different input combinations input number a is 1 1 0 1 which is 13 and input number b is 7. So, 13 is of course larger than 7. Now, the first comparator the most significant comparator compares bits 1 1 of number a and bits 0 1 of number b it immediately sets its output a greater than b and we have the answer. Let us consider the second case the number a is 0 1 1 0 which is 6 and number b is 1 0 1 1 which is 11 number b is greater than a. Now, the most significant 2 bit comparator compares bits 0 1 of number a and 1 0 of number b. Now, 1 0 is greater than 0 1. So, therefore, the comparator the most significant 2 bit comparator sets its a less than b output to 1 and we have the answer. Let us now consider the third case the number a is 0 0 1 1 and number b is 0 0 1 0 1 1 represents 3 1 0 represents 2. Now, the most significant 2 bit comparator compares 0 0 bits of number a and 0 0 bits of number b. Since both the 2 bits are equal therefore, the output of the most significant 2 bit comparator m is set to 1 for a equals to b output. Now, we do not have the answer the least significant comparator compares bits 1 1 of number a with 1 0 bits of number b. Since, 1 1 is greater than 1 0 therefore, the output a greater than b of comparator 2 the least significant comparator is set to 1. Let us compare let us see the fourth case number a is 0 1 0 0 number b is 0 1 0 1. Now, the most significant comparator compares 0 1 bits of the number a and 0 1 bits of the number b. Since, both are equals therefore, the a equals to b output of the most significant comparator is a 1 the least significant comparator compares bits 0 0 of number a and 0 1 of number b. Now, b is greater than a. So, the output of the least significant comparator a less than b is set to 1. The last case when the 2 numbers are equal. So, number a is 1 0 0 1 number b is again 1 0 0 1. Now, the output a equals to b of the most significant comparator and the output a equals to b of the least significant comparator both are set to 1. Now, let us have a look at the circuit diagram of the 4 bit comparator unit. The outputs of the most significant 2 bit comparator a greater than b is connected to an OR gate a is equal to b is connected to 3 AND gates. So, basically a equals to b output enables the 3 AND gates. Similarly, the output a less than b of the most significant comparator is connected to the input of another OR gate. Looking at the second 2 bit comparator the least significant 2 bit comparator it is a greater than b output is connected to one of the inputs of the AND gate. Similarly, a equals to b output is connected to the other input of the AND gate and a less than b output is connected to the input of the third AND gate. The outputs of the first AND gate and the last AND gate are connected to the inputs of the 2 OR gates representing the output a greater than b and a less than b respectively. The output of the second AND gate represents the output a equals to b. Now, if the most significant 2 bit comparator compares 2 2 bit numbers and finds them to be equal the a equals to b output is set to one which enables the AND gates. We do not have the answer the 2 bit least significant comparator needs to compare the numbers and it is going to set one of its outputs to one assuming the number a is larger than b the output of the least significant 2 bit comparator a greater than b would be set to one all the other 2 outputs would remain at 0. So, the output of the first AND gate would be set to one the output of the a greater than b OR gate would be set to one. Similarly, the outputs of a less than b and a equals to b would be set to one depending on the appropriate numbers. We have looked at the implementation of a 4 bit comparator unit basically 2 2 bit comparator units are connected together some external logic in the form of AND gates and OR gates is required. Now, by using this external logic the size of the circuit is going to increase. So, just imagine if you want to make a 16 bit comparator unit then a lot of external logic will be used. So, it would have been better if this external logic is inside the integrated circuit. The comparator chip if it is available then the connection of 2 2 bit comparators to form a 4 bit comparator would be easier. You do not have to use the external logic, the circuit size will also be small. If you want to use parallel comparators then you have to use external logic. Another way to implement these comparator units is to use iterative circuits. What are iterative circuits? If you remember the single bit full adder basically you implemented a 4 bit parallel adder using 4 of these single bit full adders. What did you do in that? You had only one single bit full adder, 4 of these circuits connected together and made a 4 bit parallel adder. You did not have to use any external logic in that. So, if single bit full adder is an example of an iterative circuit, there were 4 copies of it. Each copy is doing the same thing. The output of one copy is connected to the input of the other circuit. Similarly, the other circuit is an identical copy. The output of the other circuit is connected to the input of the other circuit and so on. So, iterative circuits we can use to implement a comparator. So, in comparator let us talk about A equals to B. How will the iterative circuit of A equals to B be made? An exclusive NOR gate is used to detect if the 2 bits are equal. So, if both bits are 1 1 the output of the exclusive NOR gate would be A1. If both bits are 0 0 the output of the exclusive NOR gate would be again A1. Now, iterative circuit exclusive NOR gate ka kaisa bhanega? Well, we have a combination of an exclusive NOR gate and an AND gate. Exclusive NOR gate ki output jo hai wo connect ho jaagi ek AND gate ke input pe. Dursre jo input hai AND gate ki wo ham permanently set kernenge 1 pe. So, what is the output of the AND gate? It is going to be 1 if the output of the exclusive NOR gate is 1. Agar exclusive NOR gate ki output 0 hai that means both the bits are not equal the output of the AND gate would be a 0. Now, let us consider another circuit. Just may again ye ap ke pas exclusive NOR gate hai connected to the input of another AND gate. Jo pale wale circuit ki output hai from the AND gate. If it is connected to the input of the second AND gate, second jo module bhanega jo iterative circuit bhanega usme. Ab huma hai pas kya hoge? Huma hai pas ek circuit bhanega jo 2 bits ko compare kar rahe hai. Agar chek kar rahe hai ki 2 bits equal hai ke nahi hai. So, jo dursre module hai again it would be comparing the second bit of number A and the second bit of number B. Agar equal hai exclusive NOR gate ka output ki a aega? 1 aaja aega. Palega bhi output 1 tha. So, output of the 2 bit circuit would be a 1. Agar exclusive NOR gate ka output 1 nahi hai that means the second bit of number A and the second bit of number B both are not equal the output of the AND gate would be a 0. So, similarly you can implement an 8 bit, 16 bit, 32 bit comparator unit using these iterative circuits. Isi tana A greater than B jo circuit hai uska bhi ek iterative circuit bhanega aaja aajat tha. So, you would have identical copies they can be connected together. Let us have a look at the circuit diagrams of both these circuits. Let us have a look at the iterative circuit implementation of A equals to B function. Seen in the figure we have module 0 and module 1. These 2 modules represent 2 iterative circuits for the A equals to B function. Module 0 looks at bits A 0 and B 0. If they are equal the output of the exclusive NOR gate is 1. The input of the AND gate is permanently set to 1. The output of the AND gate would be 1 if bits A 0 and B 0 are equal. If they are not equal the output of the AND gate would be a 0. Now looking at the second module module 1 it compares bits A 1 and B 1. Now if the output is A 1 that means bits A 1 and B 1 are equal. If previously bits A 0 and B 0 had been equal the output from module 0 would be A 1. Now what is the output of module 2? In case the numbers are equal the AND gate of module 1 would have both its inputs set to 1. The output would be A 1 indicating that both numbers are equal. Let us suppose that bits A 0 and B 0 are not equal and bits A 1 and B 1 are equal. What is the output of the AND gate in module 0? It would be A 0. What is the output of the AND gate in module 1? It would be 0 because one of the inputs to the AND gate is A 0. Let us consider the case when bits A 0 and B 0 are equal and bits A 1 and B 1 are not equal. So the output of the AND gate in module 0 would be A 1. The output of the exclusive NOR gate in module 1 would be A 0. The output of the AND gate in module 1 would be A 0 because one of its inputs from the exclusive NOR gate is A 0. To form a 4 bit comparator unit similar modules can be connected together. The input in module 0 which is connected to 1 is known as the cascading input. Similarly the input to the AND gate in module 1 is also known as a cascading input. Similarly the outputs from the 2 AND gates in module 0 and 1 are known as the cascading outputs. So in order to form a 4 bit or an 8 bit comparator unit the cascading inputs are connected to the cascading outputs of the appropriate modules or the iterative circuits. The cascading input of the least significant iterative circuit module 0 in this case is connected to 1. The output A equals to B would be obtained from the most significant iterative circuit or module. Let us now look at the iterative circuit implementation of A greater than B function. Seen in the diagram we have a 2 bit implementation of the A greater than B function using the iterative circuits. Looking at module 0 it has an exclusive NOR gate, 2 AND gates, an OR gate and an inverter. Let us suppose A 0 is equal to B 0. The output of the exclusive NOR gate would be A 1. Since the cascading input of the AND gate is permanently set to 0 the output would be A 0. Now the output of the OR gate in module 0 would only be A 1 when A is greater than B. Similarly looking at module 1 the output of the OR gate would be A 1 when A 1 is greater than B 1 or the cascading output from module 0 is A 1. 4 bit, 8 bit or 16 bit comparator units can be formed which generate the output A greater than B by connecting these modules together. So the least significant cascading output is connected to the cascading input of the second module. Similarly the cascading output of the second module is connected to the cascading input of the third module and so on. In this case the cascading input of the least significant module is connected to 0. The cascading output of the most significant module would give the function output A greater than B. To implement A less than B function a similar iterative circuit can be formed and such circuits can be connected together to form a 4 bit, 8 bit or 16 bit A less than B function. We have just looked at the iterative implementation of a comparator circuit. In the iterative implementation basically we designed a single module and copies of that particular module can be used connected together to form an N bit comparator unit. A equals to B can be an example like similarly A less than B key B which can be connected together to form an N bit unit. Now commercially these comparator units are available based on the iterative circuit which we have just discussed. The 7485 is one such unit. It is basically a 4 bit comparator unit. Now in order to form let us say a 12 bit comparator unit you would get 3 of these chips and you would be connecting them together. As we mentioned before these iterative based comparator circuits have cascading inputs and cascading outputs. So cascading output of the least significant unit would be connected to the cascading inputs of the next higher unit. And similarly the cascading outputs of the second unit would be connected to the cascading inputs of the most significant unit. The inputs the cascading inputs of the least significant unit would be permanently connected to 0s or binary 1, 5 volts and 0 volts. The circuit which compares and generates an output for A greater than B and A less than B its cascading inputs are connected to 0 volts. And the circuit which compares A equals to B has its cascading input connected to 5 volts. Let us have a look of the implementation using the 7485. To implement the 12 bit comparator unit 3 4 bit 7485 4 bit comparator chips are used. The least significant 4 bit comparator compares bits 0 to 3, the middle comparator unit compares bits 4 to 7 and the most significant comparator unit compares bits 8 to 11. The appropriate inputs are tied together shown by thick lines. The cascading input of the first comparator unit is connected to 0 volts, 5 volts and 0 volts. The A less than B cascading input is connected to 0, the A greater than B cascading input is also connected to 0 volts. The A equals to B cascading input is connected to 5 volts. The cascading outputs A less than B, A equals to B and A greater than B of the first comparator unit is connected to the cascading inputs, the respective cascading inputs of the second comparator unit. Similarly, the cascading outputs of the second comparator unit is connected to the cascading inputs of the third the most significant 4 bit comparator unit. The outputs, the cascading outputs from the third most significant comparator unit A less than B, A equals to B, A greater than B are set to 1s or 0s depending on the 2 numbers. So, let us suppose A is greater than B, the cascading output A greater than B of comparator unit 3 would be set to 1. Similarly, if the 2 numbers are equal, the cascading output A equals to B of the third comparator unit would be set to 1. We have just looked at the implementation of a 12 bit comparator circuit using B4 bit 7485 iterative based circuits. Connection was straight forward. उस में कोई कोंप्लिकेशन की बातनी जो cascading inputs and cascading outputs आन वो बेसिक्त हैं में लिए। करनें. And as I have mentioned before, you can implement 16 bit, 32 bit, N bit comparator unit बनाशकनें by connecting the chips together. Now, the next important unit which we need to talk about is the decoder unit. Decoder unit commonly used with the digital logic man. Decoder circuit haggya. Basically, a decoder circuit has multiple inputs and multiple outputs. Now, if you apply a multi bit code at the input of the decoder, it is going to select one or more than one of its outputs to indicate the presence of that code. So, you have a circuit multiple inputs, multiple outputs, यक code of apply करेंगे आनप्लिकेशन की अबआजासे आपभ़ट्पे यहीग बिट आपभट अपट्ट आपट्टट होँगागया यहा मल्टिपल आपटटट होगागया. Let us consider an example. Let us suppose you design a digital lock. ॐ ॐ ौ ौ ौ Because you have toalign a circuit which accepts number 11 and sets the output to 1. One indicates that this door has been locked.. Similarly, you need to unlock the door of a circuit which accepts the combination of 1001 and it sets a output to 1.. which indicates that the lock has been unlocked. Now how do we implement the door lock circuit ? अप दो practices is a अप थो दो तो तो तो तो मैं औगडा- ठीरा तो आब दागे दीखा। तो तो थो re ke do re दीखा। आप दिया। यह पने लिए आप दोट करे ओन्ब हो दा चीं क्जाने आप वे off अगाड़्ार का बराव्रावी कूनेग वेदी और जो क्यो Chart and Gate one directly connect कोनैख तो इंगे थो दो बेटका लगाडिय कोनेख हो तुभ में रया l को आप दिन अप दरकटी कोनेख कर थेंगे आद्� light duct in port span. आद़्ीट की और ठॉगाडिय प्रिच्रे के खदूए. , let us have look at the circuit which unlocks the door , the combination is 1001 number 9 , again you would use another AND gate, four input AND gate , one jo hair directly connected ho gaya . Uske ba though jo zeros are a they are connected to the inputs of the AND gate through two inverters and finally the last bit one it is directly connected to the input of the AND gate . So, the output of the AND gate would अपने चार इंपुट कोमनेशन अपलाए की किसी दो कोमनेशन पे सरकेट अपलट वन होंगे 11 पे लोग करेगा 9 पे अनलोग करेगा कोई आर कोमनेशन देंगे the circuit would not work now the most common decoder which we use is a 2 to 4 decoder circuit its 2 inputs and 4 outputs now how does a 2 to 4 decoder work basically 2 inputs then what combinations can be 0, 0, 0, 1, 1, 0 and 1, 1 on output we have 4 outputs as we have said before so if 0, 0 is selected one of those 4 outputs will be activated when 0, 1 input combination will be applied the second output will be activated the other 3 outputs will be inactive similarly 1, 0 combination will be applied and after that 1, 1 will be applied so the appropriate outputs will be activated let us have a look at the implementation of this 2 to 4 decoder circuit let us have a look at the function diagram which represents the function of this 2 to 4 decoder let us first have a look at the electronic door lock the circuit shows 2, 4 input AND gates and 3 inverters the electronic door lock is within the box the inputs to the electronic door lock are A, B, C and D the outputs are of course 2 lock and unlock now when the combination 1, 0, 1, 1 is applied at the input the lock output is set to 1 and when a combination 1, 0, 0, 1 is applied the unlock output is set to 1 for all other combinations the lock output and the unlock output remains at 0 now let us look at the implementation of a 2 to 4 binary decoder before we look at the circuit diagram let us look at the function table of the 2 to 4 binary decoder the 2 to 4 binary decoder has 2 inputs and 4 outputs the 2 inputs are represented by I, 0 and I, 1 and the 4 outputs are represented by O, 0 the output 0, O, 1, O, 2 and O, 3 now for the input combinations 0, 0, output 0 should be active similarly for input combinations 0, 1, the output 1 should be active all other outputs should remain at 0 similarly for input combination 1, 0 the output 2 should be active other outputs should remain inactive and finally for the input combination 1, 1 the output 3 should be 1 the remaining output should be 0 now this function can be implemented through a set of 4 AND gates and 2 inverters so as seen in the diagram the 2 inverter outputs are connected to the inputs of the first AND gate O, 0 now when input 0 and input 1 are both set to 0 the outputs of the inverters are 1s and the output of the first AND gate O, 0 is a 1 similarly looking at the last AND gate the non-inverted inputs are connected to the inputs of the AND gate so when both inputs are 1s the output of the last AND gate is 1 similarly for the second AND third AND gate a combination of inverted and non-inverted inputs are applied we have looked at the implementation of a sample 2 to 4 decoder there are different types of decoders available in different configurations 2 to 4 decoder have 3 to 8 have 4 to 16 have dual 2 to 4 decoders and different combinations can be attached and connect to form larger decoders we had read in the beginning BCD to 7th segment decoder that is also a decoder it is different from this particular 2 to 4 decoder in BCD to 7th segment decoder you apply a certain code a BCD code its multiple outputs are activated depending on the appropriate segments we will see that later similarly you have BCD to decimal decoder that means you apply a BCD number how many outputs are there 10 outputs because it is a BCD to decimal so output 10 must be 0 to 9 so each output would represent 1 decimal number from 0 to 9 now where do we use these decoders basically in digital systems there are 2 types of applications where decoders are used one application is selection of different devices in any computer or any digital system you have different devices so which different devices they are selected one after the other so how to select basically every device has an address so let's say a device A let's say modem you have kept its address 0 1 1 0 another device is hard disk you have kept its address 0 1 1 1 so if you have to select modem then what will you apply to the code 0 1 1 0 which is its address similarly if you have to select the hard disk you will apply its code where will you apply this code you would have a similar decoder circuit decoder's inputs will apply this code its appropriate output will be activated decoder's output will be attached to input pins of these devices which will select these devices this is the same example which we studied door lock and unlock if you expand it let's say you have 4 inputs so how many input combinations you can apply 16 input combinations similarly if you expand that circuit you will have 16 outputs so that means you have 16 rather 8 doors which you can lock and unlock 0 0 1 0 0 0 1 would open that same door similarly 2 will lock 3 combination will open that same door here you can control the light switches on or off or you can control any device so decoders can be used to select devices and in fact in computer system this is what you are doing second application instructions when you write a program when you compile it all the code changes in machine code in binary code this code when you run program in computer so your computer fetches one instruction looks at the binary pattern so what is binary pattern basically with every instruction there will be a unique binary pattern which will tell you what is this instruction adding, logical operation performing there is a command that you have to save something in memory how computer will know what operation to do basically the binary code will apply to a decoder input one output of decoder will be activated that output will be connected with appropriate device so let's say 0 0 0 1 the add operation appropriate output will be activated it will be attached with an adder unit so it will tell the adder unit to add similarly the instruction 1 0 0 0 could mean save a variable in the memory so when you apply this 1 0 0 0 code at the input of a decoder the appropriate output would be selected the appropriate output will be connected with memory chip memory will be informed that you have to save a particular variable let us now look at some commercially available decoders we have a 2 to 4 decoder and 2 of these decoders are available in a chip so let us have a look at the function diagram of this decoder and the circuit the 2 to 4 decoder is slightly different from the circuit which we have just seen the input is incorporated so whenever you use decoder you would first enable the chip when you don't use it you would disable the chip so let us have a look let us have a look at 7 4 1 3 9 dual 2 to 4 decoder that means in this chip you have 2 to 4 decoders the function table of this 2 to 4 decoder is a and another input which is the chip enable input g it is active low the outputs of this 2 to 4 decoder are y0 y1, y2 and y3 they are all active low now in order to use this decoder the enable pin has to be activated so since it is active low it has to be connected to logic 0 to activate the chip so as seen in the function table the first row g input is 1 therefore the output of all the 4 pins remains a 1 no matter what the input is if the enable pin is set to 0 as seen in the second row if you apply an input 00 the y0 output is selected since it is active low therefore you see a 0 there the remaining outputs are set to 1 or remain at 1 similarly when g input is 0 the chip is activated the inputs are 0 1 y1 output is selected it is seen to be 0 remaining outputs are set to 1 for input 10 the output y2 is selected for the input 11 the output y3 is selected looking at the circuit diagram of the 7 4 1 3 9 you have 4 9 gates with bubbles at the outputs 9 gates have been used because the outputs are active low similarly instead of using 2 inverters you see 5 inverters 1 inverter is used for the enable pin it is active low so inverter converts the active low input to active high and connects it or enables the 4 9 gates the inputs p and a are connected through 2 inverters the reason for connecting 2 extra inverters is to reduce the load seen by the input let us suppose the 2 extra inverters are not available at the inputs b and a so if this particular decoder circuit is connected to the output of another logic circuit how many unit loads would it see basically it would see an inverter and 2 9 gates so 3 unit loads are seen so if you remember the fan out term any circuit can be connected to a fixed number of gates so in this particular case if the 2 not gates are missing the fan out assuming the fan out to be 10 the fan out of the circuit would reduce to 7 by connecting the extra inverter the unit load has been reduced from 3 to 1 we have just looked at the implementation of a dual 2 to 4 decoder as I have said so there are different types of decoders which can be implemented in the next lecture until the next lecture khuda hafiz