 क्या villages अजमान लिकतिद अज्जितः के अज्जितः के लिकतिद जातिद तो, ञ्यातिद शे willenत कप्यوں कर opioid rule url воग以上 four full adder contribution will occur, that means after a delay. If you have a 16-bit parallel adder, you have a 32-bit parallel adder etc., the carry that went from the first full adder, will occur from 32 full adders, or from 16 full adders etc. That means much more delay will occur. तो अगर अपके अपके पास कमपुटूँस में, 16-bit parallel adder हैं तरी-तू-बट बट पलल अदर है तो उज़ करी आच आच है, बहुज जाज दिले होगजागा, you cannot afford that much delay इसका हल क्या ता, इसका हल क्या था, you have to somehow look at the inputs तो आप के अपके आपके पास के रेए आप कें पास परल अदर है, you have 4 bit parallel adder तो आप ने एक अपने लिए एक नहुझ याईईच फ्फ़ागा अप औगर नगी के लिए, you will look at those values देखनेंगे अगाट्र हैगे थे लेगते हैंगे और, देखनेगे बात एक सरकत शे आप, खाडिस जनवेट खेट गर एगे सद्वेट खराईगे. लिक में फ्रिएद गरिट खेट खरिट गरिट ठाग। अमने बेसिक्टली जो करी की बूलीन अक्ष्पैशन्स लिगी ती वो अमने एं तम्स अफ दी करी प्रोपगेट तम और करी जंवरेट तम्स उस तम्स में लिखी ती अं दिन वी सेट दी करी वान, करी तु, करी तु, करी तु, and करी तु, all these carry bits are generated after a delay of 2. उस्तना आपने वो जो करी प्रोपगेट की बजास से दिले हो रहा, वो अपने रिमूग कर लिए, by adding another circuit, which is known as a look ahead carry generator. अपस में कैसे कुनेख करेंगे वो में देखा था, basically the carry-out will be connected to carry-in. तुस्रे वाले का जो करी आपने अगले के करी इंपे होगा. So in this manner you can connect up to n number of 4-bit MSI adder chips. कुनेख ती जिफ्रन आपने आपने आपने लाज़र आदर, basically it is called cascading. So cascading of adders. आज हम दिसकर्शन शुप करतें, बलके कुन्तिनु करतें, with BCD adders. बीसी दी हमने बात कीती शुमें, basically it is numbers 0-9, the digits of decimal are 0-9. बीसी दी 4-bit तो नमबर है, वो नहीं को रपज़न कर है, 0-9 तक. बीसी दी की काफी सारी अप्लिकेशने है, contours are used. यह आपने क्यलक काँचने तिजिटरल कलाच की भात की थी digital numbers are displayed. तो, वीस यह वो उदो सारे bcd is numbers add or are used. बीसी दी अडर जो लुगते है, which basically add these bcd numbers. अगर, आपको याद हो बीशेदे अदिशन मिहने बात ke iss me shru mein agar aapko yad ho bhiin bhiin अदिशन मिहने बात कीटी किटी। kiute hum want keehti keehti इंके वालेग नंबर हैं। k怨हें भीष मैंगें और आपको याद हो। kiya rahein aaapko yad hó वालेग नंबर हैं। abisme tiya humair épaz jo valid karhaing तो से लेगे 9 तग हैं। तो लेख से 9 प्लस वान अगर अगर अप 10 करते हैं तो बाइनेरी में वो आजागागा 1 0 1 0 1 0 1 0 जो है वो एक एन वलेट बीसेटी नमबर है तो क्या करना दा हमें अगर आपको गाद हो अगें अप यू आद 2 बीसेटी नमबर अप यू ये आप आँँसर वो आईद 10, 11, 12, 13, 14, 15। आए यो ये आभ ढ़ाज्ती न कौए नको लेज़़ी है यो येव आप बीसेटी नमबर है टो अस में है येव, येव मैन दाज़ी वो लेग्या करना है . सो Wenn लफ्स Kingdom oflinear of Calculus Tool आन के लफ्स तो भी लफ्स नापी啦िए ने कराज यहा लफ्स Those are three values of the problem of the problem of our development dreams, उसरीः फाया बच्तू mom, उसरीख हो तिश कराज ते दचसबताने ये छ warming � Nope room right now the reality of corrugation is that अपी तुःको़ मदूना अनने नननाorder को Money is suned when it's a scenario is turned at a ये सबारे बमाशगन्या था बता रहीग के बारेता हैं। जी जेगगगगगगगblockbankbank... तो का अचात जबआट्र अजन्टडिखागसाज। ये खृईया आजन्टिखगगगगगगगगगगगगगगगगगगगगगग изुश। पहला जो फोरभेट आदर है, यो भी आदें दी तो बीची दी नमबस जो रेजाल्त आजाएगा उसको अपने चेक करना है, क्या वो जो बीची दी रेजाल्त है, वो वलेट है, या नहीं है, यो असो नहीं चेक ती करी आउत फुम दी फूरभेट आदर. आद्स दी थी बीची दी नमबबस जो दो फोरभेट आदर है, उसको वह वो दी दी आदर है, तो फूरभी आदर है जो भी परद करना आदर और जो अपने भी दी आदर है. There is a carry-out from the first 4-bit adder. Now there is an invalid BCD detector circuit. As we had said before, if you add two BCD numbers, the result could be an invalid BCD number that is numbers ranging from 10 to 15. So the output is connected to the invalid BCD detector circuit. Similarly, the carry-out from the first 4-bit adder is also connected to the invalid BCD detector circuit. Now if the invalid BCD detector circuit detects an invalid BCD number or the carry-out, it adds a 6 to the original result. Now the 6 is added to the original result using the second 4-bit adder as shown in the diagram. The carry-in of the second 4-bit adder is connected to zero. The carry-out is not used. The output is available at the S output. Now let us have a look at how we implement the invalid BCD number detector. Now the possible output sum terms are 16 starting from 0, 0, 0, 0 up to 1, 1, 1, 1. Now as we have said before, the terms 0, 0, 0, 0, 2, 1, 0, 0, 1 that is 0 to 9. These are valid BCD numbers. Binary numbers or BCD numbers 1, 0, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0 and 1, 1, 1, 1 are considered to be invalid BCD numbers. So the invalid BCD number detector should be detecting these 6 combinations of BCD numbers. In the function table, these invalid combinations are marked as 1. Now to implement a circuit, the function table is mapped to a 4-variable Karnoff map. The 2 terms are the product of S2 and S3 plus the product of S1 and S3. The terms S0, S1, S2 and S3 represent the 4-bit BCD output. The expression can also be represented as S1 plus S2 into S3. The implementation of this is done using an OR gate and an AND gate. The expression only detects an invalid BCD number. The second error condition is when a carry-out occurs. So the complete invalid BCD detector circuit has another OR gate. So it ORs this previous expression with the carry-out from the 4-bit adder. Now let us see how this invalid BCD detector circuit is connected to the second 4-bit adder and how it allows the second 4-bit adder to add the number 6 to the invalid BCD output. As seen from the diagram, the inputs to the invalid BCD detector circuit are literals S1, S2, S3 and C out 1. The invalid BCD detector circuit generates a 1 at its output when it detects either of the 2 error conditions. The input B of the second 4-bit adder has its bits 0 and bit 3 permanently connected to 0. Whereas bit 1 and 2 of input B is connected directly to the output of the invalid BCD detector. So if the BCD detector circuit detects an error condition, the output would be 1, the B input would be set to 0, 1, 1, 0. If an invalid condition is not detected, the B input would be set to 0, 0, 0, 0. Now since the second 4-bit adder has one of its inputs, the input A connected to the output of the first 4-bit adder. So it has the output result of the first 4-bit adder. So if an error has occurred, the second 4-bit adder would add a 6 to the original result. If an error has not occurred, the original result would be added to the value 0. We have looked at the example of a single BCD adder. Basically, 2 4-bit parallel adders are used. The first 4-bit parallel adder is adding 2 BCD numbers. The result is to be checked whether it is valid or not, whether it has been carried out or not. The invalid condition detects a circuit, the output is used to add a 6 or a 0 using the second 4-bit parallel adder. So you have 2 4-bit parallel adders. Let us talk about implementing a 2-digit BCD adder. So 2-digit BCD adder, how many 4-bit parallel adders are used? Basically, for 1 digit, 2 4-bit parallel adders are being used. So 2 BCD digit adder, 4 BCD adders will be used. How will the connection be? Basically, the same way, an extra copy is being added to it. Similarly, 2 set of 4-bit parallel adders are being added to the 2-digit. After that, there will be 2 error detector circuits which will check their outputs. If both the outputs are invalid, then basically you would be adding 6 to both set of BCD digits. How will they be added? You would have another set of 4-bit parallel adders. How are they connected? Basically, the least significant digit is the output of the error detector circuit. Where is it connected? Basically, the most significant digit is the carry-in. After this, we will have a look at the 2-digit BCD adder circuit diagram. And then we would be adding 2 numbers. The first example is, you add 2 BCD numbers 99 with another number 99. Results should be 198. By the way, first, the least significant digit is 9. The second least significant digit is 9. If you add both, what do you have? 18. If you see in the binary, it is 1 0 0 1 0. 1 is basically 2. 2 is a valid BCD digit. So, what does the least significant BCD circuit do? The invalid BCD detector circuit has detected the carry. So, it would generate an output of 1. So, you have to add 6 to the result 2. When you add 6 to the result 2, you will get 8. So, first, you have 8 in the digit. The most significant digit is the carry-in. It is the carry-out of the first circuit. Basically, the invalid detector has connected the output. So, basically, the second BCD adder is the number 9, 9 and 1. The result is 9 and 9 is 18. And 1 is 19. 19 is 1 0 0 1 1. So, the most significant 1 is the carry-out. And the 4 least significant bits are 0 0 1 1. Again, the error condition has occurred because the carry-out has been detected. So, what does the second or the most significant BCD adder do? It adds a 6. So, when 6 is added, 0 0 1 1, 0 1 1 0 is added, you get 9. So, the ultimate result is 1 9 8, which is the correct result. Similarly, we will see another example. We add 66 in 99. So, if we consider the first digit, 9 plus 6 is 15. How will we represent 15 in the binary? 11 11 1. Now, this particular combination of bits is an invalid BCD digit. Circuit, it would detect an error condition. So, it would generate an output of 1. Now, what do we have to do? We have to add 6 in this. So, if you add 6 to 11 11, what do you get? Well, you would get a valid number 5. Similarly, in the second digit, when you add 9 and a 6 and a carry, you would get another number which would be a valid BCD number which would be 6 or a carry out. Let us have a look at the implementation of a 2 digit BCD adder circuit. And let us have a look at these 2 examples. The 2 digit BCD adder is divided into 2 parts. The least significant digit adder and the most significant digit adder. Now, these 2 parts are identical to the single digit adder discussed earlier. The invalid BCD detector circuit output of the least significant digit adder is connected to the carry-in of the first most significant digit 4-bit adder. Similarly, the invalid BCD detector circuit output of the most significant digit adder is seen as the most significant digit, the third digit. The carry-out 4 and the carry-out 8 of the second least significant digit and the second most significant digit 4-bit adders are not accounted for. They are basically not used. The carry-in to the second least significant 4-bit adder is connected to 0. Similarly, the carry-in to the second most significant 4-bit adder is also connected to 0. So, when 2 BCD least significant digits are added, if an invalid condition is detected, the output of the invalid BCD detector circuit is a 1. The first most significant digit 4-bit adder adds the 2 most significant digits and the carry. The invalid BCD detector circuit checks the output and the carry-out from the first most significant digit 4-bit adder. If there is an error, it also generates a 1 which is available at the carry-out. Let us consider the first example, the addition of BCD number 99 to another BCD number 99. Let us first consider the least significant adder circuit. The first least significant adder circuit adds the 2 least significant digits 1 0 0 1 1 0 0 1 both representing the numbers 9. The carry-in to the first least significant digit adder is a 0. The sum output is 0 0 1 0 and a carry is generated. The invalid BCD detector circuit detects an error and its output is set to 1. Now, this output is connected to the carry-in of the first most significant digit adder. The first most significant digit adder now adds the 2 most significant digits 1 0 0 1 and 1 0 0 1 both numbers representing the number 9 and the carry-in which is a 1. The sum output of the first most significant digit adder is 0 0 1 1 and the carry-out is also a 1. The invalid BCD detector circuit for the first most significant digit adder generates a 1. Now, looking at the second least significant digit adder, it adds the number 6 to the original result. The original result is connected to the input A so it is 0 0 1 0 input B is set to 0 1 1 0 the carry-in is 0. The output is 1 0 0 0 which represents the digit 8. Looking at the second least significant digit adder, the output of the first most significant digit adder is connected to the A input which is 0 0 1 1. The B input is set to 0 1 1 0 because of the error condition Cn is 0. The sum output is 1 0 0 1 which represents the BCD number 9 and the carry-out is 1. So, the BCD number is 1 9 8. Let us consider the second example the BCD number 99 is added to the second BCD number 66. Consider the first least significant digit adder A input is connected to 1 0 0 1 the number 9 and B input is connected to 0 1 1 0 the number 6. Carry-in is set to 0. The sum output is 1 1 1 1 representing binary 15 which is an invalid BCD number. The carry-out is 0. The invalid BCD detector circuit output is 1 indicating an error condition. This output is connected to the carry-in of the first most significant digit adder. The first most significant digit adder adds the number 9 at input A which is 1 0 0 1, the number 6 0 1 1 0 which is connected to input B and the carry-in 1. The sum output is 0 0 0 0 and the carry-out is generated. Again, since a carry-out has been generated the invalid BCD detector circuit for the most significant digit sets its output to 1 which is the carry-out to the most significant digit or the third digit. Now, looking at the second least significant digit adder, it has to add the number 6 to the output result of the first least significant digit adder. The output of the first least significant digit adder is connected at the A input which is 1 1 1 1, 6 is added which is at input B 0 1 1 0, carry-in is 0, the sum result is 0 1 0 1 which is BCD 5. Looking at the second LSD adder, the least significant digit adder, the output of the first most significant adder is connected directly to the A input which is 0 0 0 0. The input B is set to 6 because of the error condition, carry-in is 0, the sum output is 0 1 1 0. So, the number is 1 6 5 which is the valid BCD sum output of numbers 99 added with number 66. We have just looked at the implementation of a 2 digit BCD adder. You can implement 4 digit, 8 digit, 6 digit BCD adders using same circuits and using the same connections. We have also looked at 2 examples basically addition of BCD 99 to another BCD number 99 and the addition of BCD number 99 to another BCD number 66. Let us have a look at subtraction. How do we perform subtraction? If you remember, we talked about subtraction in the form of 2s complement. Basically you do not need another subtraction unit or a subtractor unit. If you have a number such as 5 which you need to subtract from 9. So what do you do? Basically you take 2s complement of 5 and the 2s complement of 5 when added to 9 would give you the result 4. So you do not need to worry about the negative sign, you do not need to have a separate circuit. How do you get 2s complement of 5? Basically you take 1s complement of 5 and after that you add 1. That gives you the 2s complement. How do you get 1s complement of 5? Basically if you invert all the bits, that gives you the 1s complement of any number. So 5 is basically 0, 1, 0, 1. This 1s complement will be 1, 0, 1, 0. Now if you remember, when we were talking about a parallel adder. In the parallel adder you have 2 inputs. Input A, input B. So let us suppose you connect 9 on input A or 1, 0, 0, 1. Which represents the number 9 at input A. Input B is 1s complement of 5 which is 1, 0, 1, 0. C in, carry in is 4 bit parallel adder. You set that on 1. Now what will the 4 bit parallel adder add? It would add the input A. It would add the 1s complement at input B and the carry in. So basically 3 numbers are added. What is the result? Basically the input B, carry in is basically 2s complement. 2s complement when A is added. Basically you are performing a subtraction. The result would be 4, 0, 1, 0, 0. Now how would we implement a subtractor unit? Well if you have an adder, we have been talking about a 4 bit parallel adder. Its B input, you have to change something. What you have to change? Basically if you are subtracting, on B input, the number which you subtract, its 1s complement should come. So how would you implement a 1s complement of a number? Basically you have to use your not gates. You will remember, if you want to take any number, you have to take its 1s complement. So you put inverters. There are 4 bit numbers. So 4 bit and 4 not gates will come. It will invert. So at the B input of a 4 bit parallel adder, you would have 4 not gates. So whatever you will apply to the not gates input, it will invert and come to B input. Carry in you have to set 1. So basically you would be performing a subtraction. Let us have a look at the subtractor unit, how it works and how it is implemented using an adder circuit. Let us first have a look at a 4 bit subtraction circuit. Basically it is a 4 bit parallel adder. It has 2 inputs, input A and input B and some output. It has a single bit carry in and a single bit carry out. Now let us suppose you have to subtract 5 from the number 9. Well 9 1001 is applied at the input A and the number 5, it is 1's complement which is 1010 is applied at input B. CN is set to 1. So a 4 bit parallel adder would add the contents at input A, the contents at input B and the carry in. So B added with carry in which is 1 would generate 2's complement which added to input A would give the subtraction result which would be 4, 0100. Let us implement a 4 bit adder and subtractor unit. Basically a 4 bit parallel adder is used, A input is unchanged, input B is connected through a set of AND gates and OR gates. The AND gates marked with U mean uncomplimented input. As can be seen in the circuit diagram, the inputs B0, B1, B2 and B3 are connected through the uncomplimented AND gates to the OR gate. Similarly you have another set of AND gates marked with C. The C means complemented gates. So basically the input B0, B1, B2, B3 is complemented through the inverters and pass through these complemented AND gates to the OR gates. Now the uncomplimented or the complemented AND gates are controlled through the signal at the right where add is equal to 0 and subtract is equal to 1. When the signal at the right is set to 0, the circuit would be performing an add operation because the uncomplimented B inputs would be connected to the B input of the 4-bit parallel adder. Similarly if subtract is set to 1, the complemented inputs B0, B1, B2, B3 would be passed on through the AND gates, through the OR gates to the 4-bit parallel adder and a subtract operation would take place. When the subtract input is set to 1, the carry-in is also set to 1. So which adds to the complemented inputs B to form a 2's complement which is added to the A input. We have just looked at the implementation of a 4-bit subtractor unit. Basically we have that 4-bit parallel adder whose B input we have attached to an AND gate or OR gate circuit. Basically what is this circuit doing? It allows either the complemented version of B input to pass to the adder or the uncomplimented version of B to be passed to the full adder or rather the parallel adder. A pin on the right basically allows subtraction to be performed or addition to be performed. So if you add the pin to 0, subtract it to 1. That pin is also connected to Cn. So when you subtract it to Cn1, when you add it to Cn0, the right pin we have seen is called function select. Basically there is only one circuit that is addition and subtraction. So how will it do? We will select function select to add or subtract. Now let us have a look at implementing an 8-bit subtractor unit. How will an 8-bit subtractor unit basically cascade 2-4-bit units? The circuit diagram will be very simple. The 4-bit subtractor unit will be connected to the adder's C out to the carry-in of the next subtractor unit. The 4-bit parallel adder will be connected to the carry-in of the next subtractor unit. The B input and ORC circuit which is uncomplimented will also be in the second circuit. The function select pin will control both of them together. So if you want to add both the circuits they will be adding. If you want to subtract from the function select pin they will be configured for subtraction. So let us have a look at the implementation of an 8-bit subtractor unit. But before we have a look at that we would be looking at two examples. Two numbers and subtracting two numbers. So we will see in the circuit implementation or addition and subtraction examples. Let us have a look at the implementation of an 8-bit adder subtractor circuit. Basically two copies of 4-bit adder subtractor circuits are used. The output from the first 4-bit parallel adder the carry-out is connected to the carry-in of the second 4-bit parallel adder. The inputs A of the first 4-bit parallel adder and the second 4-bit parallel adder are directly applied. The inputs B of the first 4-bit parallel adder and the second 4-bit parallel adder are applied through the AND or circuitry which allows the complemented or the uncomplimented version of inputs B to be applied to the two 4-bit parallel adders. The function select pin at the right controls both the circuit simultaneously. If the subtract operation is selected the carry-in connected to the first 4-bit parallel adder is set to 1. If the add operation is selected the carry-in pin is set to 0. Now let us consider two examples. The first example is addition of number A 103 and number B which is 67. So let us consider the first least significant adder. The input A is set to 0 1 1 1 and input B is set to 0 0 1 1 The most significant adder the second most significant adder has its A input set to 0 1 1 0 and the input B set to 0 1 0 0 Basically the inputs A 0 1 1 0 0 1 1 1 represents the number 103. Similarly the input B 0 1 0 0 0 0 1 1 represents the number 67. The least significant 4-bits are added by the first adder and the most significant 4-bits are added by the second adder. The carry-in to the least significant adder is set to 0. So the sum output is 0 1 0 No carry-out is generated so the carry-in to the second most significant adder is 0 The sum output is 1 0 1 0 The second most significant adder does not generate a carry so the carry-out is 0 So the answer is 1 0 1 0 1 0 which is equal to 170 decimal. Let us consider the second example where the number 67 is subtracted the number 103 Now the number 67 has to be presented in its 1's complement form So the number A applied at both the adder inputs is 0 1 1 0 0 1 1 1 The number B which is 67 in its 1's complement form is 1 0 1 1 applied at the B input of the second most significant adder and 1 1 0 0 at the B input of the least significant adder The carry-in to the least significant adder or the first least significant adder is set to 1 The sum output is 0 1 0 0 Similarly the carry-in to the second most significant adder is set to 1 The sum output is 0 0 1 0 A carry-out is generated which is a 1 The answer is 0 0 1 0 0 0 1 0 0 The most significant carry is neglected We have looked at the 8-bit implementation of a subtractive unit Just now 4-bit we can make it 8-bit, 12-bit, 16-bit The connections are very simple The carry-out from the 4-bit full adder is connected to the carry-in of the next 4-bit adder and so on The pin will remain the same and it will control all the circuits So if the 16-bit subtractive unit is there then the complemented or uncomplimented form will come We have also looked at 2 examples where we have added 2 numbers subtracted 2 numbers we saw that the circuit functions correctly Let us talk about the arithmetic logic unit What is an arithmetic logic unit Every computer has a microprocessor Basically microprocessor is the most important part In the microprocessor there is an arithmetic logic unit which is a very important part of the microprocessor The arithmetic logic unit all the arithmetic operations multiply, divide, add, subtract all these do All the logical operations add or exclusive or exclusive nor all the logical operations So the arithmetic logic unit basically performs arithmetic operations and logical operations Today we have seen basically examples of BCD adder In the last lecture we have seen simple addition subtraction So all these arithmetic operations are basically ALU Logical operations are also ALU So basically how to implement Basically we will not implement Generally we will talk about that How to do the work ALU is basically commercially available in the form of different integrated circuits There are 181 available 381 available 382 available These are 4 bit arithmetic logic different arithmetic and logical operations 181 is 32 different operations How to do 32 different operations Basically you will select a operation from function select pins Let's say you want to do subtract operation So function select pins will be 181 You will give a 5 bit code So you will do subtract operation If you want to do add operation Again you will apply a special code 5 function select pins If you want to do logical operation Again function select pins You will apply a unique code You will do logical operation 181 is basically 8 inputs It is a 4 bit ALU So A input B input are both 4 bit The output logical result arithmetic result is also 4 bit Apart from this we talked about different functions So to select it To select every function You will need 5 function select pins So it is a complicated complex circuit The other 4 bit ALU 381 382 both are similar 381 is basically 8 different arithmetic and logical functions can be performed There are 2 4 bit inputs Because 8 functions can be performed Therefore function select pins How many should be Basically 3 should be So 0 0 0 One function will be performed If we apply 0 0 1 Then another function will be performed Similarly 1 1 1 Then another function will be performed So by selecting 8 different codes At the function select pins You can perform 8 different operations We will see in detail which functions can be performed The second thing 4 bit ALU will simply add 4 bit subtract 4 bit operation which is not useful Your microprocessor or computer can do 16 bit operations 32 bit operations 64 bit operations Basically if you have 32 bit arithmetic operations Basically there are 2 numbers 32 bit You have to add or subtract So you have to have 32 bit arithmetic logic unit How you will make 32 bit If you have a 4 bit arithmetic logic unit So if you connect 8 units cascade 32 bit arithmetic logic unit What are the issues What are the issues Basically the same Cary is the issue If you remember the addition We talked about 4 bit parallel adder We talked about the carry It starts with the first full adder It starts with the second It starts with the third and fourth It starts with the propagation delay You will get it on C out What was the solution We said look ahead carry We will attach it It looks at the inputs It decides on the basis Will carry generate Similarly if you look at ALU ALU also has the same arithmetic unit Subtract unit It will also generate carries So let's suppose you are implementing 16 bit arithmetic logic unit So how you will do You will connect 4 chips of 381 4 chips of 381 Now the carry out Of the first 381 Would be connected to the carry in Of the second 381 And the carry out of the second 381 Would be connected to the carry in Of the third 381 and so on Her 4 bit ALU Carry out A carry bit memory Which is going on So that means Her 4 bit ALU Will give you some delay For the next one So if you have made 16 bit ALU The last carry out After 4 delays You will get it So if you are going to be implementing 32 bit ALU That will be a lot of delay What is the solution In the last lecture We implemented a look ahead carry generator Look ahead carry generator We carried 1 Carry 2 Carry 3 and carry 4 We wrote in terms of The carry propagate And the carry generate Basically if we look at c1 c1 was based on The Generate the carry generate term G0 Plus the propagate term P0 into c0 So G0 was If A0 and B0 are both 1 Then carry 1 Will be 1 P0 was A0 Exclusive or B0 The second term P0 into c0 That means P0 is 1 And C0 is 1 So carry 1 Is always necessary to be 1 Similarly we wrote the term C2 P0 G1 Plus P1 into c1 Similarly C3 And C4 Again look ahead Carry generator We have 8 inputs What are the inputs P0, P1, P2 and P3 Similarly G0, G1, G2 and G3 So G0 G1, G2, G3 terms Or P0 G3 terms These are generated using The AND gates and exclusive OR gates All these 8 terms Are connected Look at the input of the carry generator Look at the output of the carry generator Basically we got C1 C2 and C3 And C4 Now when you are going to be Implementing 16 bit Arithmetic logic unit Which we said Cascading together Or connecting together 4 of those 4 bit ALUs Now The 381 ALU It has 2 group Carry Propagate and generate Terms Basically If you look at the output of 381 You will see a G term Or a P term Which we are representing Now if you have 4 Sets of 381 Which have to be connected together All these G terms Or P terms Where are these connected Look at the carry generator Look at the carry generator The last time we talked There are 8 inputs In G terms and P terms All these 381s G terms The P terms will be connected The output of 381 C1, C2, C3 and C4 Now C1, C2, C3, C4 Where will they be connected These will be connected Cn The input of 381 So the second The first 381 The carry input will be 0 381 The second carry input Will come from the carry generator Similarly the third carry Where will they be connected The circuit diagram Will be easier to understand Let us have a look at the implementation Of a group carry look ahead generator But before that Let us first have a look at the function table Of the 381 Which art functions perform After that we will see How the group carry look ahead generator So let us have a look Let us have a look at the Arithmetic logical functions Performed by the 34 series 381 4 bit ALU It has 3 functions select Input pins S0 S1 and S2 Through these 3 functions select input pins You can select 8 functions So 0 0 0 Performs f equals to 0 0 0 That is the output is set to 0 By selecting the function input 0 0 1 ALU performs the operation b minus a minus 1 Plus carry in Similarly by selecting the input 0 1 0 ALU performs the operation a minus b minus 1 Plus carry in 0 1 1 Allows the ALU to perform The function a plus b Plus cn Similarly by selecting 1 0 0 A exclusive or b 1 0 1 Allows the ALU to perform a plus b 1 1 0 Allows the ALU to perform a and b And by selecting 1 1 1 The output is permanently set to 1 1 1 1 The 381 ALU Has A g output and a p output Which is known as a group Carry look ahead output Both are active low outputs G is represented by the boolean expression g3 plus p3 Into g2 plus p2 p3 g1 Plus the product of p1 p2 p3 And g0 This is inverted As the output is active low Similarly the p output Which is again active low It is the product of p0 p1 p2 And p3 Now the g Active low output And the p active Low output of each 381 Is connected to A look ahead carry generator 74182 The look ahead carry generator Has 4 p0 p1 p2 p3 Inputs And 4 g0 g1 g2 And g3 inputs The output of the Look ahead carry generator Is c1 c2 c3 And Another set of p and g Outputs so you can cascade More Look ahead carry generators We have looked at the look ahead carry generator And we have looked at the group Carry terms g and p Basically if you Remember c4 The carry output The last time we discussed The boolean expression Is exactly the same In terms of g and p We would like to have a look At the implementation of 16 bit ALU We will see that in the next lecture Because we have to discuss it in detail In the next lecture We will resume our discussion With the implementation of 16 bit ALU Till the next lecture Good bye