 Hello and welcome to this presentation of the STM32-C0 The STM32-C0-PWR backup registers are intended to keep some key information about the application state during the low power modes and resume from it except shutdown. As there is no secondary power supply such as a battery, the PWR backup registers keep information as long as the main VDD voltage is present. The backup registers are organized in 4 16-bit registers stored in the APB memory space. They can store state information that's preserved when switching to standby power state. The backup registers are not reset when exiting standby mode as well as when the PWR RST control bit of the RCC APB RST R register is set. This PWR RST control bit is used to reset the PWR domain. In terms of weight states, access to backup registers require 3 extra APB clock cycles on write and 2 on read compared to standard APB access. The backup registers on STM32-C0-X is powered from the VDD domain as there's no VBAP domain implemented. In STM32-F0 and STM32-G0 series, the contents of backup registers may be preserved when the VDD power supply is switched off. In addition to this presentation, you may find the power control training module useful. Thank you for attending this presentation.