 Hello and welcome to today's lecture on main memory organization. In the last three lectures, we have discussed about various techniques by which the performance of cache memory can be improved like its hit time can be reduced, miss rate can be reduced and miss penalty can be reduced. Now apart from cache memory, there is another memory which is also very important which is known as prime memory or main memory and today we shall focus on the main memory. First after giving a brief introduction, I shall discuss about the various types of main memories that is used in computer systems, contemporary computer systems and question naturally arises, why do computer designers need to know about memory technology? Why does this question arise? The reason for that is processor performance is usually limited by the memory bandwidth. We have seen that as the IC densities are increasing, lots of memory will fit into the processor chip, so there will be many memory devices will be present in the processor itself on chip and also there will be some memory devices will be off chip, particularly you can tell the on chip memory to specific needs and we have seen the use of instruction cache which can be on chip, data cache which can be on chip and another type of buffer known as write buffer that is also used to improve the performance and which is also on chip. Now, let me very briefly give you the characteristics of memory, how do you really define or characterize memory devices, there are three important parameters as you fabricate the memory devices using semiconductor technology, number one is the area, how much chip area it occupies then speed, how fast it is which is usually specified in terms of access time and the power, power dissipation is also very important in the present day context because of several reasons, number one is you know in embedded applications the devices are battery operated, so life of the I mean usefulness of a particular embedded system is dependent on how long the battery will survive. On the other hand in case of your desktop and also in workstations and server power dissipation is also very important because we know that the reliability of the device is dependent on the power dissipation, so these are the three important characteristics which are important to in the context of memory devices. However, there are different ways by which we classify memory devices particularly semiconductor memory devices, number one of them is basic operation modes the way they operate and in this context the memory devices can be divided into two categories read write or read only. In the read write category you have got S RAM, static RAM, dynamic RAM, E from, E from flash memory and so on. On the other hand in the read only category you have got mask programmable ROM and there is another way you can categorize that is your data storage mode in which the data is stored. In this context the basic category is volatile and non-volatile, volatile means as long as power is there information is available as the power is removed information is lost. So, some memories like static RAM and dynamic RAM which are volatile in nature, similarly you have got non-volatile type again there are two basic categories under this non-volatile type. Read write where in which you can perform read as well as some write like flash memory, EP ROM, E from I shall discuss about them in more details then read only category mask programmable ROM. And another way in which you can categorize is by access mode. Access mode is there are two basic ways one is known as random, random means irrespective of the location the access time is fixed, access time is not does not change irrespective of the location of the memory within the chip. So, random access that is why you call it random access and ROM, static RAM, dynamic RAM, EP ROM, E from flash memory all these belong to random access memories. On the other hand there are some non-random access memories like serial access memory and content addressable access memory cam. So, they belong to non-random category because the access time is dependent on the location of the memory within the chip. So, with this background let us see what are the types of semiconductor memories we use in our present day computer systems. Basically as I said you have two categories random access memory and read only memories. And random access memory there are two types static RAM, S RAM or dynamic RAM, D RAM. On the other hand in the read only memory category you have different names like mask programmable ROM, programmable ROM. Mask programmable ROM is called ROM in short and programmable ROM is called P ROM in short and electrically programmable ROM in which you can do the programming and I mean reprogramming is allowed in both in programmable ROM it is if the programming can be only once but electrically programmable ROM programming can be done more than once. And then you have got electrically programmable and irresistible ROM flash memory and NV RAM which is non-volatile RAM as we know RAM is in general volatile in nature. But in NV RAM what is being done within the RAM chip battery is provided so when there is no power then that built in battery provides the power and making it non-volatile that is why it is called NV RAM. So, these are the different categories so we shall start with static RAM. Basic organization of a static RAM or rather the basic cell or a particular bit can be stored using the, I mean a bit can be stored in a cell the organization is somewhat like this the way it is realized is two inverters connected are connected back to back. Then you have got two transistors and when this is connected to what is known as row line these are connected to what is known as bit line and this is bit line bar. So, this is bit line and bit line bar now in this case you can see there are two inverters connected back to back these inverters can be realized by using CMOS technology as usual and suppose this whenever say I mean this is zero this will make it one and this one will drive this particular inverter and it will make it zero. So, there will be a kind of regenerative action that means as a particular point becomes zero the output of the inverter becomes one that one drives the other inverter which forces the other point to become zero and that is how very quickly the device will switch from one state to another state and that is the reason why the s ramps are this type of memory is known as static ramp are fast. Now, you can realize I said you can realize the static ramp by using CMOS technology in that case you will use the inverters you know by using two transistors that means two this is one inverter this is an inverter and another inverter is this one then this is connected to ground or VSS V substrate. So, these two inverters are connected back to back this is connected to VDD and you will use two additional transistors to connect to take the output which are known as bit line and bit line bar and this is the input. So, this has to be connected to this output and this input needs to be connected to this output. So, you see two inverters connected back to back and two transistors are used to take the outputs from these points. So, you get both the output and output bar that means the normal output and its complement both are available from a particular cell and this is the typical six transistors cell of static ramp. So, this particular static ramp cell provides you low power dissipation why low power dissipation as you can see since this is a CMOS inverter when this transistor is on this transistor is off here also when this transistor is on this transistor is off. So, there is no static current flow. So, as a consequence the power dissipation is quite small in that is this type of circuits. However, you have to take the outputs by using two additional transistors. So, you require six transistors and I have already told it provides you high switching speed the high switching speed comes from the regenerative action that take place which I have already explained. It also provides good noise margin the reason for that is the outputs switches from rail to rail that means V dd to 0 I mean 0 you get 0 volt very close to 0 and the one you get very close to V dd. So, rail to rail switching you get and that gives you good noise margin and also it gives you large chip area because you know this is standard CMOS technology can be used and you give the chip area that can be obtained is quite high I mean large chip area can be realized. So, that means, you can put lot of these cells on a single chip and nowadays virtually all processors use S RAMs as cache memory. I have already mentioned about the we have discussed about the cache memory without mentioning the technology that is being used in realizing cache memory. And the cache memory is cache memory uses this SRAM circuits for the realization within the chip. Now, one severe limitation of static RAM is the number of transistors that is required to realize a cell. So, for storing a single bit you require syncs transistors and obviously whenever you are thinking in terms of 2 MB 2 megabyte or 6 megabyte or nowadays you know computer systems have got several gigabytes of main memory. In such a case the total number of transistors will be very large and we have to reduce the I mean we have to find out some alternative way by which the packaging I mean the number of transistors required is small. And this is how you can realize a RAM chip you can see you have got a memory matrix 128 by 128 and this is the row decoder this is the column decoder what is being done the memory is organized in terms of 2 dimensional matrix. So, you have got say 128 by 128 memory cells are present here. So, this is your memory matrix and then the here you apply some of the address lines say some of the address lines and this is known as row decoder and row decoder output is applied. And also you have got column decoder here is your column decoder and to which you apply some other address lines that means the lower order address lines you apply here say a 0 to a 3 and here you apply a 4 to a 10 that means and this is the column I O this column I O here you have got sense amplifier and other things which communicate which receives information from the which interacts with the this memory matrix. And then you have got the input input data control input data control here here the outputs are taken from here. So, here you will get get say I O 7 to I O 0 this means you are storing 8 bit data in this. So, 8 bit data comes out through these lines and of course you will require some additional inputs like as it is shown in this diagram output enable write enable chip selects these are used for controlling the devices that means and so major components that is present here is memory cell array this is the memory cell array then you require two decoders column decoder and row decoder I O control circuit this is the I O control circuit column I O control circuit and the I O interface circuit. So, this is the column I O interface circuit is connected here. So, through the same lines you get the input as well as you get the output. So, these lines are bi-directional on the other hand the address lines are unidirectional and you have got several control signals output enable means whenever this output enable is output enable is lower this is low active when it is 0 then only output is available otherwise it is tristated. So, this chip can be represented in this way here you have got n address lines in addition to that you will be having chip select you will be having output enable and also write enable these are all low active and here you will be having 2 to the power n into m bit assuming that there are m lines available at the output. So, this is the basic organization. So, these are the address lines these are the data lines and here you can see that the control within this chip is performed with the help of these 3 signals C S output enable and write enable and when this chip select is high as I said it is low active represented by this symbol when it is high respective of these lines you will get the output will not be selected. So, you will be it will be not selected and IO pins these IO pins these are essentially the IO pins data lines will be in the high impedance state. So, high Z now only when the chip select is low this is a low active and then you can have other variations like output output enable is high write enable is high in this case output is disabled again in this case it will be high Z and when the output enable is low and this is high then you will get the output. So, this is essentially read mode of operation that means the output at the output you will get the data that is being stored. So, this is data out and similarly whenever it is low and this is low this is high output enable is out irrespective of this that means this can be independent of this when write enable then it is a write mode and you will get data in. So, this is how the chip is controlled and the organization is shown. So, the address is what is partitioned into row address and column address row address decoder enables one of the rows and the column address decoder enables one of the words and that is how the communication take place with the outside world. So, this is the basic static RAM chip organization and write operation is done by driving the bit lines 1 and 0 and selecting the row and that will perform the writing on the other hand read will involve pre-charging the IO line the bit lines bit and bit bar to VDD and both the lines are pre-charged to VDD. So, it is based on pre-charge logic and then you have to select the row by providing the row address and the cell pulls one line low depending on data being stored there depending on what is stored it will pull down on one of the low that will be sensed by the sense amplifier on column and sense amplifier is on and column detects the difference between the bit and bit bar. So, there is a kind of differential amplifier which acts as sense amplifier and then that difference is reflected at the output and you get a output. So, this is a nutshell how the static RAM read write operation take place and now let us focus on dynamic RAM. As I mentioned the number of transistors in static RAM is quite large 6. So, if we want to reduce the number of transistors then we have to go for some other technique and that has led to dynamic RAM cells. So, it started with and 4 transistor dynamic RAM cell as we shall see this dynamic RAM technology has evolved over the years. So, starting with 4 transistor cell to single transistor cell for example, in this particular diagram you have got 4 transistors. So, essentially those pull-up transistors that means the pull-up transistors are not present here, but you have got 2 transistors T 1 and T 2 which are acting as the basic cell storing information and 2 additional transistors those pass transistors T 3 and T 4 for getting the output on bit line and bit line bar. So, in the quest for small achieve area 4 transistor D RAM cell emerge and this is also volatile in nature, but where does the information is stored information is not stored in the flip flop this is not acting as a flip flop information is stored in the gate capacitance gate cap which gate capacitance for example, although this capacitance is shown here this is essentially the capacitance of this transistor. So, gate capacitance of this transistor these are parasitic capacitances you are not connecting any additional capacitance and this capacitance capacitor is also corresponding to this particular gate. So, in these gate capacitances you are storing information in the form of charge. So, you are storing charge and obviously, one of the capacitors will be discharged if this transistor is on if T 2 is on this capacitor will be discharged and if this transistor is off this transistor will be charged. So, that in that charge and discharge signal I mean which one will be charged that will come from this bit lines that means if it is one this one will come here that will make this transistor on. So, which will pull down this capacitor this charge to 0. So, information that is being stored in the capacitor will be present, but how long it will be available if you turn it on information will be lost that will that will make it that makes it volatile, but say suppose you have stored some information one is stored in this particular capacitor some charge one corresponds to storage of some charge 0 corresponds to no charge. So, that is been stored question is how long it will the information will be retained it has been found that the I mean any capacitor has a property known as it will it will the charge will be leaked away. So, here also the information that is being stored in these capacitors that will be lost because of the leakage of the charge and that is the reason why another technique is used that is known as refreshing. So, to retain information the cells must be refreshed periodically that means the refresh controller will read the value and as the voltage goes down because of discharge it will again recharge the capacitor where one is stored. So, whenever you realize in this form there is marginal area advantage over 6 transistor RAM. So, you do not have do not get much benefit because you are saving two transistors, but the capacitor should be quite I mean relatively large. So, that information is stored in other words this transistor will be of little bigger dimension. So, you do not have much advantage and that has led to another type another type of cell known as three transistor cell. So, in this three transistor cell here you have you are not using four transistors, but you have a single transistor and the gate capacitance of this transistor is used to store information and then you are taking the output with the help of again two transistors this is your this is connected to that word line and this is connected to bit line and this is also connected to bit line. So, this is bit line read and this is bit line right. So, in this case the operation is different here you are applying right line right signal and for read you are using this is for right this is for this is for right and this is for read how it is happening. Say you can see the bit line is connected here if it is one and as you make this transistor on this capacitor will be charge will charge through this transistor this is how you can write information in this gate capacitance of this transistor. So, this is the parasitic capacitance and here the charge is stored and one is stored here. Now for reading purpose you make this transistor is this transistor on that means whenever you are reading this transistor is on if one is stored here this transistor will be on and so this will be 0 you will get I mean one is stored here then you will get if you perform this read operation this will be connected here if one is stored you will get 0 here compliment of it you are getting here. And if 0 is stored this transistor is off and so you will get one here. So, you can see you get the compliment of that output corresponding to what is being stored here. And in this case the gate capacitor T 2 is used to store the information to additional transistors are used for read and write as I have told and it has been found that this is faster than 40 cell reading the 3 T cell is non-destructive here you know since it is isolated by this gate the operation is not destructive that means reading can be done with the help of these two transistors. And also the fabrication process is compatible with CMOS. So, this is another technology that was used for realizing dynamic RAM cells. Now let us come to a significantly different realization where you are using two transistor dynamic RAM cell. In two transistor dynamic RAM cell you can see there is no gate capacitance present here. So, you have to explicitly fabricate these capacitors. So, the two transistor RAM cell is essential and extension of 40 RAM cell with the exception that you are not using the gate capacitance to store information because you are using some two capacitors are explicitly fabricated which will store the information. And you get both bit and bit line bar information depending on what values are stored. So, if this is one then this will be charged if this is I mean when this bit line is one bit line bar will be 0 and that will discharge this capacitor. So, about 0 and 1 the complementary values will be stored and as you select these two transistor by activating this word line then you will get the bit line and bit line bar at the output. So, this is the two transistor dynamic RAM cell. However, this was also not very popular and this is not very popular in the present context we have gone for what is known as one transistor dynamic RAM cell. So, here you can see you have got only one transistor. So, only one transistor is here and that capacitor which is explicitly fabricated is present here. This is the storage capacitor and you have got two lines this is your write line for read and write word line for performing read and write and this is the bit line this is also used for read and write. So, this is word line this is the bit line how it works. So, suppose the bit line is one you have to store one and then whenever you activate this word line this transistor is on and it will charge the capacitor. On the other hand whenever it is zero charging the capacitor means it is one. Now, if you if it is zero then of course, this capacitor will discharge through the through this transistor and it will there will be no charge as you write it. So, writing is I mean writing is done in this way by charging this capacitor or discharging it by turning the I mean word select word line transistor on. However, let us let us see how do you perform read. So, whenever you are performing read then again you are activating these transistors. Now, the charge store available here will be available on the bit line. So, it has been it is found now that this is no longer isolated by a gate that means this particular capacitor is no longer isolated by a gate it is directly connected to the bit line. That means all the charge that is being stored here gets transferred to the bit line of course, there will be sense amplifier this difference in the charge on bit and bit line bar will help you to get the output, but unfortunately this capacitor will get discharged. So, in other words read is destructive read operation is destructive. So, this is a significant improvement in the DRAM evolution by switching to this one transistor dynamic RAM cell. So, only one additional capacitor is explicitly fabricated for storage purpose in addition to a single transistor and to store one it is charged to V d d minus V t. So, you are not charging to V d d because since it is charged through this transistor as you know there will be a voltage drop of V t. So, you will get V d d minus V t here and that will it will be charged to either V d d minus V t or it will discharge to 0 volt. And as I explained read operation is destructive and you require sense amplifier for the purpose of reading because this signal has to go to sense amplifier to amplify the signal. And so read operation is followed by restore restoration operation. That means if there was one was stored there you have to write back one you have to restore the information and that is why the dynamic RAMs are slower. And of course the advantage here is you require very small chip area you can go up to say 256 megabit on a chip or more. Nowadays you can have large number of transistors on a single chip. And another unfortunate part is that the process technology is not compatible with CMOS process technology. So, up to you know three transistor we have seen the dynamic MOS circuits dynamic RAMs transistors dynamic RAM was compatible with the CMOS technology. But two transistor one transistor cells are not compatible with CMOS technology. So, you have to go for an incompatible technology to fabricate the chip. However, because of large packaging density this is very popular and widely used nowadays. And this particular type of dynamic RAMs are virtually used in all desktop servers as main memory. And this is the typical organization here also you have got row decoder, column selector and IO circuit and at the intersection you have got one cell one transistor cell. And this is these are the word lines and these are the column lines and here you get data. So, row and column address together are applied and which actually selects a particular bit and you get a single bit at the output. And you can see this is the typical DRAM organization of a commercial chip. So, here you are using several address lines A0 to A10. Now, another important change that is the address is given same address lines are used for applying to row address and column address. Earlier we have seen that row address and column address here you can see the row address lines and column address lines are applied I mean which are lower order bit goes here and higher order bit goes here. But in dynamic RAM that is not done. The reason for that is that now you want to reduce the number of pins total number of pins increases as the size of the memory increases. So, suppose you have got 64 kilobyte or 54 K bit let us assume it is bit organized 64 kilobyte. So, you will require 16 address lines. So, instead of applying all the address lines together you use eight line then another eight line. So, this is for 64 kilobyte, but whenever you have got much larger capacity say 256 kilobyte or 1 gigabit then the number of lines will be more. So, you are saving eight pins by applying the address I mean row address and column address separately. So, that is what is being shown here for example, in this case total number of address lines is 20, but you are using row address and column address you are using two separate buffers one for storing the row another for storing the column. So, row address and column address are coming from the same lines and as a consequence you will require two signals row address I mean select and column address select. So, row address select and column address select these two inputs are there whenever you are applying row address then you have to activate the row address select and whenever you are applying column address then you have to activate the column address select. So, in addition to write enable and output enable to additional control signals are necessary to control the chip. So, and you have got a multiplexer which is needed for refreshing the memory. That means the refreshing takes place row by row and that is the reason why you are using a refresh counter. So, refresh counter output is multiplexed with the row address either this row address is applied or when you are refreshing then the refresh counter output is applied to the row decoder and which selects one of the rows in the memory and that entire row gets refreshed not one cell at a time, but entire row gets selected. So, this is the refresh circuitry and column decoder output column address is applied here to the column decoder and you get the two lines data input buffer data output buffer and through these you get the output data lines. So, in this particular case it is shown that there are four data lines, but in the nowadays always the DRAMs are beat organized. What do you really mean by that? That means you will be it is organized in the form of 2 to the power n into 1. So, the number of data lines is 1 and again n is divided by n by 2 and n by 2 that is row address and column address. So, your total number of pins required is n by 2 plus 1 I mean for address and data of course, for control and other purposes you will require four more. So, total number of lines will be required n by 2 plus 1 plus 4. So, the number of pins that is required is significantly reduced by using this beat organized memory and also by using row address and column address. As I mentioned main memory is always dynamic RAM based dynamic RAM it is called dynamic since needs to be repressed periodically. So, you may be asking why the name dynamic? So, to make the difference with static since it has to be repressed at the interval of about 8 millisecond and that is why the name dynamic RAM and this repressing causes variability in average memory access time. So, we have seen in case of static RAM we are there is no need for repressing. So, here there is additional time that is required for repressing as that will contribute to the average memory access time because sometime will be wasted for the purpose of repressing. And as I have already mentioned the address is divided into two halves row address row access stroke RAS and column access stroke that is column I mean CAS. These two signals are required for CAS row address row access stroke and column access stroke those signals are to be provided for giving the providing the repressing I mean N by 2 and N by 2. Now, the access time and cycle time is also different in case of dynamic RAM. So, we know that access time is the time between when a read request is made and when the desired word arrives. On the other hand cycle time is the minimum time between two requests in the memory. So, dynamic RAMs require a data to be written back after read we have seen you have to do the repressing that is why the access time and cycle time is different in the context of dynamic RAM which is not true in the context of static RAM. So, this is the history of dynamic RAM it was it patented back in 1968 by Dennard, but it was not commercialized significantly cheaper than SRAM 1 transistor and 1 capacitor versus 6 transistors and 1 bit is represented by a high or low as we have already seen. And one very important aspect is static RAM is I mean it is significantly slower than static RAM. So, SRAM is used for on chip memory like cassettes and scratch pads and dynamic RAM is always off chip. So, dynamic RAM it is off chip because of two reasons number one is that technology is different processor is fabricated by using CMOS technology dynamic RAM is not compatible with that. So, it has to be off chip separate chip. So, this is the pin layout is shown. So, just to compare here you can see 8 megabit EPROM. So, with the help of 32 pin chip dual end line pin package you can get 8 megabit EPROM. On the other hand you can see only by using 24 pin chip you can have 16 megabit dynamic RAM. Here as I mentioned you have got I mean multiplex address that A0 to A9 those two ten address lines are applied in a multiplex scanner selected by RAS and CAS. And of course there are four data lines present here it is not bit organized, but now a days since the capacity has increased it is bit or it is made bit organized. Now let us focus to read only memory so far we have discussed about the RAM technology. Now let us consider the read only memory. Now you may be asking why do you require read only memory? You see whenever you turn the computer on then there will be nothing in the RAM. So, how the CPU will work? CPU is a dump device it has to get instruction from somewhere. So, where from it will come? It has to be stored in a memory which is non-volatile and that is what is stored in RAM. Just like you know when a child bonds that child must bond with some built-in intelligence and with the help of which that child starts taking I mean communicating with the environment mother and relatives and parents and starts crying by making the difference. So, it bonds with some built-in intelligence then subsequently it acquires intelligence from teacher father and environment nature. So, you require read only memory in your system for example, in your computer system that BIOS basic input output system is stored in the ROM. And this is the basic organization of a read only memory as you can see despite its Gandrayo's name it has got two distinct components one is known as decoder as you require in any memory system and decoder is there in addition to the decoder you require encoder. So, you will require decoder and encoder and you can see the decoder depending on the number of lines if there are n address lines it will generate 2 to the power n lines at the output of the decoder and at any particular instant one of them will be active as you know that is the basic function of a decoder. So, it will select one of the many lines and that will go to the encoder. Now, in the encoder as you can see the you can have dots corresponding to different lines. Now, you can store 0 and 1 in these at the crossing of these lines in the encoder you can see this in some places there are dots in some crossings there is no dot indicating that there is some device it may be a diode or a transistor and sometimes nichrome wire that is being used at each of these junctions and depending on what is present at this junctions the different types of ROMs are realized in case of mask programmable ROM that why it is called mask programmable ROM you know in the factory a mask is created and that decides at what junction there will be a diode or a transistor and what juncture there will be no diode or a transistor. So, depending on what you have to store for example, here 1 0 1 1 that is being stored and on the second line you have stored 0 1 0 1. So, that means, presence of a device makes it I mean makes it allows you to store 1 why because whenever the decoder is activated this line is 1 that 1 gets transmitted to the column line through this link may be a diode or a transistor or it can be a nichrome wire. So, in the factory these are fabricated that is why it is called mask programmable ROM or simply ROM. Now, in case of programmable ROM you know the mask programmable ROM is fabricated in the factory. So, this can be done only when it is produced in mask scale that means, you require millions of such devices only then you can order a ROM and which can be fabricated in a factory. So, that is used only when you require a particular device particular type of encoding in large numbers. On the other hand this programmable ROM is user programmable. User programmable means the user can do the programming, but programming can be done only once how suppose you have got a nichrome wire connected here. So, that nichrome wire can be burnt by programming. So, with the help of a from programmer you can burn the connection between the color row line and column line and so it cannot really reconstruct it that is why you can do it only once that is why in programmable ROM the writing can be done only once. However, reading can be done many times that is why it is programmable read only memory. Now, the third type electrically programmable ROM in this case the programming can be done by electrical means. So, by electrical means the electrical means the programming can be done and in such a case the device that is being used is little different a MOS transistor is used and in the MOS transistor you know that in the MOS transistor there is a floating gate which I shall show in the next slide that is being used for example, this is the technology that is being used in case of electrically erasable and programmable ROM. So, in case of sorry this is in case of e-prom it is electrically programmable, but erasing is done by exposing to ultraviolet light. So, this is not really epi ROM, but it is epi ROM one you will be there. So, can be programmed and erased actually there are two techniques in the first case in case of epi ROM what is done the programming is done by applying a high voltage to the select gate and there is some electrons get accumulated in the floating gate and that floating gate and the that high voltage that actually overcomes the barrier and electrons can be put in this put in this particular position and that remains in those I mean near the gate and then for the purpose of erasing there is an optical window which you must have seen the the electron can be taken out and it will come out of the because of the energy that is being obtained from the from the from the ultraviolet lines source and electrons comes out. So, again it becomes zero that means whenever you do the programming you can say zero is stored and whenever you do the erasing all the cells become one. On the other hand in case of electrically programmable the another variety electrically programmable and erasable ROM you can do the programming and erasing electrically how it is done you can this is what is written here can be programmed and erase many times over and over erasing sets all the bits to zero and so you require off system erasing selective erasing is not possible and this is low cost and easy available that means erasing is done all the time in case of IP ROM, but in case of electrically erasable and programmable ROM which is a version of electrically erasable and programmable ROM you can do the writing and reading selectively. So, this allows a block to be raised or written in a single operation in a flash that means instead of a single word in case of electrically erasable and programmable ROM writing is done word by word, but in this case it is done block by block that is the difference between e ROM and flash memory. So, floating gate avalanche injection metal oxide semiconductor is used for the implementation of a cell and electrons are trapped in the floating gate as I have already mentioned in the and this is shown here. So, those electrons get tapped you know trapped in these floating gate as you can see here. Now, by applying a high voltage you are trapping electrons are getting trapped here and that is being stored here and then if you remove that high voltage the threshold voltage of the device increases. So, for those transistors I mean where those electrons have been trapped their threshold voltage is high for other transistors where the electrons have not been stored the threshold voltage is low. So, that will be used for the purpose of reading and writing and writing a byte requires creating a new block old block is copied along with the byte and so this you can do block by block in flash memory. So, the reading can be done at the speed of dynamic RAM. So, at the speed of nanosecond you can do the reading however writing is quite complicated because you have to apply a high voltage and that high voltage has to be applied for certain duration. So, that those electrons are get trapped and that takes of time of the order of millisecond. So, writing is a complex operation even in flash memory and memory capacity is increased by reducing the area dedicated to control erasing because instead of controlling byte by byte you are controlling block by block. So, number of writes is restricted due to wear in insulating wear oxide layer used to take 12 volt to write. So, present generation flash operates at 2.7 volt that means when you are using in the read only mode voltage that you require is 2.7 volt, but for the purpose of writing you require 12 volt. And nowadays you can go for multi level flash technology what do you really mean by multi level flash technology. So, this is very interesting we know that for 0 it can be 0 volt and for 1 it is let us assume 2.7 volt. Now, what can be done you can if you are allowed to store an intermediate voltage may be 1.3 volt then what you can do that intermediate voltage can be used for the purpose of storing say 00, 01, 10, 11, 2 I mean 2 bits can be simultaneously stored by storing multi level voltages in those capacitors and different levels of voltages. And instead of storing only 1 bit it will be possible to store more than 1 bit that means this may correspond to 00, this may correspond to say 11, this may correspond to 10 and somewhat like that. That means if intermediate voltages you can store say 1 it can be 1.0 or it can be say 1.5 that may correspond to 01 I mean just I am writing arbitrarily, but this is the basic idea of multi level flash technology. So, this is possible, but not yet commercially realized. So, here is a comparison between flash memory and EEPROM. I have already explained that flash memory is faster because you are writing in terms of blocks and flash can be written in system contrast to EEPROM. EEPROM cannot be written in the system, but flash memory can be written in writing in system. So, control circuitry required for erasing is much less leading to higher capacity of flash memory as I have already told. Anyway, so with this we have come to the end of our discussion on different types of technologies that is used in realizing memory devices. In my next lecture I shall discuss about how you can reduce this main memory access time essentially that will help you to reduce the miss penalty. So, just like improving the cache memory performance we would like to improve the main memory performance. So, what are the techniques that can be used for improving the main memory performance that I shall discuss in my next lecture. Thank you.