 NIT Warangal, can you ask your question please. Can you explain how the designing circuit, biasing circuit is designed such that it is able to amplify easy signals. Yeah, the bias current determines the voltage gain and so on according to the theory which would have been developed by professor Joseph John. So, essentially what we do is that we make sure that current is in that ratio as required by various stages. So, we generate a reference current once and for all which is what we had seen here. Then there was a transistor here which was diode connected and this was I think R 5 about 39 k and then another diode connected transistor. So, there is a VBE drop across this and a VBE drop across this and this is say plus 15 and minus 15 and this is about 39 k. Therefore, if you just add up all the voltages then you will get 0.65 that is this voltage plus I times 39 k that is the VBE drop across this and plus another VBE that is this voltage and that should be equal to 30 volts that is the potential difference between this point and this point. So, now I is the only unknown this VBE is also 0.65 and together they make it about 1.3 volts. So, therefore, I is equal to 30 minus 1.3 divided by 39 k and this is the one which gave that 739 micro amps or whatever that we had. So, it sets up this voltage and now this VBE becomes the reference for many other current mirrors. Now, if you have an identical transistor with the same VBE then its current will also be equal. So, therefore, that will also have the same amount of current, but if you want less current or more current then you can choose to change the collector or the emitter size of that which will then give you a current division in the ratio that you want. So, that is what the rest of the bias circuit does. The part which was a little interesting was in fact that you had the Wiedler source here and that is done by putting another transistor with a resistor here. So, the VBE of this equal to VBE of this these two are not equal because this R i also has to be accommodated. So, this VBE is k T by q this R f i ref that we had calculated this is equal to k T by q again this voltage is now being calculated from the right hand side. So, equal to k T by q l n i 2 i 2 is the current which flows here i ref is the current which is flowing here i 2 by i s plus this is R 4. So, that means R 4 times i 2 and again this has to be solved iteratively to get the value of i 2 and as I had shown you get the desired value. So, when you design that common emitter amplifier then you find out how much current the differential amplifier then you find out that for the gain and the input impedance desired how much current you need and that current is then adjusted by the value of this R 4. So, that this guy will draw that much current over Mufakkam college Hyderabad hello good afternoon sir. In new year 741 I see in the beginning we are having two differential stages as dual input balanced output and dual input unbalanced output. Why we need two stages as balanced in balanced output and balanced unbalanced output what is the need. Now, we would we would stick to this 741 design because otherwise we will have no time left for discussing all sorts of other circuits. So, in this there is only a balanced input the other input by the way which is provided in some circuits as you can see here that these two outputs are also provided and the reason is that this circuit should be exactly symmetric to be truly differential otherwise there will be an offset. So, in order to balance the two arms you can put an external potential divider to ground between these two and that is the one which will balance these two in this circuit. We will not be discussing other op-amps in this discussion because we are very limited time and we cannot take over all kinds of circuits. So, let us just stick to this circuit. Don Bosco, Gohati please ask your question. Sir, for an op-amp with supply voltage class V minus V volt what is the maximum output that can be obtained without distortion. This is the circuit and this is the output voltage. So, notice that the output voltage is given by the supply voltage minus the saturation voltage of this transistor and the small drop across these 27 ohm resistors. So, the highest voltage that you can get without distortion requires V d d minus some voltage which depends on the design and in this particular case this will be about half a volt which must be dropped across Q 14 and this resistor. So, it can swing to within V d d minus whatever voltage is required and this varies from the actual construction of these transistors and from design to design. However, it is typically almost, but not quite rail to rail. So, if you actually try to raise it to a value which is much higher than that then this transistor would be saturated and the gain would be small. So, therefore then you will start getting distortion. So, therefore you must remain, you must give an operating voltage to this transistor so that it works properly and that operating voltage is at least half a volt, but it in general for good performance you might want to give it a little more. So, the output can then swing to within half a volt to a volt of the power supply in this design, but there are other designs which might use multiple transistors and so on and therefore, this figure will vary for other transistors over. Tanthai Beryar Velour, could you please ask your question. Sir, sir my question is, first question is with respect to internal circuit diagram could you explain a common mode rejection? My second question is could you give me a numerically example to find out CMRR practically over to you sir. CMRR is defined as the ratio of the differential gain to the common mode gain. We want ideally this ratio to be infinite that is to say you want very large gain for the differential signal and 0 gain for the commercial for the common mode gain. Now, let us look at development of the differential amplifier and that will make it quite clear. Why do I use the differential amplifier as it exists? I could have simply used a circuit like this with appropriate bias and take the differential output from here. So, what would be the problem with this? Let us first try to understand that. Why do we use a differential amplifier with a long tail pair which looks like this, where this lower transistor is a current source. So, rather than using this simple circuit, we use this somewhat more complicated circuit in all differential amplifiers. So, there is some variant of this that you will find in all differential amplifiers and the reason for that is the following. Suppose, I have inputs V 1 and V 2 then the common mode voltage is defined to be the average of the two and the differential voltage is the difference between them. Now, what we want is that as long as the average the average we should not be sensitive to the average voltage of the two, we should be sensitive only to the difference of the two and how well can we reject the common mode voltage while amplifying the differential voltage that is measured by the common mode rejection ratio. Now, let us see this case. Suppose, the differential voltage is 0 then suppose, I raise both these voltages upwards then the current through both transistors will go up. It is still balanced however, the current through both transistors will go up. As a result the gain of this stage will now change, we might get higher gain because it is now biased to a higher current. As a result the common mode voltage will not be ignored, the gain of this stage has changed. So, while the output might be a times the differential voltage, this has now become a function of the common mode voltage. As a result my V out will be controlled by the common mode voltage as well as by the differential voltage and therefore, I am not suppressing the common mode voltage. What we would like to do is to keep a constant and amplify only the differential voltage. For doing that we use this differential amplifier. This is like a current source, we bias this remember the opposite of this was used in 741, where we had a PNP transistor from VDD to exactly the same configuration feeding some current into the differential amplifier. Now, because this current is fixed if these 2 voltages are equal it does not matter what the actual value is at both these volt at the at both these bases. As long as it is equal they may both be 5 volts, they may both be 15 volts, they may both be minus 5 volts. It does not matter as long as it is equal then each transistor carries a current which is I by 2, because this current source is feeding a certain amount of current here and because this situation is symmetrical it must split equally between them. Therefore, the current through the transistor is now independent of the common mode voltage and therefore, the gain is controlled by the current given by the current source and not by the not by the common mode voltage. So, now we have a fixed gain and the output is determined largely by VDD. So, this is the reason that we use a long tail pair to make the to make differential amplifiers which tend to suppress the common mode voltage. The output tends to be independent of the common mode voltage as far as the measurement of the common mode suppression ratio is concerned it is quite easy to do. Let us look at this in a practical circuit suppose I shot both of these. Now, any voltage that I apply here will be only a common mode voltage, because the common mode voltage is suppressed the gain of this will be very low now not high, because there is no differential voltage at all. Therefore, if I see the gain of this it will be less than 1 and by seeing the ratio of the amplitudes at this point and at this point I can find out the common mode gain. Similarly, the differential gain has to be determined indirectly, because that is too high to be measured directly. So, what we do is we find the deviation from the expected gain, because the gain is finite and using that we can find the differential gain and the ratio of the two gives you the CMRR. We have already determined the common mode gain and the differential gain has to be determined indirectly. Therefore, if we can determine the differential gain then we can determine the CMRR. So, how do we determine the differential gain? Essentially the way I had introduced the common mode the op-amp first that means we solve the equation for a finite gain first and then express the output as a function of the input voltage and the finite gain. And if you are if you are close loop gain is pretty high then you can actually determine the common mode gain. To take an example let us consider this amplifier. Notice that in this case we cannot assume virtual ground, because we are assuming a finite gain. Suppose we want to determine the differential gain of this which is G in that case v out is equal to G times v x this point being at input the differential voltage is v x minus 0 indeed 0 minus v x and the output will be in fact minus G times v x where the sign of G has been taken out G is the absolute value. Once I have that then I can find out v x. So, then I is equal to v in minus v x upon 10 k and it is equal to v x minus v out upon 1 meg and that tells me that 100 equal to v x minus v out upon v in minus v x. And then you can find out a find out v x as a function of v out and v in. Once you have found out v x then G is nothing but v out by v x. So, now you can find out the differential gain. So, we have found the differential gain like this and the common mode gain like this which is low enough and can be directly measured this has to be indirectly measured. Notice that v out by v x we are finding out from v out and v in which is effectively measuring the closed loop gain and finding out the deviation from 100. If it was 100 then the gain would have been infinite. In the infinite gain case we get a gain of 100, but looking at the small deviation from 100 we can find out what must be the open loop gain. So, we find out the open loop differential gain find out the common mode gain take the ratio and that gives us the common mode rejection ratio. K. J. Sumaya, Mumbai can you please ask your question. Hello sir, transistor number 11 in your internal structure of 741, transistor number 11 and 12 that is actually used as a diode. So, what is the reason behind using transistor as a diode? 4 to e sir. First of all there is no big difference between a diode and a transistor as far as the difficulty of making it is concerned I need this. So, not only this, but you would notice that even this is used as a diode. So, there are many diodes which are required and they are typically made as a transistor. The reason for that is that the leakage current is now included in this. So, it has a much better exponential characteristic than the case in which you would have used there. Remember the diode characteristic has that e to the power q v by k t minus 1. So, you have to make that approximation that e to the power q v by k t is much larger than 1. While that is a reasonable approximation, but if you connect it like this then it becomes truly exponential. So, it now has a much better behavior in terms of finding out k t by q l n i by i s that gives the voltage much better. So, that is the reason and it is no big deal. You are making so many transistors it is just a matter of laying it out there and it is actually quite convenient to combine all these transistors which are diode connected. So, for example, q 12 is diode connected, but notice that q 8 and q 9 can be just made together with a common emitter and a common base only the collector is separate and the collector of this is then shorted to the common base. So, then in fact, while we are calling them q 9 and q 8 they are actually the same transistor. So, there is nothing lost in using a transistor as a diode and it has a slight advantage in the characteristic because the leakage current is now included in the total current of this. Nidhi Kurukshetra, can you ask your question please? Sir, my question is many times we have about open drain configuration. What is the need of open drain configuration? Because many times ICPNs are also open drain. So, what is the need of open drain configuration? The question is that in logic design. So, we are now leaving op-amps behind us. It has to do with my first lecture that very often we have open drain configuration for logic and the answer to that is the following. Suppose I have a bus and various devices are connected to this bus. Suppose the output of each one of them is a traditional CMOS. In that case, what kind of circuit shall I have? Let us say this is a, this is b, this is c. So, consider a which will have an output like this and b will also have an output like this and this is the common wire that is this wire. Now, notice that a and b are independent. These are different devices peaking on the same bus. For example, this could be RAM, this could be ROM. So, therefore, it is possible that while a is 0, b is 1 because a is 0 that means this transistor is on and this is off because b is 1, this transistor is on and this is off. Now, we have a direct path from VDD to ground through the two devices and this will short your power supply. So, you cannot use conventional CMOS devices in parallel shorting their output. Unfortunately, common buses require shorting of the output. So, there are two solutions to this. One of which is to have open drain output. The other is to have tristatable device. In open drain output, this is what we do. Each device has an output which has the NMOS transistor, but does not have the pull-up P bus transistor. So, this is device A and this is device B and this is the common wire and this now requires a pull-up to VDD. Now, there is no problem. If a is 0 and b is 1, then this transistor is off and this transistor is on and therefore, this value equal to 0. So, the wire has acquired b bar. On the other hand, if a is 1, b is 0, the same thing will happen. The wire will still be 0. Therefore, the wire can be pulled down to 0 by either a or b. On the other hand, if both are in their dominant states, that means both of them are off, then the output will be 1. So, in any case, there is no case of destruction of this by a short. So, this is the advantage of using. By the way, this is not specific to MOS. Common collector outputs do the same thing in case of bipolar logic. So, now, I can connect the outputs of various stages. Only one device is enabled at a time. The device which is disabled has a equal to 0 all the time. Now, it permits me to signal for b. Whenever the b wants it to rise to 1, you will turn the device b off. Whenever you want to pull it down to 0, you will turn the device on. So, this device is now capable of signaling 0s and 1s on this common bus. Same thing is true of a. As long as only one device is enabled at a time, the data can go on the common wire. Even if by mistake both are enabled at the same time, then all that will happen is that this device will go to 0 and no device will be destructive. So, that is why very often for buses, we use common drain output. In bipolar logic, heatier logic, you get open collector gates and they also do the same thing. By way of information, by the way you notice that therefore, the dominant state of this is when both these devices are off and therefore, 1. The active state of this is when it is pulled down to 0 and therefore, negative logic is very often used on the bus. So, very often true is a low voltage on a bus, false is a high voltage on the bus because of this configuration. So, you can pull actively a device down to 0 and when you are passive because of this pull up, it automatically goes to high. So, therefore, the active value is low and therefore, negative logic is used on buses. So, this is the advantage of open drain outputs. It permits connections of multiple devices to a common wire. Thank you and I hope I have answered your question. We are back to Kakinada. If you could ask your question now please. Sir, I want to know how to use these op-amps, but producing oscillations like the mean built oscillators, other things such as applications of op-amps. So, if in various circuits that also we are very much interested in like the mean built oscillators. Where naturally it goes, the oscillations, they go into various we get pure silo if you want to control the gain of the op-amp, must be very controlled gain must be there like 3 or so. So, how excellent the queues are to be arranged in so that we get pure silo forum using op-amp in mean built oscillators. That is my question to you sir, over. I can give you one example right now and we will probably post many more examples on your moodle side. If we have time then we will come back with many more applications of op-amp. Consider an op-amp like this. Now if you have this as the inverting input that means when the voltage here goes down the output goes up. This is equivalent to 180 degrees of phase shift. If a sinusoidal input is applied as this voltage goes up, the output will go down and that is equivalent to shifting this voltage by half a cycle. So, that means there is a built in 180 degrees of phase shift. For oscillation two conditions are required. Total phase shift should be a multiple of 2 pi and the loop gain should be 1. In fact, this is very close to what we discussed in the digital domain. When I talked of storage, I had said that you have to make a replica of the signal and then that signal is not required anymore. Oscillators are similar. Oscillator produce an output in which no input is required. Therefore, you must be able to make a replica of the input and producing something with a gain of 1 and an effective phase shift of 0 means that you have made a replica of its input. So, once oscillation starts it can be maintained forever. So, these are the two conditions for making an oscillator. Now in this particular case, 180 degrees of phase shift is already produced. How can we produce the remaining 180 degrees? We know that this circuit can at the most produce 90 degrees of phase shift. In fact, the phase shift is asymptotically 90 degrees. It will always be less than 90 degrees. If you want to produce 180 degrees of phase shift, then you need at least three such units. Now, this unit will can produce 90 degrees of phase shift at some frequency, a phase shift of 180 degrees. If we connect this unit between output and input, let us see what happens. So, I am now talking of the phase shift oscillator. So, you have one unit, you have the second unit and the third unit. Now, it is possible to configure this c and r values. So, that 180 degrees of phase shift is provided here because of the inversion and this provides a total of 180 degrees of phase shift. We also have to control the closed loop gain of this amplifier. So, therefore, to configure the closed loop gain, actually rather than returning it to the ground, we make this into a resistor like this and have a feedback resistor and put the ratio of these two resistors, so that the closed loop gain is just right. Now, consider this configuration. Because of this c r configuration, the signal is actually attenuated. In fact, if you analyze this circuit, if this is v in and this is v out, the current is given by v in divided by r plus 1 by j omega c and therefore, the output v out is r times i which is r upon r plus 1 by j omega c into v in and therefore, v out by v in that is equal to j omega c r upon 1 plus j omega c r v in now, this is less than 1 as you can see. Therefore, there will be some attenuation of the amplitude and the phase will be tan inverse omega c r tan inverse omega c r becomes 90 only when the argument is infinite. For any finite value of omega c r, this can give a phase shift less than 90. Therefore, we require at least 3, otherwise we could have made do with 2 such units, but because the value has to be less than 90, then to produce 180 degrees of phase difference, we use 3 such units and arrange for omega c r to be 60 degrees. Now, we have got a closed loop gain. We have got an attenuation of a certain amount. It comes out actually of the order of 29 or so and then therefore, this configuration should provide a gain of 29 again. So, it should have precisely that much gain. Now, both conditions will be met. The total loop gain equal to 1, this combination would have attenuated by a factor something like 29 or 31 depending on the configuration and this has then amplified back by the same amount. So, the total gain is 1 and the phase shift is 180 here and a further 180 here, so that the total phase is 360. Now, both conditions for oscillation are met and this will act as an oscillator. So, this is one application of an op-amp for making a phase shift oscillator, which will then produce actually a sinusoidal output. There are many other configurations and we will probably take up a few applications of op-amp in a subsequent lecture. Amrita Bangalore, please. Good afternoon, sir. My question is on PLD. You taught us how to develop the product array and I would like to know how to develop even the sum array. We have three product terms A, B, C, D and C, E. Is it using only three single transistors for each of those lines? Three programmable transistors are used. I assume that the product array is clear to you, as you said. In that case, these are the various inputs and these are various potential outputs, each with a load transistor and so on. And these are the various outputs. Suppose I want to include this product, this product and this product in my output. I want to take the sum of these three products. I may have produced a large number of products, but for one particular sum, I want the sum of these. That means, I actually want to produce the OR of all these and that is very easy because I can have a NOR first followed by an inverter. Now, notice that in terms of logic, this was a NOR array. So, I put down exactly the same circuit with these outputs as its inputs and produce a NOR array here. And if I enable the transistors of this line, this line and this line, then for this row, so inside there is this row and I have enabled the transistors of these three lines, then I will get p 1 plus p 2 plus p 3 or in this case, it is p 1, p 3 and p 4 bar. And again now we do at the output, the same trick that we had used at the input. That means, we give straight and complemented versions of each output. So, therefore, the straight output is p 1 plus p 3 plus p 4 bar, but this output because it also has the inverter will be p 1 plus p 3 plus p 4. So, now I have added the product. Please confirm whether that was your question and whether I have answered it or not. That was right and is that meaning that we can program only the product array and not the summary? In a fully programmable PLA, both can be programmed. So, the advantage of partial programmability is that you produce all possible term and then you can make do with only one programmability. That is to say, you decide which term is of use to you, all are generated anyway. So, then you can make do with less programmability, but you may have products which are redundant. On the other hand, you can make both of them programmable. Therefore, different architectures are partially programmable or fully programmable both in the product and the sum array. So, a fully programmable version has the product as well as the sum programmable. Otherwise, it will give you only a few products and you plug the inputs appropriately to those and then you can choose to add selected products from that. Essentially, the programming is producing a product and producing a sum of selected input. Therefore, the selection could have been done for you already in the product and now you can add the selected product or the sum could have been done for you and you can feed selected products for you. Correspondingly, you can either program one array or the other or indeed both. So, that depends on the architecture of the kind of PLD that you have. Over. We can now take a question from MKSS S. Pune. Hello, good afternoon sir. So, in the first stage of 741 operational amplifier, the first stage is differential amplifier. We can see that the differential amplifier is symmetrical in nature. Then, how will assign inverting and non-inverting pins to that differential amplifier? The functionality of those pins are different, but we can look from differential amplifier both are symmetrical in nature. So, over to you sir. This actually depends on how the two inputs are combined. I will illustrate by a simplified circuit which will make it clear. So, let us take the MOS equivalent of that. That way we will cover MOS op-amps also while answering this question. Consider the MOS equivalent of this differential amplifier. This is very similar to the combiner that you had seen for the bipolar case. Now, let us see how this output will behave. Now, this is a current mirror and therefore, both these currents must be equal. So, let us say that this current is I 1 and this current is I 2 because this and this are in series. Therefore, this current must be I 1 because this and this are current mirrors. Therefore, this current is I 1. Therefore, what comes out of this is I 1 minus I 2. If you apply K C L here, I 1 is entering. I 2 is leaving from here. Therefore, I 1 minus I 2 should go there. Now, notice that I 1 has a plus sign and I 2 has a negative sign. So, depending on the final output, whether which one retains the positive sign, which one retains the negative sign, you are producing a differencing and that specifies which input is the positive and which is the negative. Typically, there will be one or two inversions after this by the second and third stage. So, accordingly one of them will become a plus input and the other will become the minus input. I hope that answers your question. Hello sir, my question is what is rail to rail voltage? What is its significance and what is the logic behind calling it as a rail to rail voltage? The power supply lines are often called rails. This is because the PC boards when they were designed were designed to have straight lines taking the power supply voltages and they looked like rails laid down for trains. So, those are called rails. Therefore, in case of an op-amp, this is a rail V plus and this is a rail V minus. Now, the rail to rail voltage is the total voltage difference seen by the circuit connected to this. For example, an op-amp like 741 might have plus 15 volts here and a minus 15 volts here. So, while the power supply is a plus minus 15 volts, the devices have to operate with a voltage difference of 30 volts. Therefore, while designing this circuit, it has to be designed to withstand 30 volts. So, that 30 volts is the rail to rail voltage. That means, the voltage difference from this rail to this rail is actually 30 volts. So, rail to rail voltage is nothing but the total power supply voltage in case of a bipolar supply. In case of a single supply, this is not much of a deal. The rail to rail voltage is still valid, but it is just equal to the supply voltage. But if you have multiple voltages, then depending on their magnitude and sign, the rail to rail voltage has to be taken as their difference and this circuit has to be designed to withstand that total absolute value. Therefore, we need to calculate the rail to rail voltage. And when the output is able to swing all the way up to this voltage and all the way down to this voltage, then it is said to have a rail to rail swing. That means, it is able to produce an output which goes all the way to the positive supply and all the way down to the negative supply. That means, it is capable of giving you an output which swing from plus 15 to minus 15. If it cannot, then there is a saturation voltage and you might say that it is peak to peak voltage can only be plus minus 13 volts when the supply voltage is plus minus 15 volts. So, the rail to rail swing essentially depends the rail to rail voltage determines what is the maximum output voltage that you can take from a circuit. Over, Mepko Shivakashi, could you please ask your question. Good afternoon sir. I want to ask a question regarding transistor biasing. Sir, for analyzing a cell biasing, we convert the circuit into equivalent circuit. Consisting of Vthavanin and Rthavanin, for finding Vthavanin, we consider the resistance are in serious form. For finding Rthavanin, we consider resistance in parallel form. Why it is so, sir? I am not very sure whether I have followed your question exactly, but let me tell you the difference between DC analysis and AC analysis. When we do DC analysis, in that case, we are actually measuring the current flowing from the power supply to the ground and the power supply and the ground are not to be considered at the same potential. For example, consider this common emitter amplifier. If I am doing DC analysis, then to find out the current flowing through this path, I must take these two resistors to be in series because they are indeed connected in series across the DC supply. However, when I do AC analysis, at that time, I am looking at differential. I am looking at only differences in voltages and there is no differential of voltage here and there is no differentiation of voltage here. These voltages are held fixed. Therefore, as far as AC analysis is concerned, both of these are at ground. Therefore, the equivalent circuit will put this point at ground and will put this circuit also at ground. If you now look at this circuit, then concentrated only on R1 and R2, you have this one at ground and this is also at ground. Therefore, R1 and R2 are indeed now in parallel with one end connected to ground in both cases and the other end connected to the joint. Therefore, as far as the AC analysis is concerned, they are in parallel because both these terminals are effectively ground and AC ground means the voltage which is which never fluctuates, which is held fixed. Therefore, both are at AC ground and therefore, that puts R1 and R2 in parallel. However, as far as DC analysis is concerned, then both of these are not at the same potential and for current flow, I must take as they are and then they are indeed in series. I was not very sure whether that is the question that you wanted to ask. So, I will come back to you whether that has answered your question. Thank you, sir. Over. Sridhiva Sir, Institute Kakinanda, could you please ask your question? Good afternoon, sir. My question is related to op-amp, sir. Why op-amp fluidity is limited? At very high frequencies, why op-amp output is distorted? These two questions are somewhat related. Let us look at the output of an op-amp. Again, because it is simpler, I will illustrate using a CMOS op-amp, but the principles are exactly identical in case of a bipolar. Let us say this is the differential amplifier with a current source here and the differential to single ended converter that we had talked about earlier. If you look at the output, what is… Suppose there is a capacitance here. Now, notice that because of the bias, suppose this current is I, when is this device driven hard S? That means when the difference between these two is maximum. So, then what will happen? That all the current is going through one device and zero current is going through the other device. It cannot be any different. In that case, there is zero current here and all of I is flowing through this, just to take an example. Because these two are in series, this draws zero current and because this is a current mirror, this draws zero current. As a result, as a whole, we can draw a maximum of the current I from this capacitor. No more current is possible because this current mirror limits the amount of current to I. Therefore, the rate of change of voltage on this capacitor is given by this relationship and therefore, d b by d t, the rate of change of voltage is given by I by C and both of these are constant. As a result, there is a maximum rate of change of voltage. If you require the output voltage to change at a rate higher than this, in that case, it will not be possible for the output to change at that rate because in order to change the output at a higher rate, you require more current and this current source limits the current to that value. This being the case, this puts a rate, a limit on the value of d v by d t and this is called the slew rate limitation. Now, suppose my voltage is not d c, but an a c. In that case, how much current should I dump or take away from this capacitor in order to change the voltage? Have an output voltage v. So, then c d v by d t becomes c d by d t of the amplitude times sun sin omega t. This is equal to I. If I now take the differential, then that tells me that a times omega times c times cos omega t that is equal to I and because I is limited, the product of a and omega is limited. As omega becomes higher and higher, the maximum amplitude that I can reproduce at the output becomes lower and lower. Therefore, at high frequencies, because of the same slew rate limitation, I am not able to go to the full amplitude and therefore, if I give too high an input, which would have required a higher than possible output, then I will not be able to reproduce and I will get distortion. So, this tells you a somewhat brief and gives you a somewhat brief answer of what is slew rate limitation, where it comes from and why it causes distortion at high frequency. Over. Thank you, sir. We are taking questions from Jay Chammaraj Indra College, Karnataka. Good afternoon, sir. Can you please explain the operation of a current mirror circuit in detail? I am not sure how much time we have to go into great detail, but I will explain absolutely the basic principles. Again, explaining it is easier for an MOS. The bipolar case is quite similar. If you recall, these are the characteristics. Whether it is a bipolar or MOS, the characteristics look very much like this. In this region, the current is determined only by the base current or the gate voltage depending on which device you are using and not on the drain voltage. Therefore, we can use it as a current source. So, the operative point is that the current is determined by the voltage or current at the input and not at the drain or collector voltage. So, it is uniquely determined by, let us say, the gate voltage in case of an MOS. Now, consider this circuit. This is a current mirror and you could be drawing some current from here, let us say, by putting a resistor here. Now, the current that is drawn here, this saturation current is given by k by 2 into v g minus v t whole square. It is because it is not a function of v d that it is determined only by v g and is insensitive to changes in the drain voltage here. However, in this particular case, on the left hand side case, it is also connected to the gate. So, the same voltage is v d and v g. Therefore, this guy is not a current source. However, this one is a current source and how much current will flow here? Well, this transistor is also saturated. So, let us first calculate v g from this v g equal to 2 i by k 2 i divided by k square root plus v t. So, this is the value from here. Root 2 i by k of this transistor plus v t is the voltage at this point. Now, analyze the circuit to the right of this. This transistor is also saturated. Therefore, its current is given by this formula, which is k by 2 into root 2 i by k plus v t that is the value of v g minus v t whole square. v t cancels. The square root will go when I square it and what I get is k by 2 into 2 i by k, which is equal to i. As a result, this transistor will provide exactly the same amount of current that this transistor is drawing. Hence, it is called a current mirror. Whatever is the current through this side circuit, the same current will flow through this and this will be independent of this drain voltage as long as I remain in this region, because now the current is determined only by the gate voltage and not by the drain voltage. So, this is the basic principle of current mirrors. In case of bipolar transistors, the same thing applies except that the relationship is exponential and logarithmic rather than square and square root over. Thank you, sir. And the explanation was simply superb, sir. Thank you.