 Hello and welcome to this presentation of the STM32C0 power controller. The STM32C0's power management functions and low power modes are also covered in this presentation. STM32C0 devices feature a power control unit designed to increase flexibility in power mode management and further reduce the overall application consumption. Run mode can support a system clock running at up to 48 MHz with only 58 microamps per MHz. STM32C0 devices support 5 main power modes, run, sleep, stop, standby and shutdown modes. The high flexibility in power management provides both high performance with a core mark score equal to 125 at 48 MHz together with an outstanding power efficiency. The STM32C0 has several key features related to power management. Several low power modes, down to 19 nanoamps while it's still possible to wake up the MCU with an event on an I.O. A large number of peripherals can wake up from the various low power modes. Dynamic consumption is down to 58 microamps per MHz executing from flash memory. And thanks to the large number of power modes, STM32C0 devices offer a high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance and needed wake up sources. STM32C0 main power supply is VDD, VDDA PIN, supplying all I.Os, the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry which includes the wake up logic and independent watchdog. VDD supplies voltage regulators which provide the V-core supply. V-core supplies most of the digital peripherals SRAM and FLUSH controller. VDDA voltage is the same as the VDD1 and supplies the analog peripheral. The VRF plus pin provides the reference voltage to the analog to digital converter and can be used as an external buffer reference for the application. Note that the flash is connected to two power rails, VDD for the memory and V-core for the controller. The main power supply VDD ensures full feature operation in all power modes from 2 up to 3.6V. Device functionality is guaranteed down to 2V, the minimum voltage after which a power down reset is generated. The analog power supply VDDA is always connected to VDD. VRF plus is the analog peripheral input reference voltage. VRF plus must be between 2V and VDDA. It can be grounded when the analog peripherals using VRF plus are not active. On packages without VRF plus pin, VRF plus is internally connected with VDD. The power supply supervisor guarantees a safe and ultra low power reset management. STM32C0 devices embed a power on reset or poor and a power down reset or PDR, which are always enabled in all power modes except shutdown mode. The brownout reset or bore ensures reset generation as soon as the microcontroller power supply drops below the selected threshold, regardless of the VDD slope. Full thresholds from 2.0 to 2.95V can be selected by option byte programmed in flash memory independently from rising and falling edge. It can also be disabled to save power consumption. The power resets bore and poor reset all registers. When exiting standby mode, all registers powered by the main regulator are reset. When exiting shutdown mode, a power reset is generated. When the bore is enabled, four bore levels can be selected through option bytes with independent configuration for rising and falling thresholds. In run mode, the CPU is clocked and the program can be executed from flash or SRAM memory. The power consumption in run mode can be reduced through selecting a system clock with lower frequency, scaling down the system clock frequency, disabling unused peripherals and or stopping their clocks. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripherals clocks are off except the flash interface clock. The SRAM clocks are always on in run mode. By default, the device is in run mode after system or power reset. The current consumption in run mode depends on several parameters. First, the executed binary code, which means the program itself plus the compiler impact. Then it depends on the program location in the memory, the device software configuration, the IOP loading and switching rate, the temperature and the memory from which instructions are fetched, flash or SRAM. When code is executed from flash, the energy efficiency is better when the flash accelerator is enabled because instruction cache and prefetch buffer are based on SRAM memory. Sleep allows all peripherals to be used and features the fastest wake-up time. In these modes, the CPU is stopped and each peripheral clock can be configured by software to be gated on or off. This mode is entered by executing the assembler instruction, wait for interrupt or wait for event. Depending on the sleep on exit bit configuration in the Cortex-M0 plus system control register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt service routine. This last configuration allows to save time and consumption by saving the need to pop and push the stack when exiting the low power mode. However, all computations must be done in Cortex-M0 plus handler mode because the threat mode is no longer used. In sleep mode, the CPU clock is off. The frequency of the system clock is up to 48 MHz. By default, the SRAM clock is enabled. It can be gated off during sleep mode by software. The sleep mode consumption is 17 microamps per MHz with the flash memory on. Note that the flash memory can be powered down in sleep mode when the FDPS LP bit is set to 1 prior to entering sleep mode. Stop mode is the lowest power mode with full retention and only a 2.5 microseconds wake-up time to run mode at 12 MHz. The contents of SRAM and all peripheral registers are preserved in stop mode. All high-speed clocks are stopped. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake-up from stop mode. System clock on wake-up is the internal high-speed oscillator at 12 MHz with only a 2.5 microseconds wake-up time from SRAM or 5.9 microseconds from flash, the divider configuration to CIS-CLK is kept upon wake-up. All clocks in the V-core domain are stopped. The HSI-48 and the HAC oscillators are disabled. The RTC clocked by the internal or external low-speed oscillator remains active. The brownout reset is always enabled. Most of the peripheral clocks are gated off. Several peripherals can be functional in stop mode. Usart 1 and 2, I2C1, independent watchdog. The events from all IOs can wake up from stop mode as well as the interrupt generated by the active peripherals. The I2C1 and Usart 1 and 2 can switch the HSI-48 on during the stop mode in order to recognize their wake-up condition and switch off the HSI-48 after receiving the frame if it's not a wake-up frame. In this case, the HSI-48 clock is propagated only to the peripheral requesting it. The stop mode consumption typical at 3 volts is 80 microamps when HSI is disabled, 605 microamps when HSI-48 is enabled. The standby mode is the lowest power mode in which context information can be retained in 4 PWR backup registers. The voltage regulators are in power-down mode and the SRAM and the peripheral registers are lost. The ultra-low power brownout reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull-up or pull-down which is applied and released thanks to the APC control bit. This allows to control the input state of external components even during standby mode. Five wake-up pins are available to wake up the device from standby mode. The polarity of each of the five wake-up pins is configurable. The wake-up clock is HSI-48 divided by 4, so a frequency of 12 MHz. In standby mode, the voltage regulator is powered down. The RTC clocked by the internal or external low-speed oscillator may remain active. The brownout reset can be enabled. The independent watchdog can also be enabled in standby mode. The red, brownout or power-down reset, independent watchdog and any event on the five wake-up pins can exit the microcontroller from standby mode. The consumption in standby mode without the RTC is 7.45 microamperes typical at 3V. The shutdown mode is the lowest power mode with only 19 NAH at 3V. This mode is similar to standby mode, but without any power monitoring, the brownout reset is disabled. Hence, the microcontroller state is not guaranteed in case the power supply is lowered below 2 volts. The LSI is not available, and consequently neither is the independent watchdog. A brownout reset is generated when the device exits shutdown mode. All registers are reset and a reset signal is generated on the pad. The wake-up sources are the five wake-up pins. When exiting shutdown mode, the wake-up clock is HSI 48 divided by 4, so 12 MHz. In shutdown mode, the voltage regulator is powered down. The brownout reset is deactivated. The wake-up events are the reset input and the five wake-up pins. Here's a summary of all the STM32C0 power modes. The device can transition from run mode to any of the low power modes and from any low power operating mode to run mode. Transiting from one low power mode to another isn't possible. Three bits are available in the flash option bytes to prohibit a given low power mode. When cleared, an option bit configures reset generation when entering shutdown mode. Another bit configures reset generation when entering standby mode. And the last bit configures reset generation when entering stop modes. The microcontroller integrates special means to allow the user to debug software in low power modes. By default, stop, standby and shutdown low power modes deactivate FCLK and HCLK, which prevents debug capability. In sleep mode, however, the device keeps FCLK and HCLK always active. To keep FCLK or HCLK clocks active and preserve debug capability in stop, standby and shutdown modes, the debugger host must set, before entering one of these low power modes, the DBG stop bit for stop or DBG standby bit for standby and shutdown of the DBGCR register. When the related bit is set, the regulator is kept on in standby and shutdown modes, and the HCLK and FCLK clocks are provided by an internal RC oscillator. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the microcontroller isn't under debug because the consumption is increased in low power modes. To complement this presentation, you can refer to the following presentations, reset and clock control, internet management, peripherals with wake up from stop capability. The table in this slide compares the features of STM32C0 and STM32G0 in terms of power control. The STM32C0 supports a unique stop mode, while the STM32G0 supports two stop modes. The STM32C0 ensures the retention of only the backup registers in standby mode, while the STM32G0 also ensures the retention of the SRAM. VBAT mode is not supported by STM32C0. Sampling mode for BOR and PDR is not supported by STM32C0. In stop 0 and 1 and standby mode, BOR and PDR can be periodically activated in STM32G0 to decrease power consumption. Thank you for attending this presentation.