 So, welcome to the second lecture of digital system design with PLDs and FPGAs. In the last lecture I talked about the contents of the course, the course objective what are the competencies I hope you will develop at the end of the course, reference book and some the mode of giving the exercises during the lectures, all that was covered in the course objectives and contents. Then I started an overview of the field or revision and overview of the field. So, quickly we will recapture the overview we have done the last lecture then continue with the this revision and the overview. So let us move on I said in learning you learn always bottom up that means from the smallest building block to the complete system you go hierarchically that like a transistor gate combinational sequential and the system. But while designing you go top down like you take a processor break into pieces take each piece and make it into further pieces and go all the way to the gates and the transistors. So, when you design you should remember that this is the hierarchy we use but while learning the opposite is the thing. We have run through some example like you start with transistors, construction characteristics, example then you make gates out of the transistor various gates it is input output characteristics. Then you build further useful circuits like full adder using XOR gate and gate and OR gate by writing it is truth table minimizing it and implementing it and so on. At the next level we use this as a building block to build even bigger you know multi bit adder in this case a 4 bit ripple adder made of 4 full adders. Then having known this then we can go to the next level of building with these building blocks the combinational and sequential building blocks a multiplier with multiplicand accumulator multiplier with adder and so on. But in the case of design we do the opposite having known the multiplication algorithm we design an architecture with higher level sequential and combinational components. Then each block is designed separately in this case I am illustrating one of the block design. So, you take the adder then that is shown as a 4 bit ripple adder in that it is made of 4 full adders and full adder is taken that is designed. And then this is taken the gates are designed in terms of transistors and so on like when you design a chip even this you have to go further you know you have to make the transistor layout in the chip and mask and so on. But our interest in this course is up to here when we come to this point the front end design is over that we convert the spec or the algorithm into gate and flip flop level circuit. So, that is the front end design that is the focus of the course so let us move forward and as I said when you design the major constituent of the design the first foremost important thing is the function. And you have learnt all the building blocks in your undergraduate curriculum where is a combinational circuit to all these blocks like you know engoder, multiplexer, arithmetic circuit and so on. Then comes to flip flops so you have flip flops, registers, memory all these need to be thoroughly learnt what is the architecture of this, what is the function of that, what is the input output characteristics and so on. This should be thorough so that we can build higher level system using these blocks. And I talked briefly about the minimization so you would have learnt most of the time this graphical tool called Karnoff maps, the computer algorithm equivalent to that is a coin maklowski which is very complex because it starts with the minterm. So, there are faster methods like espresso which is heuristic which does not necessarily produce a minimal solution but very near minimal solution. But the computation time is very negligible or compared to the coin maklowski so this is what is used in real life synthesis tools use this minimization algorithm. So, in power mostly you are used to kind of two level implementation but in again in real life circuits we will have multiple stages of combinational circuits and there could be multiple outputs. So when you minimize a multiple output scenario you have to find the common sub-expression among the outputs to be able to share the resources. So, that is one step in multi-level multi-output minimization so these are the kind of steps which helps us in multi-level multi-output minimization like factoring, substitution, flattening. But as I said this is not our focus those are interested can look at the latest minimization algorithm in digital synthesis. So let us move on and this is where we have kind of stopped last time so I would like you to make a little differentiation between the gates and the function okay. So you take an AND gate depending on the active levels of the signal it can do other functions so take this truth table and assume that a, b that the inputs and the output are active high. So you look at it that means that when both the inputs are active output is active otherwise output is not active. So it means or if you want to the conventional terminology if both inputs are true then the output is true. So the AND gate when all the signals are active high implements an AND function but look at this same truth table and assume that we are treating a, b, y as active low that means you look at the truth table when any one of the input is active the output is active that means when we treat the inputs and outputs are active low the AND gate implements an OR function. So that is what is shown here the same AND gate but the function is OR and the bubble indicates the active level. So in essence AND gate can implement AND function or OR function and for clever student you can easily make out this is exactly bringing the De Morgan's theorem into our concept. So here it is y is a and b so if you take the y bar so I use slash for the bar because it is easy to type in text y bar is nothing but ab bar which is nothing but a bar or b bar. So essentially what we are doing is bringing this De Morgan theorem into our conceptual level so that when you work out simple circuit it is very easy that you do not waste gates. So let us take another example let us go and look at the NAND gate. So AND gate can do AND and OR function depending on the active level of the inputs and outputs. So let us take the NAND gate and you look at this we will treat the inputs are active y and the output is active low. Then you see when both the inputs are active the output is active or when both the inputs are true the output is true that means it is implementing an AND function. And look at the opposite like when we treat the inputs are active low a and b as active low and y as active. Then you look if any one of the input is active the output is active otherwise it is not active. So this implements an OR function so that is shown as that OR symbol with the bubbles for the active low input. So when you see this symbol it is essentially doing an OR function of the active low a and b but essentially the gate involved is a NAND gate okay that is the idea NAND gate has one more property. So that let us move to the next slide. So look at this when both the inputs are active low output is active y or when both the inputs are false the output is true when both the inputs are true the output is false. It shows that if you tie it together so you tie a and b together like this and you have a single input then if input is 0 the output is 1 input is 1 output is 0. So this NAND gate can act as an invert it can implement an invert function or act as an inverter. So NAND is called a universal gate it can implement AND function OR function AND invert function. So in conclusion if you take NAND gate and OR gate these are universal gates depending on the active levels of the signal it can implement AND OR or invert but both AND gate and OR gate can implement both AND function and OR function. So this is making a difference between the gates and the function and also we are essentially we are bringing in the De Morgan's theorem into the concept. So let us move on so an example of this which you often do is that you have an AND or implementation say 2 AND gates feeding an OR gate. So let us put a bubble here that means inverted and to compensate for this inversion or a bubbling we will put another bubble at the input here similarly put a bubble here and bubble here so that it is equivalent these 2 circuits are equivalent. But moment you put that you know that this is a NAND gate which is doing an AND function and this is also a NAND gate which is doing an OR function okay. So you essentially convert an AND OR into a NAND AND by applying this concept you do not have to do a De Morgan's theorem very simple conceptual way you can convert this AND OR into a NAND NAND kind of representation that is why the beauty of differentiating the functions and gates. So let us move so again an application is shown here suppose you have an Boolean equation like A bar or B bar and C bar then if you take it in a very naive way without kind of trying to minimize it then you will put 3 inverters A bar B bar C bar put an OR gate and then everything will be this output and input is ANDed to get. So you end up with say 5 gates but if you apply this the method we have discussed then we put these are come as bubbles. So here is a bubble and we have one bubble here so to compensate like here for this inverter to make it symmetric we put a bubble here and bubble here. So immediately you know that this is nothing but a AND gate and this is nothing but a NOR gate. So you end up with 2 gates instead of 5 gates so though we are not going to do any kind of gate level implementation but for small circuit very quickly you can work out sometime it is useful you have a little glue logic very simple logic you can quickly write a VHDL code by converting like this not that the tool can handle it but then sometime in simple cases you can work out at least the concept wise what you have learnt it reinforces. So that is why I discussed this let us look at one or two other combinational components take an encoder you would have studied an encoder let us take the example of a binary encoder. So here in the binary encoder in this encoder you have 8 distinct input at a time any one of the input can be active high. So we code the output as a equivalent binary number that means if this is active this will be 000 if I1 is active 001 I7 is active 111 like that. So it is an 8 input to 3 output 3 binary output encoder and you can imagine that the internal circuit is nothing but OR gate suppose I7 is 1 then there will be 3 OR gates and I7 will go to the input of all OR gates so that you get a 11. So encoder essentially uses an OR gates and when your priority suppose there is a situation that more than one of this can be active at any time then we have to kind of give priority to one of them because we assume that only one will be active at any time. In that case there will be AND gates of you know coming here the top so that when the I0 is active it should mask the I1 out so there will be the invert of I0 will be going to mask it the I1 and when it comes to I2 invert of I0 and I1 will be going and masking the I2 and so on. So the last gate will have a huge AND gate with which mask with all the compliment of all these inputs you have studied priority encoder. So this is what is encoder about and one property of the encoder is that the number of bits in output will be less than the number of bits in input. So this is what is encoder and basically it is nothing but the OR gate equal to the number of outputs in case of simple encoder. Let us look at the decoder I am showing an example of a binary decoder. So here we have three binary inputs that means it can go from 000 to 1111 so that means 0 to 7 and we have distinct 8 outputs. Suppose the number here is 101 then O5 will be active so if the number is 5 fifth output will be active okay. So this basically uses AND gate that means we will put an AND gate suppose number is 101 here put an AND gate here this one goes directly one goes directly this goes through an inverter or a bubble to the AND gate. So for 5 only this AND gate is active and that goes to O5. So you can imagine there will be 8 AND gates with 3 inputs each with the decoding all the min terms. So that is a decoder in a general decoder the number of bits in the input will be less than the number of bits in the output. So normally in digital design in high level design we will be using there will be need to use the decoders may not be much of encoder but we will be definitely using more decoders than encoders but depending on the need there could be use of encoders also. So let us move on this is one case the tri-state gate which is cause often quite a lot of confusion. So this shows a tri-state inverter so where it is like normal inverter when this enable is high. So if enable is high then A is 1, Y is 0, A is 0, Y is 1 but when enable is 0 then we say Y is tri-stated and most people do not know what is or we say high impedance and it is indicated by the symbol Z. So to understand what is high impedance and if I ask a student what is the high impedance many people are not very clear. So let us look at the implementation of this tri-state inverter. So it is like a usual normal inverter like PMOS on top and NMOS on at the bottom but in between you can see one more NMOS and one more PMOS it is introduced. When enable is active this transistor and this transistor will be on so that when A is 1 this path is active pulling the Y to 0 when A is 0 this path is active pulling the Y to the VDD making it 1 okay. So what happens if this enable is off in an inverter case either this path is active or this path is active but when enable is active you can see that this is cut off and this is cut off. So this particular point this output has a very high impedance path to the VDD or ground. That means you can say if the resistances are equal maybe as a 10 meg to here, 10 meg to here and if the supply is a 5 volt then this will be floating at 2.5 volt. Any coupling any small signal coupling can pull it to the 1 or 0 that is why this is called high impedance and this is used for multiplexing and busing and all that. Let us see the scenario here. So here I show say multiple tri-state inverters are tied together to form a bus. The idea is that only at any time only one of the output drives this output. So all others will be cut off and if both are 2 more than any one of them is on then there will be a clash here that means it can be 1 and if this is 0 then there is a problem. So one is active like that and the 0 so there will be a short circuit from the VDD to the ground. So that should be avoided but there is a problem if all are cut off then this input will be this output will be kind of in between and if this bus is connected to some input then this will be floating and any small noise can make it switch go up and down and there will be lot of power wastage in this. Maybe in the circuit design this is taken care this is ignored when everything is cut off but still there will be lot of power dissipation due to switching. So when you tri-state a bus normally either you pull it up or pull it down through a higher assistance so that when everything is cut off it is safely kind of 1 or 0 a weak 1 or 0 is there. So either you pull it up to VDD through a higher assistance or pull it down to the ground using a higher assistance. So that is about the tri-state gate so please remember this tri-state gate as 3 state at the output 1 is 0 then the next one is 1 and the high impedance means output is floating and if you are driving any input it should be pulled up or pulled down and it is a very bad strategy to keep any output at high impedance to mean inactive state. Many a time students write VHDL code if enable is if some condition is not met the output is tri-stated it is a dangerous thing to do if you are not sure what you are doing that means that output will be in between some state and that is driving some input and it can produce incorrect logic levels at the output of those circuits which it is driving. So you have to treat tri-state gate tri-state gate should be used only when you are multiplexing or you are busing otherwise it should not be used it is not an inactive state like 0 or something like that. So just like that you should not put Z in coding when you are coding the digital circuit. So let us move on to the next combinational circuit you would have learnt that is multiplexer. So the multiplexer you know that multiplexers the input. So in this case I am showing a 4 to 1 multiplexer. So 4 to 1 multiplexer will have a 2 bit select line when the select line is 0 A goes to Y when select line is 1 B then 2 is C and 3 is D. This can be like 1 bit or multiple bits it does not matter and you know that internally it is nothing but AND or gates and the select line will enable particular AND gate. So in the case of 4 to 1 marks I have written here for 1 bit case there are 4 AND gates corresponding to 4 inputs and each AND gate has this particular 1 bit input and the select line going to enable this is the minterm decoding of the select line like here the select 1 and select 0 will go with the bubble. Here select 1 and select 0 will go directly so that when it is 1 1 this path is selected and there is an OR gate here which combines the output of all the 4 AND gates. So in general if you have a 2 raise to N to 1 multiplexer then you have at the input 2 raise to N AND gates with each AND gate is a 1 plus N inputs that is a logarithm of the number of inputs ok to the base 2 1 plus N inputs and an OR gate of 2 raise to N input to combine all the 2 raise to N output of the AND gate. So that is a multiplexer let us move on to the demultiplexer it is opposite of demultiplexer. So you have 1 input depending on the select line it puts it to any one of the 4 outputs. So if the select line is 0 it goes here if it is 2 it goes here and so on and basically it is an AND gate you know that there is an AND gate in this case there are 4 AND gates at the output and this A goes to all the AND gates as 1 bit in the 1 bit case and the select line goes to all the AND gates with the proper decoding like here select 1 bar and select 0 bar here select 1 and select 0. So for a 1 to 4 D marks there will be 4 AND gates a 1 plus 2 input for 1 to 2 raise to N 1 D marks you have 2 raise to N AND gates each AND gate as 1 plus N inputs so that should be kept in mind. So a multiplexer is AND OR gates and the demultiplexer is nothing but the AND gates. So and this is one picture that you see in a textbook normally the application of the multiplexer and demultiplexer is shown like that. There is a 4 to 1 multiplexer with multiplexers with the select line and at the other end it is demultiplex with the same kind of select line okay. So it is a textbook conceptual picture and many a time some kind of a rotary kind of arrangement is shown but in real life in real system this need not be very symmetric that means symmetric I mean that at 1 and it may be 4 to 1 multiplexer at the other end it may be 1 to 3 demultiplexer. Second thing is that it need not be ordered like it is not that A goes to A it need not be like that maybe A and B will go to B here and C go to A and so on. It need not be very much ordered and the best thing you can go and see some serious digital logic design you will not see any symbol of a demultiplexer okay. You won't see any explicit demultiplexer in the circuit okay. So you can think over it please think over why that happens okay. It is not that the demultiplexing is not happening it is happening but you won't see a combinational circuit which is acting as a demultiplexer. So you can mull over it you can come out with the answer maybe you can communicate with me or find the answer yourself. So that is about the multiplexer and demultiplexer. Let us move on let us so that is the kind of a quick overview of some of the components of the combinational circuit. So I have told you about the gates and the function. So as I said an AND gate can do AND or OR function and AND gate can do AND OR or invert function similarly in OR gate. So they are universal gate and essentially we are building the De Morgan's theorem into our concept. And second thing I have told you is about the tri-state gate. What is the tri-state high impedance and the care need to be taken while using the tri-state gate or what are the application of tri-state gate. And the next thing I talked about is encoder and decoder. Encoder what is the structure of encoder what is the structure of decoder. Then we looked at the multiplexer and demultiplexer what is multiplexer and what is demultiplexer. And the real life circuit is not like textbook picture you may not see a demultiplexer symbol and as I said you please think over and come out with an answer why there is may not be a combinational demultiplexer you know explicitly the symbol is not there in the real circuit. So let us look at the flip-flops and latches so this is important so this shows a latch a transparent latch it has an input D and the output Q and there is a clock and the operation of that the latch is that when the clock is active when the clock is high so I am sorry for this picture these are lines this is the real waveform and these are the lines which shows the edges. So do not confuse and these are the kind of lines dotted lines to show the clock edges to match it these are the waveforms. So you see when the clock is high the Q of the latch follows the input okay so when the clock is high you can see the Q is exactly same as the D but when the clock goes low whatever was input is latched and so it remains. So you can see here in the QL next time when the clock comes that clock goes active it again produces the D but when the clock goes low here it remembers the last state till the clock becomes active. So it remains one though the input has gone low here it remembers whatever is during this period and then it samples and it allows the input to come to the output and when again when the clock is active you can see that before the clock is active it is going high but that does not come to the output when clock goes high then you get the output and when clock goes low it is latched okay. So that is the behaviour of the latch when the clock is high it is transparent clock goes low it remembers till the next active clock comes but in the case of flip flop this is edge triggered that means whenever a clock edge comes whatever is the input is transferred to the output with some timing constraints which we will see later. So here you can see the behaviour of it and this triangle represent the edge triggering action. So this is a positive edge triggered flip flop so you can see that when the positive edge comes and this is the flip flop output the input is same. So when the positive edge comes the input is 0 so the output is 0 and it remembers till the next clock edge. So here also the input is 0 the output is 0 and the next clock edge input is 0 the output is 0 and here you can see that input is going high but is not reflected but when the active clock edge comes that is transferred to the output and it remembers okay till the next clock edge though it is gone low it retains till the next active clock edge and the next active clock edge it captures this 0 and it becomes 0. So in the case of the flip flop you get output in synchronous with the clock edge you can see the one is going high the output is going high at this clock edge and it remains there till the clock edge not so in the case of the latch because when the clock is active whatever is the input changes will be reflected in the output. So there is a difference between the latch and the flip flop and most cases we will be using the edge triggered flip flop in the design. There are special cases where the latch can be used in advanced cases we may not see those cases in this course but we will stick with the use of flip flop in this course. So let us move on so that is the sequential part we have seen in our view of the combinational circuit now we have seen the sequential circuit what is the difference between latch and the flip flop and the flip flop is edge triggered it can be positive edge triggered or negative edge triggered and it is synchronous with the clock edge and so that is the one important part of the digital design the function or the logic. And we have seen some basic sequential circuit and the combinational circuit you have learned and this is very useful so keep in mind there are other parts which I am not touching upon I hope you revise and understand that and let us move on to the next important requirement. So that is nothing but the timing ok once you have tackled the function once a circuit is working then the next important thing is the timing and now we will look at the timing for the basic timing parameter for a combinational circuit and a flip flop from there we can build the more complex timing details of the digital circuit. So let us turn to our slide so for combinational circuit essentially say like a take an AND gate essentially it is a propagation delay that means if one of the input changes how much time it takes for the input that change to propagate to the output ok. So from A to Q how much it takes that is the TPD or propagation delay. Now there is a difference TPD is divided into two sections or two parts one is TP LH and TP HL ok. So this is the propagation delay TP LH is the propagation delay when the output switches from low to high and TP HL is when the output switches from high to low. So this will be different because you see the circuit is not symmetric CMOS circuit is made of PMOS and the NMOS circuit and depending on the input signal may be PMOS is on may be the NMOS is on you can see here the NMOS is in series PMOS is in parallel and so depending on how the output switches whether it is going from low to high or high to low some part of the circuit is switched and some NMOS is involved some PMOS is involved you know that the mobility of electrons and holes are different may be the sizes of these transistors depending on the design is different. So that all makes a difference in the propagation delay so normally in a combinational circuit you need to specify the propagation delay from each input to each output. So most of the time manufacturers will specify in the symmetrical case the worst case delay that means from if you have 10 inputs to 10 outputs that they will specify what is the worst case input output delay which is TP LH and TP HL. But in if there is a large variation it is worthwhile to specify the slowest input and the fastest input so that we can maybe take that into account and come out with some clever design to take advantage of it. So let us move on to the flip flop so in the case of H-triggered flip flop there are some important timing parameters so here it is not that when the clock comes whatever is at the input is immediately transferred to the output. When the clock comes first thing to notice is that for the input here when the clock comes the input is 1 for the output to become 1 it takes some time that is called TCO or the propagation delay for input to appear at the output from active clock edge ok. So that is called TCO clock to output or sometime it is called TCQ which is clock to Q that means not that the data is going from the clock to Q but the enabling path is from the clock. So that is why it is called clock to Q the input goes to the Q but for this to happen for the input to come to the output the input itself should mean some timing requirement with respect to the clock edge ok. So that means if the input has to go to the output when the clock comes the input has to be there at this point sometime before the clock edge that means that time is called setup time. So input should be setup sometime before the clock edge not only that after the clock edge it should remain there for some time then only properly the input will be transferred to the output if this is not met we cannot guarantee what is the state of the output it could become 1 or it could become 0 in the worst case it can even get stuck in between ok which probably you would not have studied again in this course I do not have time to deal with I mean the concept related to that. But I will at least tell you how to handle that such situation we will study in synchronization how to handle it this scenario but essentially in flip flop there is a setup time that means the input has to come sometime before the clock it has to remain there sometime after the clock that is called hold time you hold the input after the clock edge for sometime and if that is met with a TC or TCQ delay the output appears at the I mean the input appears at the output with that delay and this is the basic timing parameter of a flip flop. So knowing this that is basically the combinational delay which is TPD propagation delay which is TPLH and TPHL and this the TCQ in the case of flip flop and setup and hold time we can build all other timings whichever is required for the sequential circuit from this basic timing the next level we can build on this understanding. So if you have not learnt this part of the timing please learn it now let us move on. So I want to show an example some kind of application of the timing let us look at take this circuit you have an AND gate with a fine annus can delay input one of the input is coming directly to one of the inputs of the AND gate. The other input of the AND gate goes through 3 inverters each a fine annus can delay. So this point is called A this is intermediate point is called B and the output is Y. So assume that the A is changing at 15 annus second from 0 to 1 okay before that we assume it is 1. So if you do a static analysis of this circuit what happens is that typically you learn in the undergraduate this is 0 that means this is 1 because of the odd number of inverter this is 1 and this is 0 1 and 0 is 0 if this becomes 1 this input is 1 this is 0 again the output is 0. So we are expecting you know a constant static 0 at the output but you see because of this 15 nanosecond delay for B to change from say 1 to 0 something interesting can happen let us look at what is a B when A goes from 0 to 1. So B will change from 1 to I mean 1 to 0 like this after 15 nanosecond. So at 65 nanosecond B goes from 1 to 0 but you know that A is directly connected here so A changes here from 0 to 1. So for 15 nanosecond time both A and B are 1 here and so that pulse will come at the output as a 1 with a delay of 5 nanosecond so the output Y look like this. So you get a pulse of 15 nanosecond duration which was not intended like we were not like after all 0 and 1 in an AND gate is 0 but we get something called a pulse and many a times it is called a glitch and I do not know whether you have studied this is called a static 0 hazard. So whenever you have an AND gate this static 0 hazard can happen now you can imagine an opposite of that a static 1 hazard. So if you have for that you have to have an OR gate here and similar setup but instead of A going from 0 to 1 A has to go from 1 to 0 ok. So here an OR gate input of the OR gate has a same structure same circuit and the A moves from 1 to 0 then you are normally expecting a constant static 1 but you will get a 0 glitch or a 0 pulse. So this is called static 1 hazard and you must have studied some ways of eliminating this static hazard and things like that using adding some redundant terms product terms and all so on. But the important thing is that why are we studying this because nobody will cook up a circuit like this everybody knows that 0 1 is 0 or in the case of an OR gate 0 1 is 1. So there is no need of cooking up a circuit like this only thing is that the only use for this circuit is that if you want a pulse out of an edge then you can use this circuit and definitely we will be using this kind of structure as we proceed for precisely for same application. You have an edge which is going like something is going from 0 to 1 for a long time but we want to convert into a pulse you can use it. But other than that why are we studying this hazard is that it is just a model okay in real life this can happen in very kind of very nice way which you may not detect. So let us move on to the real life case you take an AND gate with 3 inputs which is coming from some circuit through some IS in a chip and assume that B is C is permanently 1 at some time instance B is going from 0 to 1 and A is going from 1 to 0. Now C is 1 B goes from 0 to 1 initially it was 0 and A goes from 1 to 0 and there is some delay here some logic is there here and maybe it is a wire delay. So the A does not go from 1 to 0 immediately it stay there for some time so you get a glitch here. So whenever there is an AND gate and the input does not arrive at the same time or there is an unbalanced path delay you will get the glitches at the output okay. Similarly whenever you have an OR gate with unbalanced path delay you will get glitches okay. So that is the first thing to understand most of the time in your basic course you have taken everything as static that you apply some kind of set of inputs then you get some active high or low for a particular input but it is not going to be like that the outputs are going to glitch and will settle to some value. So this is quite normal you need not be worried about it in a moment I will tell you how to handle that. So you will see lot of glitches in combination circuit lot of switching before getting the correct output is not a problem at all but the main thing is that one side effect of that is that if there are lot of switching then there will be lot of power dissipation because the power dissipation is proportional to the switching. So if there is unnecessary switching so if the it will be good from a power dissipation point of view if we can balance delay then the power dissipation in this gate will be less. So that is about the hazard and in this case we have seen that in this one and there is one glitch so but you can imagine a situation where input changes one once and there could be multiple glitches at the output and that can happen in a multi-level circuit say take the case of an AND gate with a static hazard case which gives a 010 glitch but you see there is an OR gate following which gets this 1 to 0 transition before the 010. So I am showing A here this particular x, x is not marked I am sorry so this is x, x is shown here so the y is shown here this glitch but you know that this 1 to 0 comes before that and both combine you will get a 1010 2 glitches at the output okay. So it is supposed to transit from 1 to 0 but it goes to 0 then goes to 1 and then goes to 0. But it is quite normal in the case of combinational circuit and you can imagine if there is this is followed with another level of the circuit it might glitch 3 times depending on the logic. So that should be kept in mind but normally in sequential circuit what we do is that we will have a flip-flop here when everything settles we will give enough time for all these things to settle then we will latch the correct output to that flip-flop. So in a sequential circuit we are not worried about the glitches only thing is that when you simulate circuit you will see lot of glitches you need not worry this is quite normal so that is about the hazard. So let us move on so that is the second factor we have talked about after the functional aspect I have you know talked about the timing and delay parameter for the combinational circuit is propagation delay and there are two parts one is TP LH and TP HL that means the propagation delay when the output switches from I to low or output switches from low to high because the circuit is not symmetric not all the all the transistors are switching at the same time and some are PMOS some are NMOS. So this makes a difference when a particular output switches from low to high and depending on the number of inputs from each input to each output the delays will be different. But the manufacturers often specify the worst case delays or if there is variation it can be large variation the fastest and the slowest can be specified. We have seen the timing parameters of a flip-flop the setup time whole time the input has to setup some time before the clock edge input has to be there for some time after the clock edge. And if that happens with a propagation delay TCO the input appears at the output properly if it does not happen then the output is not we cannot say what will be the output it could be 0 it could be 1 it could get suck in between. Then we have seen hazard static 1 hazard static 0 hazard it is useful because in real life because of the unbalanced path delay AND gate and OR gate can produce glitches which is normal and it can be dynamic hazard multiple glitches. But normally we put in sequential circuit a flip-flop at the output when everything we give enough time when everything settles the settle value is latched on to the flip-flop. So the next we will move on the next important constituent is the electrical characteristics okay and these are the voltages currents and the power dissipation. And again in your basic course you have studied this voltage levels VoH, VoL, IOH and IOL VoH is output voltage when the output is high VoL is output voltage when the output is low, IOH is output current which is flowing out when the output is high, IOL is output current which is flowing inside when the output is 0. So that is the output voltages or output voltages and currents input voltage is V IH that is the voltage which the circuit considered as a high voltage or a 1. Similarly this is the VIL is the voltage which is considered as a 0, IAH is the input current flowing in when the input is high and IIL is the input current which is flowing out when the input is low and things like that. To understand we should look at the output stage of any gate all the gates output stage will look like this there will be an PMOS transistor here and NMOS transistor here any one of them will be on if the output is 1 this PMOS is on and NMOS is off output is 0 the NMOS is on and the PMOS is off okay. So when the output is high this IOH current flows and charge the output capacitance, output capacitance means all the capacitance if there are lot of inputs connected everything lump together as a lump capacitance it is showing. Similarly IOL is when the output is 0 this capacitor discharge through this particular transistor. Now you can see that if the VOH is nothing but the VDD minus the IOH into the on resistance of this transistor. So it is VOH is nothing but VDD minus IOH and R on. So as the current increases this comes down. So if the current is increasing because of the dissipation across this transistor increases the voltage here goes down. So but then you know that there is a danger that it should not go below some voltage because then if an input is connected here it should recognize it as high voltage. So there is a limit below which it should not go. So the manufacturers will make sure that at the maximum current specified they will say that it will not go below a particular minimum value. So that the inputs can recognize it as high. So opposite case is when the output is low the VOH is nothing but the IOH into R on resistance of this transistor. So VOH is IOH into R on. Now you know that if the IOH goes up the VOH goes up. So when the IOH is going up the VOH will move up. Again it is important that this should not exceed the maximum limit of the VIL. So the manufacturers say for the maximum current specified it does not exceed some fixed value not only that it is not that there has to be some gap between the VOH max and the VIL max. Some gap between the VOH min and the VIL min. So that some noise come that does not corrupt the logic operation. So there has to be some margin between this VOH min and VIL min that is called noise margin. So let us look at this. So this is noise margin when an output drives an input. The manufacturers specify at the maximum IOH what is the minimum output voltage and manufacturers make sure that the VIL min that means the minimum voltage which is recognized as high or the one is below the VOH min and that is called NMH as a noise margin. This accommodates some noise voltage so that if a noise couples here it does not corrupt the logic operation. Only the VIL max has to be less than the VIL max and the difference is called the noise margin. The next thing we important to know is what is the fan out. Fan out is nothing but the number of inputs a particular output can drive. So that is fan out. So how do we find out because here we have IOH and IOL so that means when the output is high this IOH is supplying the IOH of many inputs okay. So similarly this IOL is supplying the many IOL. So basically to find out the number of the input a particular output can support we have to find the ratio of IOH to IAH and IOL to IAL and find the minimum value that will give us the fan out. So the fan out is nothing but the minimum of IOH max by IAH max and IOL max and IAL max. So that is the fan out in the case of digital circuit and you know that when a output stage like take this case the supplies VDD assume that this capacitor is C then when you know that when suppose this is switching on and off with the frequency of F you know the energy stored here is the half CV squared F but there are two paths with switching on and off. So half CV squared F plus half CV squared F then you will get the kind of switching dissipation is not the leakage the switching dissipation is nothing but the C which is the output capacitance VDD is the supply voltage and F is the frequency for an output single output stage power dissipation is proportional to the capacitance all the capacitance lumped together the power supply voltage and the frequency. So one good thing is that the power dissipation is you know quadratic actually related to the power supply voltage. So that is why many a times the supply reduction the feature size reduction happens when you reduce a feature size you make transistor small this capacitance becomes small. So the power dissipation reduces similarly since the transistor becomes small the supply can be reduced and if supply is reduced from 5 volt to 2.5 volt there is a 4 times reduction in the power supply. But this frequency many a times people are not interested in reducing it it goes higher and higher the year after year. So that is about the power dissipation equation. So here in the electrical characteristics we have seen basically the voltages and current VOH, VOL, VIL and IOH IAL and we have seen that the VOH comes down as the current goes up. So there is a minimum for VOH and VOL goes up when the current goes up. So there is a max for VOL and there has to be a margin between VOH min and VAH min VOL max and VAL max that is called noise margin. And the fan out is the ratio of the currents the minimum value of it and the power dissipation is CV squared F. So the power dissipation is proportional to capacitance that is why the transistors are made small two purposes the power is reduced. And also the area comes less so that within the same area more transistors can be put and the power supply and the feature size is reduced the power supply can be reduced to for a quadratic reduction in the power dissipation. And similarly power dissipation is proportional to frequency many a times you are not able to reduce the frequency because you know the computation requirement are high. But you can see that nowadays the devices your mobile phones or the laptops or even the desktop when it is not operational the frequency of the CPU is scaled down. That means if it is idle the frequency of the CPU core is reduced so that the power dissipation is reduced. So these are the three main constituents of at least the important constituents which cannot be ignored at all that is the function, the timing and electrical characteristics. And if you look at any data sheet you must have seen some symbol gates like 7400 I do not know whether it is used now but if you look at it the first thing is a function in the data sheet. So you have the truth table of the gate followed with all the timing parameters like TPLH, TPHL followed with all the electrical characteristics and you take the case of a processor all these will be specified that function the timing and the electrical characteristics only thing is that in the case of complex circuit this will be quite a lot of spec and many a times nowadays separate data sheets are you know issued for each of this thing. So that is I can say a brief revision of the basic. Now what is left in this overview part is that a quick review of the present state of the digital VLSI or FPGA so that you are in touch with the field before we get on with the serious design. So I hope you enjoyed this lecture please go back review refer to the reference book learn well and I wish you all the best thank you.