 So, welcome to this lecture on VHDL in the course digital system design with PLDs and FPGAs. The last class we have looked at the simulation and the various classes and data types. So, we will have a quick run and we will complete the data types and classes and we will go on to the basically the concurrent statement which will enable you to write start writing the codes for combinational circuit to start with. So, let us look at the slides the last lectures portions. We have talked about how kind of event driven computation enables the simulator to resolve concurrency. We have looked at the case where there is time delay. And we told that the time delay enables the simulator to keep track of the sequence. But in a logic simulation or functional simulation where there are no delays. This is problematic because if there is an event on A then x also the result will happen at the same time that will create an event here and the y everything changes at the same time. And you cannot keep track of the sequence or the one after the other it cannot be ordered. And the problem came because there was no delay. So, the solution is to add a small delay called delta delay. That is what we talked and do the event driven computation. So, if there is an event on A at 100 nanosecond. I look at the right hand side and then evaluate x and which is assigned after a delta delay. So, that creates an event on x at 100 plus delta. So, the simulation time move from 100 to 100 plus delta and this is evaluated and y is assigned at 100 plus 2 delta. And then there is nothing more to compute because there is nothing y does not come on the right hand side. So, everything gets stabilized. And that is shown pictorially initially we show the delta delay but everything is a delta is made 0 and everything is stabilized. Then you get the correct output A is going from 1 to 0 and you can see y is going from 0 to 1. And we also said like when you implement you can say that the delta delay how small it should be. It should be smaller than any circuit delay or any changes in the in input you know that these two are related in any way. Like you specify like delays you know change in the input kind of in relation to the delays you implement anyway. So far to kind of satisfy our curiosity we have looked at the case of feedback. We have taken a cross coupled nan latch and it was in reset mode and then we changed it to set mode. And it was a s and r both changed at 100 nanosecond and which kind of force evaluation of both z and y in the first place there is nothing z does not change there is nothing to be done y changes from kind of 0 to 1 which is assigned at 100 plus delta. The computation at 100 nanosecond is over. So, it is moved to 100 plus delta and that forces a computation on the z and z changes from 1 to 0 at 100 plus 2 delta that in done force this to be evaluated at 100 plus 2 delta. But there is no change y remains the same everything is stabilized delta is made 0 you get 100 and that is how it is shown here. It is going from kind of reset to set and you can see that this is the delta delays which is shown ultimately you can see y is going from 0 to 1. So, simulation in the case of feedback a functional simulation with feedback two things can happen either it can go on oscillating or it can kind of create a stable output after few delta delays depending on normally you can imagine it is related to number of levels of the logic you know as if there are multiple three levels of logic and you have three internal signal then it will take three sequence three steps for it to stabilize. Even in the case of feedback if it is going to stabilize in a cycle it depends on how many kind of levels of logic is there with the internal signal then it is going to be stable otherwise it will oscillate which is not an issue at all as far as simulation is concerned. And then we looked at this scenario where we had some 5 inputs maybe 6 inputs and we have some internal signal and we as we described earlier we implemented a process with this input signal in the sensitivity list. But now having known this delta cycle business we know that even though x, y, z is written in the proper order assignment with some if or case whatever then but x get assigned only after a delta cycle and when it comes to y it uses a current value of x and the change in x does not get reflected in y and change in I mean so y and z remains kind of old x is going to be assigned correct value after the delta cycle. So to be able to you know make this process compute correctly we need to put this x and y these internal signal in the sensitivity list. So x get assigned after a delta cycle which creates a simulation time I mean event on x so that comes back and runs through it y gets assigned again and even on y will make it to compute again and ultimately after 3 iteration it gets computed. So the rule is that basically you have to put the internal signals in the sensitivity list if there is one and as I said you could have written and a single expression for z then this is not required if you have internal signal then that need to be put in the sensitivity list. We also said that the concurrent statements are equivalent to the process that means you can think of concurrent statement as processor process with whatever is on the right hand side of concurrent statement in the process that means if you have multiple concurrent statement it is possible to write you know related to same kind of inputs then you can write a single process to kind of concisely represent all that concurrent statements. Similarly if you have a process with multiple output it is possible to kind of write equivalent multiple concurrent statements. So that should be understood and in any case if you have multiple process multiple concurrent statement everything is kind of concurrent to each other if an event happens then wherever that signal appears on the right hand side of concurrent statement wherever that signal appear in the sensitivity list of a process all will be computed by the simulator ok. Again when we talk about all the sensitivity list event definitely we are talking about simulation not synthesis as I said synthesis looks at the written code to infer the structure. So let us move on to the last part we have handled and ok we have looked at the synthesis and we said when you have kind of such a statement the sure way of synthesizing is to write a truth table and in this case we write the A, B as a column and you write equal output in terms of those inputs. But the problem is that as the data input width increases the complexity is exponential because it is everything expands in power of 2. So this become prohibitively kind of costly in terms of memory and computation. So most of the time the synthesis tool will infer equal means XOR plus means an adder plus 1 means an incrementer and so on ok. And normally these are implemented in the library with the proper code to implement the required circuit that means the plus will be the moment the plus is taken as a kind of function or an operator you go to the library then the adder is implemented there. Similarly when you get equal XNOR with the AND or XOR with the subsequent circuit is implemented in the library code that is how the synthesis is done not on truth table and because that can be prohibitively costly. And we have looked at the data objects classes we have 4 classes constant signals variables and files the syntax is class a name a data type signals are used everywhere the signal name and the data type constant is used for kind of some kind of generic implementation when you have a say counter then you can specify the width of the counter or the size of the counter in a constant. So that you do not have to go and change suppose you want a 16 bit counter in one place you change it and you write everything in terms of width you know wherever you say the counter output you say width minus 1 down to 0 then that is done. Variables are used for indexing temporary storage and simulation it can be used for synthesis but in a non-trivial case like a normal algorithm you take with variable then sometime it does not make sense we will see what is the use of variables. And this is the kind of syntax variable is a keyword a name in this case integer is specified and so you have to specify the range so that it can be inferred that is an 8 bit signal and files are used for test pages we will see it when we go to the test pages. Then that is the 4 classes and everything is explicitly kind of declared and the data types you have 2 types one is scalar the second one is a composite in the scalar you have enumerated integer and flow data types in the composite you have array and record and we have seen enumerated so you say type which is a keyword given name for the enumerated data type and in the bracket you write what are these values this state type can take. So in this case this is a state diagram with 5 states the names of the states are innate sample weight interrupt out whatever it means but internally this will be coded in kind of 3 bits because it is 5 states and it takes values like 0, 1, 2, 3, 4 and this assignment for whatever reason if you want to change it you could change using attributes we will see when we come to the functions and operators there this is useful. And we also have seen this particular data type here the Boolean is written which takes a false and true value and the type bit is defined with 2 values 1 is 0, 1 with codes around and this is quite restrictive so we use standard logic but the first thing defined is standard u logic and that can take values like u, x, 0, 1, z, w, lh and dash and the comments are written here and most of it is probably this is a bit of an overkill but then most of it is useful like u when a simulator starts simulating at the beginning before the signal get initialised it can be shown as uninitialised 0 and 1 are the whatever you know 0 and 1. When 0 and 1 clashes you get forcing unknown clashes in the sense that you have 2 tri-state gate both are enabled to the same line and one is driving 1 the other is driving 0. Then the resultant value is unknown so that can be represented by simulated as unknown this falls in the same line but l and h generally means weak 0 and weak 1 essentially it means that the drive is not a low resistance drive it is a high resistance drive. So when you have a line which is pulled up to the VDD then you have a h pulled down to the ground of VSS then you have the l and if l and h clashes as in the earlier case then you get weak unknown. Now mind you that just because you write an output is assigned with the l you will not get a pull up resistor or pull down resistor or a weak drive or something like that this is just a standard eulogic values the synthesis tool is not going to obey all that it is going to treat this as 0 and 1 that is a high impedance very useful and for synthesis we need like many a times we need to say something is down care and then the down care is used for simulation all these are meaningful but may not be the down care for synthesis normally we use 0, 1, z and down care. So that is a kind of standard eulogic definition and standard logic is defined as subtype standard logic is resolved standard eulogic we will see that what is this but essentially it is that when multiple standard eulogic outputs are driving a line in synthesis again it does not matter because you put tri-state gate there is no issue but when you simulate if more than 2 outputs are driving it by mistake then the resultant value is not has to be computed by the simulator, simulator has no knowledge of that because simulator just know that the standard logic takes these values. So this function this particular function resolved kind of resolve that multiple drive you know that if 0 and 1 come together this function will tell what is the resultant value okay that always need not be x because 0, 1 is x but then if both are 0 then it can be 0. And similarly if there is an h drive and 0 so 0 it can be still 0 because a weak one and a forcing 0 then the resultant value can be 0 nothing no short circuit happens like even 0 and 1 then you have a short circuit but then whenever there is L or h then there is a there is assumed to be a kind of high resistance drive so it is not a short circuit. So let us move to the integer and floating and physical types the internally this is the internal definition of the integer type integer is range like minus 2 raise to 31 to plus 2 raise to 31 okay you know the kind of 2 complement range one is the positive side is one less but then you can imagine that and the weight use it as variable suppose for a variable we are using integer then variable a name count integer range 0 to 255 always we have to specify the range because this integer range is defined as it is a big range so you have to find the equivalent width of the bus so always we limit the range or you say constant width integer colon equal to 16 whenever you say colon equal this is not like the assignment we use for the signal this is an immediate assignment. So when we assign a signal we use the symbol less than or equal to for assignment that has a significance like delta cycle and all that but this does not have any kind of delta cycle assignment or timing assignment this is assigned immediately whenever is colon equal to is used. Let us come to floating type the floating type is internally defined in the standard library as type real is range minus of 1 into 10 raise to 38 to plus same range so that is the kind of floating point number once again just because you have a data type do not imagine you take two floating point numbers and multiply the synthesis tool is going to implement a floating point multiplier it may not happen at all. So there is unlike the sequential languages we need a time in VHDL or hardware description language so that is specified as time so that is called a physical data type so you have type is a keyword time is range again the same range as this and the units one important thing is that this is integer and floating point these are mere numbers but this is physical type so you need a unit so the units is defined like that you start with units keyword the end units is the end of that kind of body then you specify the units like the basic unit is fs which stands for femtosecond then ps which is pico second equal to 1000 femtosecond nanosecond is equal to 1000 pico second microsecond so on up to hour. So in a simulator and the VHDL code you are able to specify you are able to say after 10 nanosecond after 100 femtosecond after 1 minute and so on whether it makes sense or not but you can specify the signals with the time delay you require and that is enabled through this physical data type. So these are the kind of predefined the data type internally you have enumerated you have integer you have floating type which is called real and the physical type like time. One more thing is that you can define suppose you have any of this type you can define a sub type of the type so here you see the definition is a sub type which is a keyword my end is integer range 4856 so wherever you use my end it is the integer with range 4856 similarly you have sub type ux01 it is just a name any name is resolved standard u logic resolved means it causes a resolution function range u21 that means it takes in the standard logic all the values from ux01 you know that is the meaning of it u21. So like but then you might ask you could have written like this you know we have written sub type a name is integer range 4856 but you could have also define a type of your own like saying type my end is range 4856. So kind of what is the difference between these two if you can think about it some of you might know when you use sub type you are a kind of you are a part of that my end spec. So essentially whatever operators define for my end can be used here. So you can use the plus minus division multiplication whatever was defined for integer can be used by this particular when you use this. But if you define your own range then you have to overload those operators for your type. So it is not a kind of simple difference so if you can live with a sub type always use a sub type then defining your own data type because if you define your own data type then you have to overload all the operators whatever you need for that particular data type like suppose you are defining your own integer you have to go to the integer operators and overload for this new data type. So you will end up writing a lot of functions to overload for plus minus multiplication exponentiation and so on. So always try to use a sub type if at all is required. So let us move on let us see some we have seen the definition of what is standard. But you could define your own data types say take this case just as an example. But when you do design try to use the inbuilt data types because operators are specified you will have less headache than defining kind of your own data type. So these are some of the user defined examples of user defined data type. Say type MEL is u,0,1,z it is a user defined enumerated data type. Similarly type index is range 0 to 15 this is a user defined integer. The next one word length is range 31 down to 0 it is a user defined integer data type. Type volt range is 3.3 down to 1.1. So it takes all the real values so it is a user defined real type. Similarly this type current range is 0 to 1 in generation 9 which is again a user defined real type. And this is a user defined physical type which is type current is range 0 to 1 in ion. Then you define units nano ampere, micro ampere, milli ampere and ampere and there is which shows a sub type kind of declaration. So that is a user kind of data types the scalar ones enumerated integer real then the physical types this can be predefined this can be user defined. So let us look at the composite data type look at this definition of an array. So here it is defined as type word type is a keyword for a data type word is a name is array again keyword 15 down to 0 bit which we are saying that whenever we use word it is a 16 bit bus you know that is the meaning of it. And then you can declare signal address east of type word that means address is a 16 bit bus or a 16 bit signal. And like in libraries many a times arrays are declared unconstrained that means here you say take this example which is in the standard logic 1164 package which say type standard logic vector is array natural range this means unlimited that means whatever is a natural number defined in the standard library mostly that is 0 to 2 raise to 32-1 of course of standard logic that means that this standard logic vector means such a huge unconstrained array. But that is why when we declare we use standard logic vector we constrain it to proper size like here signal a is standard logic vector 3 down to 0 so it is 4 bit because at the time of definition it is unconstrained so we constrain it while using it that is the kind of standard logic vector. So this is a kind of single dimensional array but nothing stop you from you know using it for two dimensional or multi dimensional array. So an example is shown here type a name is array 0 to 7, 0 to 3 of standard logic. So you can imagine this is an 8 element array each element is of 4 bits you know that is a meaning of it like 4 bits or 4 standard logic values. So it is an 8 by 4 two dimensional array and you see how this data type is used constant XOR that is the type this particular two dimensional type equal to then you have 8 values which is in kind of double quotes each value because it is multiple bits and each value is of 4 bits and an underscore is put to just separate you can use underscore whenever there is a kind of string to separate and if you carefully look at it this is nothing but the truth table of 3 input XOR gates you have these are the inputs and this is output. So this is a clever way of writing the truth table so that is array so nothing stop you from using it for multi dimensional array if it is useful there are you know kind of two dimensional structures sometime used in hardware. So in such places it will be advantageous to use two dimensional or multi dimensional array and let us come to this record type which is similar to the structures of C. So here how it is defined is an example is shown type IOSL is record and you say n record and within it you can include multiple signals. So here you have an input signal called you know buffer input is standard logic vector 7 down to 0 enable is standard logic buffer out is again 8 bit vector just comprises of two 8 bit signal and one single bit signal it just mere signals there is no logic but you can imagine this as say you have a tri state gates 8 of them gang together to connect to an 8 bit bus maybe then this can be treated as the input of the tri state buffer this is the output of the tri state buffer and enable is the enable signal of the tri state buffer. So this is something you know in hardware which comes together so maybe it is worthwhile to put it together in a record so not very much used but then can be useful. So this shows the usage you have a signal which is bus A, bus B, bus C is of type IOSL it means that there are three kind of similar structures you know input output and enable and we have a vector which is 8 bit. Now in principle you can assign this vector input 8 bit vector to the input of bus A output of bus B and so on ok. So let us see how it is used so here you say bus A dot buffer input means for this particular bus the buffer input is assigned with the vector which is an 8 bit you know vector which is defined here similarly you can say bus B buffer input is bus A buffer input it means that they are tied together you have two inputs tied together bus B enabled is one means that you are driving one to it bus C is bus B means that again these are everything is connected together you know that is same. Suppose you want a logic you really want to synthesize type C logic between this input and output then you say bus A for particular bus bus A dot buffer out is assigned bus A dot buffer input when bus A dot enabled is one else others Z ok. Now we will see soon what is others Z others Z means all the values all the 8 bits if it is in the case of 8 bit is tristated that is the meaning of it. So we will the record is not much used but then in principle you could combine kind of signals with the correct contacts you can combine put it together which may be useful to kind of a kind of modular code useful to understand all that. And let us come to this keyword Elias this is nothing but suppose you have a 32 bit address signal address is standard logic vector 31 down to 0. And many a times you want to use some top bits of address for something may be memory decoding like when you have an address bus the lower address line goes to the address addressing the memory and peripherals it is a higher bits which fix the memory map. So that is used for chip select decoding so maybe we have an suppose we need we are doing the top 4 bit for this kind of chip select decoding and we do not want to write all the time address 31 down to 28. So we give use an Elias or another name called say top add then how it is defined is you say Elias the name how many bit it is standard logic vector 3 down to 0 it is 4 bit is now that 4 bit comes from where is written here is address 31 down to 28 that means that we have a 4 bit signal which is 31 down to 28 of address is now known by a different name. So wherever you stop add you will get this properly ok that is a basic idea. Now let us come to when you have an array how to assign the array so please have a look at this various type of assignments. So the signal is defined as a row which is standard logic vector 7 down to 0. So this is a row signal which is an 8 bit vector so it can be assigned in these ways you know say row assigned 1 0 like individual bits and if you remember our component instantiation this is like a positional association like 7th bit is 1, 6th bit is 0 and so on ok. So that kind of prompts us you can use the kind of named association so we can say row get 7th position is 1, 6th position is 0, others is 1 means all others other than 7 and 6 all others are 1 ok and you could even write like a complete string you said you put double quotes and write the value like as a single string say 1 0 1 1 1 1 1 1 like that you could write. You could use others along with the positional association like you say row is 1 0 and all others are 1 others like it is equal to and greater than 1 ok. You could use various bases you say row is x bf that means row get you know kind of 1 0 1 1 1 1 1 1 1 which is the hexadecimal equivalent of this whatever assignment done here you could use octal binary specifiers also the pieces also and you could say like this you know many times at the initialization you may want to make everything 0 or tricep then you can say row gets others assign 0 that means everything is 0, row others z that means everything all the 8 bits of row are z that is what is you know written here bus a dot buffer out is bus a dot buffer input when bus a enabled is 1 else is tristated is the thing. So I think that concludes the data type which is a little boring the class and of you know the objects data type so the last part we have seen the composite data type array you can have arrays a multidimensional arrays you can assign them in various ways you can use record to combine something kind of which comes together like in an IO cell and things like that so that is and we have seen this array assignment for the row. So let us move on now with the serious the VHDL so all kind of different models of description how the simulator works what are the classes what are the data types all that is kind of we have covered now let us get on to the serious business of writing the codes which need basically the constructs of the statements and we will go to the statement. So first let us take the concurrent statements when I say concurrent statement these are the statements written in the architecture declaration region as a concurrent kind of statement that means it is not written in the process not written in the function not written in the procedure ok. Procedure can have concurrent statement but any of the sequential bodies you cannot have the concurrent statement so normally it appears in the architecture statement region. So let us come back to the slide you have two types of concurrent statement one is called with select when and the second one is called when else ok. These are the two concurrent statements there are loop like generate loops which we have seen we will take that up later after maybe the sequential statement also. So let us look at the syntax for with select when the syntax is like this with that is a keyword cell is some input it can be single bit multiple bit select ok that means we are going to define an output in terms of the various values of this input signal that is a game and you say some output signal it can be y z or any name assigned to say some expression of inputs a when choices choices mean the values of select line ok. If select is 2 bit you say y gets 1 when 00 ok y gets 0 when 01 and so on ok. So the rule is that so this is the output signal output signal single bit or multiple bit this is an input signal and the choices means all the values of input signal or mutually exclusive values you cannot specify 00 here and again here this has to be mutually exclusive and one more thing is that if you write an expression then this is composed of input. So you have inputs here you have inputs here your outputs here and now you think what is happening when you have some input signal you are telling the output for all the values of input signal ok and this can be as I said this need not be an expression in terms of input it can be some 1 and 0s or numerical values. So you must be getting the idea that for some input signal all the values of input signal you are specifying the output this is nothing but the truth table ok. So I am bringing it early on because many textbooks show some typical examples which we will discuss it which looks as if the width select is kind of man for that particular hardware and so on. So that is to avoid this confusion I am talking about the truth table. So basically we are specifying the truth table for an output signal in terms of the input signal and let us see some examples say here you take this example which says that there is an input called A which is let us take it as 2 bit with A select Y is the output Y gets 0 when A is 00 0 when 10 1 when 11 0 when others ok I will come to this in a moment which says that Y is 1 when A1 is 1 and A0 is 1 else it is 0. So you quickly get this is nothing but an AND gate. So it is very simple it is a truth table of an AND gate which is quite complete here there is nothing to add but you may be wondering about what is this game like the syntax also we said some expression last one is when others that means when you come to the last one whatever is not covered here can be covered you know can be written here. So in principle we could have written 1 when others instead of when 1 1 ok. Now mind you this is if you do not write the tools are going to complain because you should know that assume that we are using standard logic then each standard logic bit can take the 9 values. So if A is 2 bit as a combination it can take 8 to 1 values and we are only specifying 4 of them and the simulator should know what should be the output if none of this condition match. So you need to say what is like for 9 into 9-4 77 cases are not specified what is the output for those 77 cases need to be specified that is what this is doing and this you could combine with the last one there is no absolutely no need to write an extra kind of statement ok. So basically the truth table of this looks like this you have A1 A0 because it is 2 bits 0 0 is 0 0 1 is 0 1 0 is 0 and 1 1 is 1 so it is the equation is nothing but y is A1 and A0. So this is a very simple case of with select. So let us add some kind of expression and see what is happening like we said some expression in terms of the input. So let us write one statement for that so let us see this. So we say with A select y gets B when 0 0 y gets not of P when 0 1 y gets C when 1 0 y gets B when 1 1 and when others it really does not matter and this definitely helps in debugging and all that something goes wrong when you simulate like if you give a proper value then this can be easily kind of you know debugged from some whatever is happening at the output. So that is a one kind of side effect of this when others. So if you look at this you know that 0 0 is B 0 1 is not B 1 0 is C and 1 1 is B. So the truth table you have A as 2 bits A1 A0 you have B and C so y is written in terms of this when it is 0 0 you can see y is 0 when B is 0 y is 1 when B is 1. So that is the meaning of the first one y gets B when 0 0 y gets not of P when 0 1 so when these are 0 1 B is 0 the y is opposite of that. Similarly come to the 1 0 when 1 0 is there the y is nothing but exactly same. So but only thing is that each statement you can see now because of this inclusion of B and C expanded into multiple rows and when it is 1 1 this is nothing but y is B so 0 0 1 is 1. So if you write the equation the equation comes like this. So here the equation is y gets A1 bar A0 bar A1 bar and A0 bar and B that comprises of this two rows which is combined. So basically equations comes as the min terms okay you like in this wherever there is one the min term is there but here we do not know we are not working with numerical values so we have to write everything. So this captures this particular two rows and the next like A1 bar A0 is capturing this y is nothing but not of B 0 y is 1. So that is an B bar so that is this two rows and this is or so if it is 1 0 then the y is nothing but C if it is 1 1 then y is nothing but B. So that is shown here. So each of this kind of equation is translated to is coming from two rows in the simple case if there are numerical value then it is it will be coming from a single row. So that is how the two table is formed in this case. So let us go to another example so that you are thorough you should not think you should not be confused about with select. So let us okay this is what I have told now mind you one thing when you write such a code if anything any event happens on the input okay like input can be A, input can be B then this the simulator will compute this particular concurrent statement. So if there is an event on A event on B event on C anywhere this will be computed that you should keep in mind but when it comes to synthesis tool it does not matter it looks at this code and you know come out with the implementation either through two table or through the operator whichever is kind of easier. So that is what is summarized here for all the mutually exclusive values of input signal output is specified which is nothing but two table and each choice represent a min terms and the output equation is that min term or another min term because both condition cannot happen at the same time. So you have or of min terms wherever there is one happens when output is expressed as a function of some input then this can be translated to each row each statement can be translated to multiple rows in a truth table. But in equation it can be written as a single statement not an issue. Similarly you can work out the equation looking at the truth table and we said that simulator whenever there is an event on input simulator computes but synthesis tool look at the code and try to kind of generate the circuit. So let us look at another example which is a 4 to 1 multiplexer. So you have four inputs A, B, C, D of some width can be 4 bit or 8 bit or whatever or even a single bit and y is again the same size as A, B, C, D and select line is 2 bits and now we write y in terms of the various values of select line so width, cell, select that is this y gets A, A when 0, 0 when this is 0, 0, A will go to y, 0, 1, B, 0, 1, 0, C, 1, 1, D. So that shows the kind of multiplexer implementation using the width select. Now this can be little unfortunate because most textbooks kind of specify this as a standard example but the trouble is that people will think that from the syntax this is something specific for multiplexer but as we have said that it is a truth table we are specifying in some kind of basic level or little abstract level. So basically any combinational circuit can be implemented using width select, multiplexer looks little natural for you know the syntax. So that is the multiplexer with cell select 0, 0, y gets A and so on. Now let us derive the equation and you know that irrespective of the number of bits the equations are going to be same. Suppose you have y3 to y0 then the path between A3 and y3, A2 and y2 is same as the path between A1 and y1, A0 and y0 and so on okay. So the equation is that you go row by row so you have yi is nothing but a of i like if it is y0, a of 0 when select 1 bar and select 0 bar okay that is this or like b of i when select 1 bar and select 0 okay. So that is the second kind of choice or the third and so on. So basically you work out the equation as the min terms or the product terms here or the next product term and so on. That is how the equation is defined as I said absolutely this syntax has got nothing to do with the multiplexer this is used for combinational circuit and the multiplexer looks like a natural fit for this kind of syntax. But mind you you should know always remember in the case of multiplexer the select line is going to the input of the AND gates and sometime the picture convey a message saying that this is something controlling which when it is become 1 the input goes to output and so on like a thyristor but then it is very unfortunate because we know that the select is also an input ABCD is also input okay. So in principle so when I want to kind of summarize so with select it can be used in any combinational circuit suppose you have multiple inputs ABC and an output y then in principle you can choose any of the input and you can say with say let us pick b you can say with b select y gates now we have to specify the y because we are going to specify 00 of b. So when you decode that min terms come properly but when you write y now for you have to write as a function of a and c because that is not specified. So for this case when the value is 1 the y is function 1 of a and c value is to another function of a and c and so on. Ultimately we say when others you know comprising of all the cases which is not discussed. And in principle you can even write a multiplexer with as a select line okay. So there is nothing you can write to say with a select y gates function of BCD and select various functions of BCD and select. It is like in the case of a multiplexer if you do that it is going to be quite cumbersome and it may not make much sense. So it is natural that we use a select signal as the real select signal of the concurrent statement. So that is about the concurrent statement and this is used for combinational circuit without any priority and you can also it is not that you have to specify suppose you have this function and this function are kind of same then you can say same function when value 1 or value 2 okay that is what is shown here. You can have multiple choices in a single statement say here you say we have a prime number kind of detection for 3 bit input. The num is a 3 bit kind of input prime is output we say when it is 2, 3, 5 and 7 the prime number is high. So you say prime gets 1 when 010 or 011 or 101 or 111, 0 and others. So you could use the choices in the case of with select to combine. So the next one is when else maybe we will take that in the next class because we will not be able to cover it. So a quick recap of what we have done today like this is what we have done this index with select and output signal is specified in terms of the mutually exclusive values of some input signal the output can be numerical values or some expression of the various input signal. And the rule is that you have to specify the mutually exclusive everything mutually exclusive values and when you say when others it captures everything which is not specified. And when you use standard logic this is quite useful because there are lot of each standard logic position take 9 values. So if there are multiple bits then there are lot of unspecified thing which simulator would like to know how to handle it. So that is why we specify that and we have seen a simple example of an AND gate which is straight forward you know you have the truth table. And how the equation comes you write the minterm of wherever there is one or minterm of the if there is a one another places but here it is only in one place. And we have seen a little more complex example where the output is a function of not only the select line but the input then you have the equations coming as a1 bar a0 bar and b and so on. So we have seen a truth table where a single statement expand multiple rows and when you write equations again it becomes concise. And we have seen that a multiplexer you know the code to be familiar but as I said this is with select has got nothing to do the multiplexer. In principle any combinational circuit can be coded with the with select. So you have multiple inputs you pick up one input write the output as different functions of other inputs for each values of b that is the basic idea of with select. And it is used wherever there is no priority. So any combinational circuit without priority you can implement you can specify choices using what kind of multiple choices using vertical bar. So I think I wind up today's lecture please go back and read that whatever we have covered in the data type basically the integer physical user defined then the arrays and records. Then we have looked at the syntax of with select please go and revise it write some simple program if you can with with select very simple combinational circuit you can take and write it using the with select. So we will continue with the concurrent statement and the sequential statement next class we will have a look at the other concurrent statement called when else. Then we will follow it up with the if then case when sequential statement and try to complete the combinational circuit part very soon. So thank you wish you all the best.