 Namaste, welcome to the session design examples on synchronous counter. At the end of this session students will be able to analyze and design synchronous counter examples. Now, let us see design steps in synchronous counter, but before that take a pause here and recall what is synchronous counter. So, synchronous counter is also known as parallel counter since flip-flops are triggered simultaneously by a clock pulses. So, in synchronous counter all the flip-flops which are used in a counter are simultaneously clocked by a basic clock input and synchronous counter are faster as compared to the synchronous counter, but those are complex one. Steps to design synchronous counter. In the first step we are finding out number of flip-flops required using equation n less than or equal to 2 raised to n, where capital n represents number of states and small n represents number of flip-flops. Then in the next step we are writing count sequence in the truth table and then we are writing excitation table of the selected flip-flop and based on the excitation table or the state table we are drawing a K-map and obtaining equations for the flip-flop inputs to design a counter and finally we are drawing a logic circuit based on the obtained equation. Now, let us see the example 1. So, the question here is design a counter that goes through states 0, 3, 5, 6, 0 using t-flip-flop. So, here in this equation you can analyze that the counter is up counting, but with a specific states. So, here we have to draw the state diagram first. So, in the state diagram we should have only these states. So, we have here the state 0. So, after state 0 next state should be 3 and to that we should have 5 and then 6 and after state 6 it again repeats the previous or initial state that is 0. So, in this way the counter should work. So, for this state table is as it is told in the question that we have to use t-flip-flop. So, we are having excitation input for the t-flip-flop. So, we have column as present state represented as PS then next column is NS that is next state and the last column is required excitation for the t-flip-flops. So, as you can see here the final state is 6. Here we require 3-flip-flops because we have to make the counter to go through all these states. So, we require at least 3 t-flip-flops here and the output of flip-flops are represented as Q3, Q2, Q1 from MSB to LSB bit. So, very first state is a 0. So, it is represented as 0, 0, 0. So, when you are in a state 0 then next state should be 3. So, in the next state you can see here 0, 1, 1. So, when you are in a state 3 next state should be 5 and when you are in a state 5 the next state should be 6, 1, 1, 0 and when you are in a state 5 then next state should be 6 and when you are in a state 6 then next state should be again 0. So, in this way we have written here present state and next state and to make the transition from present state to next state we have the excitation input for 3-flip-flops. So, for t3 we have 0 to 0 transition. So, 0 input for the next input 0 to 1 that is toggle mode. So, we have to give input as a 1 to the next that 1 to 1. So, there is no transition. So, again t input is 0 and when it is 1 to 0 the t input should be 1. So, for the second t-flip-flop you can see here from present state to next state always there is a transition from 0 to 1 or 1 to 0. So, there is always toggle mode. So, here you can see the t2 input are all 1, 1, 1 because there is a next state which is opposite to the previous state or present state. Then for the t1 again we are writing here as excitation input if it is 0 to 1, 1, 1 to 1, 0, 1 to 0, again 1 and 0 to 0, 0 and based on the state table we are writing k-map here for the t3 the first k-map is written. So, t3 we are getting output high for this combination 3 and 6. So, in the cell 3 and 6 we are marked here 1, 1 and as you can see here we have 0 3, 5, 6 are the valid states and invalid states are taken as a don't care conditions. So, invalid states are 1, 2, 4, 7. So, for making a group 2 and 7 are helping here to make it a quad. So, this quad gives us t3 is equal to q2. So, similarly for the t2 so we are getting 1, 1, 1 for all these input combinations those are 0, 3, say 5, 6. So, 0, 3, 5, 6 and all other cells are nothing but don't care conditions. So this is forming octet and octet gives us t2 is equal to 1. Similarly k-map for t1 we are getting output 1 for 0 and 5 for 0 and 5, 1, 1 and don't care conditions are 1, 2, 4, 7 again. So, this is giving us a quad which will give us t1 is equal to q2 bar. So, from this k-map we are obtaining equations as t1 is equal to q2 bar, t2 is equal to 1 and t3 is equal to q2. Now here in the logic diagram we require three flip-flops which are simultaneously clocked from the single clock input. Then we are giving input as per the logic equations. So, t1 is equal to q2 bar. So, q2 bar is connected to t1 as a input then t2 has a input as a 1, t3 has a q2. So, in this way we can design a particular synchronous circuit using a particular flip-flop. Let us have next example design a counter that goes through states 0, 1, 2, 4, 0 using deep flip-flop where the undesired states must always go to 0 in the next clock pulse. So, as you can see here there is a state 4 also. So, here we require three flip-flops again and we have to use deep flip-flop. So, let us draw the state diagram here. So, state diagram is so, counter should go only through this states 0, 1, 2, 4 and one more condition is that whenever counter goes to undesired states as 3, 5, 6, 7 it must always go to state 0. So, according to this state diagram we have to write a state table as present state and next state and we are writing next state based on this diagram. So, whenever it is in state 0 it should go to 1, whenever it is in 1 it should go to 2, whenever it is in state 2 it should go to 4 and whenever it is in 3 now 3 is invalid or undesired state. So, it should go to 0. So, for 3, 5, 6, 7 you can see it is in state is going to the 0 state and whenever it is 4. So, for 4 it is going to 0 and when it is 0 then cycle repeats it goes to 1. So, based on this we are writing excitation input for the deep flip-flop. So, you know that deep flip-flop is a transparent flip-flop. These are the excitation input for the deep flip-flops. So, it is similar to the next state. So, from this column of excitation input we can write the equation for D 3 D 2 D 1 as we are getting output high for D 3 for this input combination. So, it should be Q 3 bar Q 2 Q 1 bar for D 2 for this combination we are getting output high that is Q 3 bar Q 2 bar Q 1 and for D 1 the first input combination uses D 1 is equal to Q 3 bar Q 2 bar Q 1 bar. The logic equations we obtained are D 1 is equal to Q 3 bar Q 2 bar Q 1 bar then D 2 is equal to Q 3 bar Q 2 bar Q 1 and D 3 is equal to Q 3 bar Q 2 Q 1 bar. So, based on this logic equations we are drawing the logic diagram with appropriate inputs. So, that we have connected here Q 3 bar Q 2 bar and Q 1 bar with the help of this AND gates then D 2 having input Q 3 bar Q 2 bar. So, Q 3 bar Q 2 bar already connected to the AND gate and then we are connecting Q 1. So, Q 1 is coming from here and the Q 3 bar and Q 2 bar coming from this AND gate and finally, for the D 3 we have Q 2 which is coming from here and Q 3 bar and Q 1 bar those are coming from this AND gate. So, in this way we can design any such counter these are references. Thank you.