 Hello, and welcome to this presentation of the STM32 MP1 Reset and Clock Controller, or RCC. The RCC is a complex block closely working with the power controller block. So, before going through this slide set, please have a look at the power control module. The RCC offers several clock sources, three internal RC oscillators, two oscillators using an external crystal or resonator, and four PLLs or phase locked loops. The clock distribution block uses all those clock sources to provide a flexible set of clocks for peripherals, bus interconnects, and processors. The clock gating control block is in charge of the gating of the clocks in order to optimize the power consumption. Many peripherals have their own clock, independent from the bus interface clock, allowing the user to dynamically change the bus interface clock without affecting the peripheral interface rate. The STM32 MP1 RCC provides high flexibility in the choice of clock sources, which allows the application to meet both power consumption and accuracy requirements. In addition, the RCC also embeds a reset control block, generating the reset for the complete system. Finally, the RCC register interface, trust zone capable, allows the application to properly control each function of the RCC. The RCC can be fully controlled via registers. The RCC offers trust zone capabilities and can handle three kinds of secure attributes. The always secure registers. Those registers can be modified only by performing right secure accesses. The secureable registers. Those registers can be switched to secure or non-secure mode via two bits, TZEN and MCK PROT, located in an always secure register. TZEN and MCK PROT bits enable the application to control the security perimeter. This is detailed in the next slide. And the non-secure register. Those registers can be modified by secure and non-secure right accesses. On top of trust zone, some registers of the RCC can only be written by the MPU. This is the case for the registers offering services dedicated to the MPU. Those registers are also sensitive to trust zone, so it is possible to have registers allowing only secure right accesses performed by the MPU. The following access rules apply for the RCC. All registers can be read without restrictions. The MCU is also allowed to read registers dedicated to the MPU. A secure register can only be modified by a secure writing. A non-secure writing into a secure register generates a hard fault. Non-secure registers can be modified by secure or non-secure right accesses. And the MCU cannot write into a register designated MPU only. At the RCC level, the trust zone feature prevents a non-secure application from performing a reset or disabling a peripheral used by a secure application. The figure gives a simplified view of the trust zone perimeter. The RCC can be in three different protection modes. The first mode is the non-secure mode, TZEN equals zero. In this case, all registers can be accessed in a non-secure way. Some registers are still protected against master accesses other than the MPU ones. The second mode is the secure mode with TZEN equals one and MCKPROT equals zero. In this case, peripherals located in the APB-5 and AHB-5 domains can only be used in secure mode. The DDR and MDMA are also protected, as well as all the required interconnect buses and clock generators. In this configuration, the secure peripheral shall use clocks provided by secure elements. And the third mode is the secure mode with TZEN equals one and MCKPROT equals one. This mode is similar to the previous one, but the perimeter is increased in order to also secure the MCU subsystem. Now let's focus on the reset part of the RCC. The RCC offers a rich set of safe and flexible reset management without any need for external components to reduce the application costs. The RCC manages several types of resets, the power-on reset, the system reset, the local resets, and the backup domain reset. Thanks to the voltage monitoring included in the PWR block, the filters embedded into the NRST pad and the RCC reset control, the amount of external components is significantly reduced. The first type of reset is the application reset, which resets most of the registers except the ones located in the backup domain. Many sources can generate an application reset, an invalid voltage on the VDD supply, see the PWR block for details, an invalid voltage on VDD due to a brownout function. The brownout function allows the user to choose their own threshold levels for the VDD supply, see the PWR block for details. A low level on the NRST pad, a timeout from one of the independent watchdogs, IWDG 2 and 1. Software reset request initiated by the Cortex-M4, the MCU, if the option bytes allow it. Software reset request initiated by the Cortex-A7, the MPU, the RCC registers, or a failure on the HSC oscillator. Note that the application reset asserts the pad NRST, allowing the reset of external components. A system reset is generated when the application reset is asserted, or when an invalid VDD core is detected, V-core RST. This situation appears after a power-on sequence, or when the chip exits from standby mode. The option bytes configuration and the memory repair sequences are triggered every time an invalid VDD core voltage is detected, or when an application reset occurs. The block named RPC-TL, or reset pulse control, allows the application to define the minimum activation time of the NRST pad. The block named RD-CTL, or reset delay control, allows the application to delay the activation of the system reset until the DDR is in self-refresh mode. Those two blocks will be explained later. The backup domain reset occurs when the VSWRST bit is set to 1 by the application. As shown in the figure, this bit is located in the RCC-BDCR register. When the VDD and VBAT are both powered on, if both supplies were previously off. The MPU reset is performed when the MPU resets one of its processors via MPU-PXRST bits. One processor can be reset without disturbing the other. The snoop control unit is not reset. When a system reset occurs, or when the system exits from C standby mode if allowed by the PWR management. The MCU reset is performed when the MPU asserts the MPU-RST bit, when a system reset occurs, when the window watchdog is not reloaded at the right moment, or when the MCU requests a system reset. The reset of the system can be blocked by an option byte, but the reset of the MPU is performed. The peripherals are reset either by their respective reset bit on RCC registers or by a system reset. The debug parts are reset when the bit DBGRST is asserted on request of the DAP or when the VDD core is invalid. The table is a simplified view of the parts reset by the most important reset sources. The power on reset or PORRST is the reset having the largest coverage. It resets all the logic located in the VDD domain and most of the logic of VDD core. The logic located in the backup domain powered by VBAT and the logic located in the VSW domain are not reset. Note that the power on reset also triggers the system reset and APPRST, and the NRST pad is asserted during the power on reset. The application reset or APPRST resets most of the logic located in the VDD core domain except some resources located in the RCC and the PWR. The backup and VSW domains are not affected by this reset. The system reset or NRESET resets most of the logic located in the VDD core domain except some resources located in the RCC, the PWR. Debug components, IWDG2 to 1 and the backup and VSW domains are not affected by this reset. The V-CORE reset or V-CORE RST resets most of the logic located in the VDD core domain except some resources located in the RCC, the PWR. The IWDG2 to 1 and the backup and VSW domains are not affected by this reset. The backup domain reset or NRESET VSW resets all the components located in the backup and VSW domains which contain the RTC and the external low speed oscillator, the backup RAM and the retention RAM. The reset pulse control block allows the application to control the minimum activation time of the NRST pad. This feature is particularly helpful because some external devices may request a minimum reset duration for the activation of the NRST. The reset pulse duration can be adjusted from 1 to 31 milliseconds with the accuracy of the LSI oscillator. If the LSI is switched off when a reset occurs, the LSI is switched on as long as it is needed by the RPC-TL control register. The reset delay control block allows the application to set the external DDR device into self-refresh mode before generating a system reset or NRESET to the circuit. When an application reset occurs, C1, the RDC-TL maintains this reset active and prevents the propagation of the system reset, C2. Then the RDC-TL requests the DDR-PHY to switch the DDR into self-refresh, C3. Once it is done, the RDC-TL asks the PWR to switch DDR pads to retention, C4. Finally, the system reset is propagated, C5, and the application reset is no longer maintained, C6. If the DDR-PHY does not answer to the self-refresh request, the system reset is propagated to the circuit after a timeout delay programmable by the user. The RDC-TL block can also be bypassed if needed. The RCC stores the reset root cause into two registers, RCC-MCRSTS and RCC-BRRSTS. The boot ROM can check and acknowledge the reset root cause via the RCC-BRRSTCLRR register. In addition, the boot ROM updates the physical register RCC-MCRSTS via the RCC-MCRSTSETR register. The MPU can check and acknowledge the reset root cause via RCC-MCRSTCLRR register. The MCU can check and acknowledge the reset root cause via the RCC-MCRSTCLRR register. The hold boot function allows the MPU to maintain the MCU in a frozen state every time the MCU is reset. After a system reset, the hold boot function is enabled and the MCU is frozen. The MPU can then load the application code into the MCU SRAM and allows the MCU to run by setting the bit boot MCU to 1. When the circuit is running, the MPU can decide the behavior of the MCU after an MCU reset. The MCU can simply reboot after an MCU reset if boot MCU equals 1. Or the MCU can remain frozen after an MCU reset if boot MCU equals 0. The MPU can decide which processor is allowed to restart its application after a standby mode. This feature is controlled via two bits, MPU-BEN and MCU-BEN. For example, when the system is in standby mode, if an event wakes up the system, the boot ROM checks if the MCU must be activated or not via the MCU-BEN bit. If the MCU needs to be activated, the content of the RETS SRAM is checked or not by the boot ROM code before giving the control to the MCU. The MPU application boots or not according to bit MPU-BEN. If the MCU needs to wake up the MPU, it can generate an SEV event. Focusing on the clocking part, the RCC offers a large choice of clock sources which can be selected depending on low power, accuracy and performance requirements. The STM32MP1 microprocessor embeds three internal RC oscillators. A high-speed internal RC oscillator or HSI which can work at 64, 32, 16 or 8 MHz. A low-power internal oscillator or CSI working at 4 MHz. And a low-speed internal 32 kHz RC oscillator, LSI. It also embeds two oscillators working with external crystals or resonators. A high-speed external 8-48 MHz oscillator or HSE with a clock security system. And a low-speed external 32.768 kHz oscillator or LSE also with a clock security system. Four PLLs are also available, each with three independent outputs for clocking different peripherals at different frequencies. Note that the USB and DSI have their own dedicated PI. The high-speed internal oscillator is a 64 MHz RC oscillator with an accuracy of 1% and a fast wake-up time. The HSI clock is trimmed during production testing and can also be user-trimmed. A dedicated divider allows the generation of a 64, 32, 16 or 8 MHz clock. The HSI clock is selected as system clock for the MCU when the system wakes up from system stop mode. The HSI clock remains powered when the system goes to stop mode in order to speed up the wake-up time. Some peripherals such as the I2C's and UART's can request the activation of the HSI clock in system stop mode for their own processing. If the HSI is disabled, the RCC automatically enables the HSI and provides this clock to the peripheral which requested it. The low-power internal oscillator is a 4 MHz RC oscillator with an accuracy of 5% and a fast wake-up time. The HSI clock is trimmed during production testing and can also be user-trimmed. The HSI clock can remain enabled when the system goes to stop mode in order to speed up the wake-up time. Some peripherals such as the I2C's and UART's can request the activation of the HSI clock in system stop mode for their own processing. If the HSI clock is disabled, the RCC automatically enables it and provides this clock to the peripheral which requested it. A crystal or ceramic resonator working in the range of 8 to 48 MHz can be connected to the HSI clock. The HSI can also be set in digital bypass mode and receives a digital clock on the OSC-IN input. In analog bypass mode, a clock with a reduced amplitude down to 200 mV peak-to-peak can be used. A clock security system allows an automatic detection of any HSI failure. In this case, an application reset is generated and a failure event is provided to the temp block, allowing the protection of backup registers and the backup RAM. Some peripherals can request the activation of the HSI clock in system stop mode for their own processing. If the HSI clock is disabled, the RCC automatically enables it and provides this clock to the peripheral which requested it. The boot ROM must use the HSI oscillator when a boot is requested via the USB port. For that purpose, the boot ROM needs to know how the HSI clock is used in the product and configures it properly. The OSC-OUT must be connected to ground via a resistor in order to inform the boot ROM that an external digital clock is provided as HSI clock. The OSC-OUT must be connected to VDD via a resistor in order to inform the boot ROM that an external analog clock is provided as HSI clock. If pull-up or pull-down are not detected, then the boot ROM configures the HSI in oscillator mode. The STM32MP1 microprocessor embeds an ultra-low-power 32 kHz RC oscillator which is available in all modes except in VBAT mode. The HSI clock can be used to clock the RTC, LPU arts, some RCC blocks, low-power timers, and the independent watchdogs. The 32.768 kHz low-speed external oscillator can be used with external crystal or resonator or with an external clock source in bypass mode. The oscillator driving capability is selectable in order to adapt the oscillator characteristics to the external crystal device. A clock security system monitors the failures of the LSC oscillator. In case of failure, the application can switch the RTC clock to the LSI clock. The clock security system is functional in all modes except VBAT mode. The LSC clock can be used to clock the RTC, the USARTS, or low-power UART peripherals and the low-power timers. The PLLs embedded in the device provide a flexible way to generate the wanted frequency for the system or peripheral clocks. The STM32MP1 microprocessor integrates two PLL 1600s. The input frequency must be between 8 and 16 MHz. The VCO frequency must be in the frequency range of 800 to 1600 MHz. The PLLs also provide three different outputs, which are all derived from the VCO frequency divided by two via post dividers, DIVP, DIVQ, and DIVR. In addition, it is possible to change the values of the post divider without disabling the PLLs. The application just needs to disable the corresponding post divider, change the division ratio, and re-enable the post divider. In order to get a duty cycle close to 50%, the application has to program the post dividers to even values. The PLLs can be switched in fractional mode, allowing a high precision in the VCO frequency. The 13-bit fractional divider can be changed without disabling the PLLs. The feature can be useful to perform accurate clock drift compensation. Finally, the PLLs integrate a spread spectromechanism in order to reduce the amount of EMI, more especially for the DDR interface. The STM32 MP1 microprocessor also provides two PLL 800s. The architecture is very similar to the previous ones. Those PLLs are more dedicated for the generation of the medium speed clocks. The input frequency must be between 4 and 16 MHz. The VCO frequency must be in the frequency range of 400 to 800 MHz. Other functionalities are similar to the PLL 1600. The slide shows the relation between the input and the output frequency of the PLL for integer and fractional modes. The application shall take care to respect the frequency range for the VCO and for the clock frequency of the signal provided to the PLLs. The spread spectrum clock generator, or SSCG, performs a triangular frequency modulation of the VCO frequency using a 16-bit fractional divider. The application can adjust the modulation period via a mod per field, the modulation depth via a mod ink field, and the modulation mode via the SSCG mode field. This option allows the SSCG to generate a modulation either centered on the VCO frequency or lower than the VCO frequency. The SSCG is mainly used for the DDR interface as it is an important contributor to EMI interferences. This is due to the amount of IOs toggling at high frequency with steep edges. The SSCG does not significantly affect the jitter because the modulation frequency is very low compared to the speed of the DDR interface. The modulation frequency is generally in the range of 20 to 50 kHz, and the modulation depth is around 1%. The small plot shows an example of the effect of the clock spreading. Spreading the frequency over a limited frequency band spreads the power of the signal over this band, reducing the peak of power. The red signal is the VCO output without SSCG, and the black signal is the VCO output with SSCG. The oscillators don't deliver a clock if they are not ready. The ready flag is based on a temporization. This temporization is bypassed for the LSE clock when the LSE is in bypass mode. The control of the oscillators can be switched in secure mode when the TZN bit is set to 1. The HSE, HSI, and CSI oscillators provide a kernel clock dedicated to peripherals and a system clock. Those clocks are identical except the gating logic. The PLL1 and PLL2 can use either HSE or HSI as reference clock. The PLL3 can use either HSE or HSI or CSI as a reference clock. And the PLL4 can use either HSE or HSI or CSI or I2S CKIN as reference clock. The PLL1 is dedicated to the MPU. The DIVP shall be bypassed or use even division ratios in order to ensure a duty cycle of 50%. The PLL2 is dedicated to the AXI subsystem to the GPU and to the DDR. The PLL3 is dedicated to the MCU subsystem and to peripherals kernel clocks. Finally, the PLL4 is dedicated to peripherals kernel clocks. Each PLL has a dedicated pre-divider in order to adjust the reference clock for each PLL. Note that the PLLs clock source must not be changed if one of the PLLs is enabled. In addition, the generation of the MPU, AXI, GPU, and DDR clocks can be switched to secure mode. If desired, the generation of the MCU clocks can also be switched to secure mode. There are three main subsystems in the STM32-MP1 microprocessor, the MPU subsystem, the AXI subsystem, and the MCU subsystem. The clock provided to the MPU can be changed dynamically via the switch MPU-SRC or by changing MPU-DIV. The clock provided to the AXI subsystem can also be changed dynamically via the switch AXIS-SRC or by changing AXI-DIV. In addition, the frequency of APB-4 and APB-5 can be changed dynamically. The clock provided to the MCU subsystem can also be changed dynamically via the switch MCU-SRC or by changing MCU-DIV. In addition, the frequency of APB-1, 2, and 3 can be changed dynamically. The MPU can be clocked up to 650 MHz. The MCU and the multi-layer AHB can be clocked up to 209 MHz. The AXI clock shall not exceed 266 MHz. Other limitations are shown in the figure. After power-on reset, a system reset, an application, or an exit from standby mode, the MPU, the AXI subsystem, and the MCU subsystem are clocked with the HSI clock. The clock for the RTC-AWU can be selected among LSE, LSI, or HSE clock divided. Note that when the divided HSE clock is used as kernel clock for the RTC-AWU, the frequency shall not exceed 4 MHz. The RTC-SRC switch can be modified only once after a reset of the backup domain or after an LSE failure. Note as well that if the LSI clock is used as kernel clock for the RTC-AWU, the RTC-AWU will no longer be clocked in VBAT mode. If the divided HSE clock is used as kernel clock for the RTC-AWU, the RTC-AWU will no longer be clocked in standby or VBAT mode. It can be clocked in stop mode if HSE-KERON is set to 1. The LSE clock remains enabled in all low power modes, including VBAT mode. The RCC also provides two clock output signals, MC01 and MC02. A pre-scaler allows the application to adapt the frequency to the pad's capability. This feature allows the circuit to distribute its internal clocks to external devices. The RCC offers the possibility to estimate the frequency of CSI and HSI clocks with respect to HSE clock with an accuracy better than 0.3%. Timers 12 and 15 receive the calibration clock signal for that purpose. The timers count the amount of timer clock periods within a period of the calibration clock signal. The capture registers of the timers keep the last completed calibration value. Interrupt services are also available. Many peripherals in the STM32MP1 microprocessor have different clocks for the data and control flows via the processor bus interface and for the peripheral specific interface. Generally, the clocks for the data and control flows via the processor bus interface are named bus clocks and the clocks for the peripheral specific interface are named kernel clocks. The peripheral clocks represent the clocks received by the peripheral, bus clocks and kernel clocks. Having a separate bus clock and kernel clock allows the application to change the interconnect and processor working frequency without affecting the peripheral. For some peripherals, it is also possible to disable the bus clock as long as the peripheral does not need to transfer data to the system. So it gives good flexibility on the frequency selection for the bus processor and memories and for the real need of the peripheral interface. For example, the UARTs have a kernel clock which is used, among other things, by the Baud rate generator for the serial interface communication and an APB clock for the register interface. In addition, some peripherals are able to request the kernel clock when they detected specific events. The distribution of the kernel clocks is not detailed in this presentation. Please refer to the reference manual for specific details. Most of the peripherals using a kernel clock have a dynamic clock switch to select the optimal clock source. The proposed clock sources generally come from one of the PLL outputs from internal or external oscillators. This is mandatory for peripherals requiring a kernel clock when the system is in stop mode. From pads, for example, on peripherals using an external PHY, but also for audio as well in order to use a clock reference from an external device or from other internal peripherals for synchronization between blocks. The dynamic switching eases the transition between one source and another. RCC registers allow the configuration of the kernel clocks for all peripherals. Peripherals generally receive one or several bus clocks, one or several kernel clocks. Each processor can control the clock gating of the peripheral clocks via dedicated registers located in the RCC. The gating of the peripheral clocks depends on several parameters, the clock-enabled bits. Each processor has a dedicated enable bit named M-P-P-E-R-X-E-N and M-C-P-E-R-X-E-N. The low power clock enable bits, and the processor states C-Run, C-Sleep or C-Stop. Setting the bit M-P-P-E-R-X-E-N to 1 indicates that the peripheral P-E-R-X is enabled for the M-P-U. This operation is named allocating a peripheral. The next slides give additional information on the clock gating conditions. It is important to notice that the RCC offers two register sets, allowing each processor to enable or allocate peripherals to their own use. The peripheral allocation in the RCC offers two registers sets, allowing each processor to enable or allocate peripherals to their own use. The peripheral allocation informs the RCC that the M-P-U or M-C-U enabled a peripheral. This information is used by the RCC for the clock control in low power modes. So, before using a peripheral, the processors have to allocate it to their own use. The same peripheral can be allocated by both processors. It is up to the application to avoid resource conflicts. Some peripherals are implicitly allocated to a processor. The CISRAM, DDRC, DDRPHYC, and IWDG1 are implicitly allocated to M-P-U. The M-C-U can also allocate the CISRAM, but by default it is not allocated to the M-P-U. If the CISRAM is allocated to the M-C-U, the CISRAM is still available when the M-P-U goes to C-Stop mode. Otherwise, the CISRAM is being clock-gated. Some other peripherals are allocated to both processors. This is the case for the RCC, PWR, SRAM1, 2, 3, and RETRAM. When a processor has been allocated a peripheral, this peripheral's status depends on the processor state for the low power modes. The processor plus the peripherals allocated by this processor and the associated interconnect are considered by the RCC as a processor domain. To give a simple example of the use of the peripheral allocation by the RCC, a rule can state that the RCC will not allow a domain to be clock-gated if one of the peripherals of this domain is used by the processor of the other domain, which is in C-Run or C-Sleep mode. The following table is a simplified view of the system states versus processor states. The system is in Run mode when one of the two processors is at least in C-Run or C-Sleep mode. The system is in Stop mode when both processors are in C-Stop mode and one of them does not allow the entry in Standby mode. The system is in Standby mode when both processors are in C-Stop mode and both of them allow the entry in Standby mode. In System Standby mode, the VDD core is switched off. For more details on system states, please refer to the PWR training slides. When it is requested to go to Stop mode, the RCC performs the following operations. The RCC waits that the DDRC enters into self-refresh. Then the RCC stops all clocks. More precisely, the PLLs are disabled and the oscillators are disabled except if they are requested to remain active. And finally, the RCC informs the PWR that all clocks are gated. Then the PWR block can either reduce the VDD core voltage or keep the current VDD core voltage according to the way it is configured. When the system is in Stop mode, most of the clocks are disabled except LSE and LSI can still be running if enabled. HSE, HSI or CSI oscillators can remain activated in Stop mode if they have their Karen bit set to 1. This feature allows a very fast reaction of peripherals in Stop mode and also a faster exit from Stop mode. And HSE, HSI and CSI oscillators can also be activated on peripheral requests. The system leaves Stop modes thanks to events generated by peripherals able to work in Stop mode. Before entering Stop mode, the application shall program the EXTI in order to define which event shall exit the system from Stop mode. When a peripheral generates the expected wake-up event, then the EXTI informs the PWR that a wake-up event requests the exit from Stop mode. Step 2 in the drawing. The PWR block restores the PMIC state if needed and waits for a valid VDD core. Step 3 Once the VDD core reaches its nominal voltage, the PWR informs the RCC that exit from Stop mode can be performed. Step 4 The RCC enables the HSI clock if it is not yet available and provides the clock HCLK4 for the EXTI and PWR. Step 5 The PWR and EXTI can then define if the wake-up event shall wake up the MCU or the MPU. Step 6 and 7 Finally, the RCC restores the clocks to the corresponding processor and generates the corresponding wake-up interrupt. Step 8 When the system exits from Stop mode, the RCC provides to the MPU and the EXTI subsystem the same clock setting as before going to Stop mode. This means that PLL1 and PLL2 are re-enabled automatically if they were used before going to Stop mode. The RCC provides the HSI clock to the MCU for fast restart. If the wake-up event was for the MPU, then the RCC generated a wake-up interrupt for the MPU. If the wake-up event was for the MCU, then the RCC generated a wake-up interrupt for the MCU. Note that a programmable delay named PWR-LP-TEMPO can be configured in order to delay the activation of the PLL1 and PLL2. The restart of the MCU can also be delayed or not by PWR-LP-TEMPO according to the MCT-MPSKP bit. This feature can be helpful to adapt the circuit according to the capabilities of the external power devices. Some peripherals such as the U-Arts and I2Cs are able to asynchronously detect events requesting a kernel clock for processing. The RCC can provide on-demand a kernel clock to those peripherals when the CPU allocating the peripheral is in C-Stop mode or if the system is in Stop mode. The kernel clock request only works if the selected kernel clock source is an oscillator, HSE, HSI, or CSI. In order to speed up the activation time when a peripheral requests a kernel clock, the HSE, HSI, or CSI oscillators can be maintained activated during the system stop mode. In system stop mode, if enabled, the LSI and LSE clocks are always available for peripherals. A kernel clock is provided to the peripherals if one of the following conditions is met. One, when the CPU to which the peripheral is allocated is in C-Run mode. Two, when the CPU to which the peripheral is allocated is in C-Sleep mode and if it's LP-Enabled bit is set to 1. Three, when the CPU to which the peripheral is allocated is in C-Stop mode and if it's LP-Enabled bit is set to 1 and the peripheral is generating a kernel clock request and the kernel clock source is HSE, HSI, CSI, LSE, or LSI. Or four, when the CPU to which the peripheral is allocated is in C stop mode, and if its LP-enabled bit is set to one, and the kernel clock source of the peripheral is LSE or LSI. The bus interface clock is provided to the peripherals only when conditions one or two are met. The RCC integrates specific modes in order to control the low power transitions of the DDR controller, or DDR-C, and DDR-PHY. The software self-refresh mode, or SSR. The automatic self-refresh mode, or ASR. Or the hardware self-refresh mode, or HSR. In software self-refresh mode, the application has to directly program the DDR-C in order to switch the external DDR device immediately into self-refresh mode. The RCC just performs the gating of the DDR-C and DDR-PHY-C clocks, as it is performed for other peripherals. The automatic self-refresh mode must be used if the application programmed the DDR-C in order to switch the DDR in self-refresh mode if the DDR-C did not receive any transaction for an amount of time configured by the application. In this mode, the DDR goes to self-refresh mode when it is not used for a defined amount of time. When the DDR-C receives a new transaction, the DDR-C requests the DDR to exit from self-refresh mode. The counterpart is some microseconds more to exit from the self-refresh mode. In this mode, the RCC has two levels of clock gating. The RCC dynamically controls the gating of the DDR-C clock according to the DDR-State and independently of the processor state. The RCC dynamically controls the gating of the DDR-C and DDR-PHY-C clocks according to the DDR-State and independently of the processor state. This mode can only be used when the DDLs of the DDR-PHY-C are bypassed. For example, it can be used for an LP DDR2 working in the range of 125 MHz. The hardware self-refresh mode is using the AXI low power interface in order to control the DDR-C and DDR-PHY-C clock gating. In hardware self-refresh mode, the DDR automatically goes into self-refresh mode when the interface is disabled via DDR-C XEN bits, when the MPU transitions from C-run to C-sleep mode, or when the MPU transitions from C-run to C-stop mode. The DDR automatically exits from self-refresh mode when the interface is enabled via DDR-C XEN bits, when the MPU exits from C-sleep or C-stop mode, or when the DDR-C requests to exit from self-refresh mode. This could happen if another master is accessing one of the AXI ports. This mode tends to set the DDR in self-refresh mode when the MPU is in low power mode, but other masters such as DMA can exit the DDR from self-refresh mode if needed. In this mode, the RCC also has two levels of clock gating. The RCC dynamically controls the gating of the DDR-C clock. The RCC dynamically controls the gating of DDR-C and DDR-PHYC clocks. This mode can only be used when the DLLs of the DDR-PHYC are bypassed. For example, it can be used for an LP DDR2 working in the range of 125 MHz. The RCC provides two interrupt interfaces, one for the MPU and one for the MCU. The MPU interrupt interface can be switched in secure mode via T-Zen bit if needed. For each processor, the RCC provides a general-purpose interrupt and a wake-up interrupt. There are mainly three kinds of event. Clock failure events, oscillators and PLLs ready events and wake-up events. In addition to this training, you may find the power control and interrupt controller trainings useful. Thanks a lot for your attention.