 Hello, and welcome to this presentation of the STM32U5 Reset and Clock Controller, or RCC. The STM32U5 Reset and Clock Controller manages the system and peripheral clocks. This slide presents the three reset types and sources of reset. STM32U5 microcontrollers embed six internal oscillators to oscillators for an external crystal or resonator and up to five phase locked loops, or PLLs. Many peripherals have their own clock, independent of the system clock. The STM32U5 RCC provides high flexibility in the choice of clock sources, allowing the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication bot rates and also to keep some peripherals active in low power modes. Some peripherals support autonomous mode. They are able to generate a kernel clock request and an AHB APB bus clock request when needed in order to operate and update their status register even in stop mode. The system clock can be derived from the high speed internal 16 MHz RC oscillator, HSI 16, from the high speed external 4 to 50 MHz oscillator, HSI, from the multi-speed oscillator system, MSIS, or from the PLL1 RCK output of the PLL1. The AHB clock, called HCLK, is derived by dividing the system clock by a programmable prescaler. The APB clocks, called PCLK1, PCLK2, and PCLK3, are generated by dividing the AHB clock by programmable prescalers. The RTC clock is generated by the low speed external 32,768 KHz oscillator, LSE, the low speed internal 32 KHz RC oscillator, LSI, or the HSC divided by 32. This selection cannot be modified without resetting the backup domain. The LSE can remain enabled in all low power modes and in VBAT mode. The LSI can remain enabled in all modes including VBAT, except in shutdown mode. Various clocks can be output on input input output pads. The microcontroller clock output feature enables the external output of one of these nine clocks, HSI 16, HSC, MSI system, MSI kernel, LSI, LSE, CIS CLK, PLL1 RCK, and HSI 48. The low speed clock output feature enables the external output of the LSI or LSE clock, which is driven onto the low speed output clock, or LSE OPAD. The LSE output remains available in all stop modes, standby and shutdown modes, but not in VBAT mode. Note that LSI is not available in shutdown mode and that the LSI frequency is selectable through a control register, either 32 KHz or 250 Hz. Choosing 250 Hz allows lower consumption. This slide describes the features of five oscillators. The high speed external oscillator provides a safe crystal system clock. The HSI supports a 4 to 50 MHz external crystal or ceramic resonator, as well as an external source in bypass mode. A clock security system automatically detects an HSI failure. In this case, a non-mascable interrupt is generated and a break input can be sent to the timers in order to put critical applications, such as motor control, in a safe state. When an HSI failure is detected, the system clock is automatically switched to an internal oscillator, either HSI 16 or MSIS, so that the application software does not stop in the case of crystal failure. The high speed internal oscillator is a 16 MHz RC oscillator, which provides 1% accuracy in fast wake-up times. The HSI 16 is trimmed during production testing and can also be user-trimmed to take into account temperature and voltage variations. The HSI 16 can be automatically awoken when exiting any stop mode in order to make it available for peripherals when it is not used as the system clock. The HSI 48 is generated from an internal 48 MHz RC oscillator. 48 MHz is a canonical frequency for USB full speed module. HSI 48 can also be used as the reference clock for the RNG and SDMMC modules. The HSI 48 is associated with a special clock recovering system, CRC, circuitry, that dynamically adjusts the frequency according to the receipt of a USB full start-of-frame package or the LSE or an external signal. The secure high speed internal 48 MHz SHSI oscillator drives the secure AES coprocessor or SAS. The low speed internal LSI oscillator is the unique clock of the independent watchdog and can be the clock of the RTC. It can be kept running in all stop and standby modes. The clock frequency is either 32 kHz or 250 Hz. When using the independent watchdog, 32 kHz operation is selected and forced on. This table summarizes the HSI 16 oscillator electrical characteristics. The values are the same for all series. Minimum, typical and maximum frequencies are indicated for different operating conditions. The HSI 16 frequency can be trimmed in the application with a typical step of 29 kHz. Start-up time and stabilization times are also indicated. Note that the HSI 16 has a faster start-up time than the HSI crystal oscillator. Finally, the table provides the typical and maximum consumption of the HSI 16, considering that the HSI 16 can be switched off using the HSI on-bit. STM32U5 supports two multiple speed internal oscillators, the MSI system or MSIS and the MSI kernel or MSIK. MSIS is one of the oscillators that can be selected as the input clock of the PLLs. MSIK generates a clock that is independent of the system clock and therefore convenient for peripherals that require a fixed clock while the system clock may vary over time due to dynamic voltage and frequency scaling. MSI is made up of four internal RC oscillators, MSIRC0 at 48 MHz, MSIRC1 at 4 MHz, MSIRC2 at 3072 MHz and MSIRC3 at 400 kHz. Each oscillator feeds a pre-scaler providing a division by one, two, three or four. MSIS and MSIK frequencies are independently selected by programming the control register RCC-ICSCR1. In addition, when used in PLL mode with the LSE, the MSI provides a very accurate clock source that can be used by the USB full-speed device on STM32U5 series MCUs. The MSIS clock is used as the system clock after restart from reset, wake up from standby and shutdown low power modes. After restart from reset or when exiting shutdown modes, the MSIS and MSIK frequencies are set to their default value 4 MHz. When exiting the standby mode, the MSIS and MSIK frequency range is from 1 to 4 MHz. When exiting stop 0, 1 and 2 modes by issuing an interrupt or a wake up event, HSI 16 is selected as the system clock if the bit stop clock is set. MSIS is selected as system clock if stop clock is cleared. Wake up time is shorter when HSI 16 is selected as the wake up system clock. MSI selection allows a wake up at a higher frequency up to 24 MHz. The last point describes the two MSI modes, sampled and continuous. MSI is in continuous mode when the internal regulator is in voltage range 1, 2, or 3. The MSI is also in continuous mode when the internal regulator is in range 4 and low power modes when MSI BIAS equals to 0. MSI is in sample mode when the regulator is in voltage range 4 and in stop 1 or stop 2 mode when MSI BIAS equals to 1. By default, MSI is in continuous mode to maintain the accuracy of the output clocks. Setting the MSI BIAS bit reduces the power consumption of MSI in range 4 but decreases its accuracy. When a 32,768 kHz external oscillator is present in the application, it is possible to configure either the MSI-S or the MSI-K in PLL mode. In the case that MSI-S and MSI-K ranges are generated from the same MSIRC source, the PLL mode is applied on both MSI-S and MSI-K. When configured in PLL mode, the MSI-S or MSI-K automatically calibrates itself thanks to the LSE. Consequently, the MSI accuracy is the LSE crystal accuracy. At 48 MHz, MSI-K in PLL mode can be used for the USB full-speed device on some STM32U5 series MCUs avoiding the need of an external high-speed crystal. The figure on the right assumes that MSI-PLL mode is enabled for MSI-K and MSI-S when the frequency is 24 MHz. In this case, the MSI-RC zero oscillator clock is calibrated. The second frequency that can be selected for MSI-S, 2 MHz, is provided by MSI-RC1 and therefore PLL mode cannot be used. The stabilization time of the MSI oscillators configured in PLL mode depends on the MSI-PLL fast bit. When this bit is zero, 0.8 ms is required, whereas when this bit is one, the time is reduced to two cycles when LSE is already enabled and stabilization was previously done. This table summarizes the MSI oscillator's electrical characteristics. Minimum typical and maximum frequency values are indicated for operation at 30°C. The MSI frequency can be trimmed in the application with a typical step of 0.4% of the frequency. The drift according to temperature and voltage variations are indicated. These variations can be monitored in order to dynamically update the calibration parameter. Startup and stabilization times are also provided. Up to five PLLs integrated in RCC are completely independent. The three main PLLs have the same input stage. The input clock is either HSI-16 or MSI-S or HSE. PLLs can be used to multiply the frequency of these reference clocks. On the main PLL block diagram, the PLL input frequency must be between 4 and 16 MHz and the frequency at the VCO must be between 128 and 544 MHz. The value of the divider located after the clock multiplexer must be chosen accordingly. See the PLLX RGE parameter in the figure. The PLLs can work either in integer or fractional mode, which is an important new feature of the STM32U5. The 13-bit sigma-delta modulator fine-tunes the VCO frequency in steps of 11 to 0.3 ppm. The sigma-delta modulator can be updated on the fly without generating frequency overshoots on PLL outputs. This table indicates the maximum frequencies according to the voltage ranges. In voltage range 1, the maximum performance is obtained, 160 MHz system clock, possibly 200 MHz, for the octo-speri kernel clock. In voltage range 2 and 3, the maximum system frequency is respectively 110 and 55 MHz. In voltage range 4, the maximum frequency is 25 MHz and must be provided by an oscillator as PLLs are disabled. The 32,768 kHz low-speed external oscillator can be used with an external quartz or resonator or with an external clock source in bypass mode. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral, RTC, for clock calendar or other timing functions. The oscillator driving capability is programmable. Four modes are available from ultra-low-power mode with a consumption of only 510 nanoamps to high-driving mode. If the LSC is used by other peripherals or functions than RTC and TAMP, the LSC CIS-EN bit must be set. The peripherals that can be clocked by the LSC are the use-arts, the low-power UART-1, the low-power timers, the Cortex-M33 SysTick, the DAC-1. A clock security system monitors for failure of the LSC oscillator. It detects a missing clock or over-frequency. The CSS on LSC works in all modes including VBAT. It is also functional during system reset, excluding power-on reset. On all STM32U5 products, except on STM32U575, 585, RevX, CSS detection signal can generate an interrupt with wake-up from stop capability. The CSS on LSC failure is connected to a temporary vent. In case of failure, the application can switch the RTC clock to LSI. This is not automatic. This slide highlights some interesting features of the STM32U5 clock architecture. ADC-1, ADC-2, ADC-4, and DAC-1 modules share the same clock, which is the output of a multiplexer whose inputs are SIS-CLK, HCLK, PLL-2-RCK, HSC, HSI-16, and MSI-K. This shared clock scheme minimizes the VF-plus perturbations in the case of simultaneous conversions. The OctoSPI and HSPI input clocks are allowed up to 200 MHz when the PLL is used. This clock is faster than the Cortex M33 clock in order to maintain a high performance when the core executes code from the external OctoSPI memory. ICLK is the clock of the USB OTG full-speed module and one of the clocks that can be selected for the SDMMC controllers, the other one being PLL-1-PCK. A multiplexer selects the source of ICLK, either MSI-K, HSI-48, PLL-1-QCK, or PLL-2-QCK. Some peripherals support autonomous mode. They remain active while the microcontroller is in a lower power stop mode. These peripherals generate a kernel clock request and an AHB-APB bus clock request when needed in order to operate and update their status register even in stop mode. Depending on the peripheral configuration, either a DMA request or an interrupt can be associated to the peripheral event. Upon an AHB or APB bus clock request from an autonomous peripheral either the MSI or HSI-16 oscillator is woken up. If the autonomous peripheral is configured with DMA requests enabled a data transfer is performed thanks to the AHB-APB clock. The best clocks as well as the oscillator HSI-16 or MSI are automatically switched off as soon as the transfer is finished if no other peripheral requests it. The device automatically goes back in stop mode. The autonomous peripherals mapped on AHB-1, AHB-2, APB-1, and APB-2 belong to the CPU domain also called CD and are autonomous in stop 0 and stop 1 only with the GPDMA-1 and SRAM-1, SRAM-2, SRAM-3, SRAM-4, SRAM-5, or SRAM-6. The autonomous peripherals mapped on AHB-3 or APB-3 belong to the smart run domain also called SRD and are autonomous in stop 0, stop 1, and stop 2 with the LPDMA-1 and SRAM-4. This figure indicates which memories, masters, and peripherals belong to the smart run domain which remains fully functional in stop 2 low power mode. The SRD includes peripherals connected to AHB-3 and APB-3. The masters are the CD bus matrix which is idle in stop 2 mode and the low power DMA-1 that can be used to transfer data from peripheral to SRAM-4 or from SRAM-4 to peripheral without requiring to wake up the CPU domain. Note that the presentation on power management describes various scenarios involving DMA and peripherals working in autonomous mode. For more details please refer to application note AN2867, an oscillator design guide for STM8S, STM8A, and STM32 microcontrollers and application note AN5676 which explains how to calibrate STM32U5 internal RC oscillators.