 Hello, my name is Drew Festini. The Embedded Linux Conference North America and Europe are always a highlight for me every year. It's too bad we can't be together in Dublin, but I'm excited to be a part of it virtually. So I wanted to talk to you today about two of my favorite things, which are Linux and open-source hardware and how Risk 5 plays into that. I'm an open-source hardware designer at a PCB manufacturing service in the U.S., mostly on the board of directors of the Beagle Board of Dark Foundation. You might be familiar with the BeagleBone, which is a small open-source hardware Linux computer. I'm also on the board of directors of the Open Source Hardware Association, or AASHWA. We have a open-source hardware certification program that you can take part in. I'm also a Risk 5 ambassador for Risk 5 International, and I'll talk a little bit more about that organization later. There's Risk 5 virtual meet-ups all around the world, including Munich and Bay Area. And while they're not in person right now, you can find ones that are in your time zone at risk5.org. And coming up in December is the big annual event for Risk 5 called the Risk 5 Summit, which will be happening December 8th through 10th. I moved to Berlin while I'm from Chicago, but I moved to Berlin last year and I started the Berlin and Benelinds Meetup along with Lucas Hartman. If you're interested, join the group. We're not meeting right now, but when we're able to, we'll start meeting again, hopefully. And a really cool project that Lucas has been working on for several years now is the Reform Laptop, and it's finally shipping. It's a completely open source from the mechanical to the electronics to the software laptop. So what is Open Source Hardware? So it's hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design. So in the context of electronics, this means the schematics and the board layout are shared under an open source license. And this would be the editable source files. So if you're using Keycat or using Eagle, it would be the files from that program, not just an output format. And also the bill of materials are parts lists. And it's not a requirement, but the best practice is to use components that are available from distributors in low quantities. I've also been asked, you have to use an open source cat tool. And it's not a requirement, but it is the best practice because the idea here behind open source hardware is you're trying to enable collaborative development. So lowering the bar to entry so that you don't need, you can get parts in low quantity and you can use open source software to edit the designs. That's going to increase the number of people that can participate in their project. I talk more about open source hardware in certain aspects like licensing during this talk last December and you can watch the video. So I wanted to talk about risk five today and it's an instruction set or an ISA. This is the interface between hardware and software. So for example, you have a C++ program and it gets compiled into instructions for your processor to execute. But how does the compiler know when instructions the CPU understands? This is defined by the instruction set architecture. So the ISA is a standard. It's a set of rules define the task that the processor can perform. But proprietary ISAs like X86 and ARM, they require licensing so you can't just use them. So risk five is a free and open source instruction set. It started about 10 years ago at UC Berkeley by a group of computer researchers led by Krzysztof Sanovich. He gives a talk called the risk five state of the union a couple of times a year. So that link is to the latest one. So you might wonder what is risk? So risk stands for a reduced instruction set computer. So this goes back to a new concept of computer architecture from the early 80s and it's become quite dominant. For example, ARM is a risk, risk, risk instruction set and then you might wonder why the V or the five. So that's because this is the fifth instruction set to come out of UC Berkeley. But why do I say it's free and open? This is because the risk five specifications are licensed under the Creative Commons attribution license. So what's different about risk five? Because there's a lot of instruction sets out there. So the idea behind risk five was they wanted to start with a clean slate given all their experience from the previous generations of risk instruction sets that they had helped to find. The idea was to make it simple and far smaller than other commercial ISAs like Intel or ARM V8. And have a clear separation between unprivileged, which is like bare metal code in privileged ISAs, which is what you'd be using for running a full operating system. Another key concept was separating the specification from the implementation. So not having micro-architecture be part of the instruction set. So that you'd be free to implement it how you see best fit. It's also a modular ISA that's designed to be extensible and be able to be specialized. So there's a small standard base with multiple standard extensions, which makes it suitable for everything from a tiny micro-architecture to a big powerful secret computer. But it's also stable because the base and standard extensions are frozen and then additions are made via optional extensions. But it's not a new version of the base ISA underneath it. So there's four base integer instruction sets. The first of which is RV32i, which is 32-bit. Then there's less than 50 instructions. You can look there and if you looked at x86 or maybe ARM BA, this is much, much smaller. There's also an embedded variant that has smaller number of registers to save on resources. But probably the more common one will be RV64i, which is 64-bit integer. There's even 128-bit, which might seem a little silly, but the experience of the designers were that you can never have enough address space, that that's the thing that if you run an address space, it's really hard to work around that. And with non-volatile RAM capacities increasing, we may need that sooner rather than later. It's also beneficial for security reasons as well to have a large address space. So the RISC-V base gets added these standard extensions. So for example, there's M, which is multiply divide, A for atomic, which is useful if you have a multiprocessor system. And then you have different precision of floating point F, D and Q. And then G is for general purpose. So this is shorthand for integer multiply atomic flow in double precision flow. And then C is for compressed instruction encoding. And this helps conserve memory in cache and similar to you might be familiar with ARM thumb. And then there's also additional extensions that are being worked on, such as vector processing. But these won't require a new base version of the ISA. And then more practical for my interest, Linux distros like Debi and Infidora are targeting specifically RV-64GC. So that's the base, ISA, in the standard extensions that Linux distros are targeting. And the base and the standard extensions, these were frozen in 2014, and then they were ratified in 2019. So if you were to compile a program right now for RV-64GC in 20 years from now on some giants, RISC-5 fancy processor, it'll still be able to run. So to give you a sense of the landscape of the base ISA and the standard extensions, this is all the instructions on one card. And if you compare that to X86 or RV-8, I would say it's much smaller. If you want to get more in-depth in the instruction set, I recommend the RISC-5 reader. It's a pretty short book, about 100 pages, and it gets you up to speed really quick. It's also available in several different languages. So RISC-5 is seeing increasing adoption in industry. RISC-5 International now controls the specifications at RISC-5.org. They took over from the original group at Berkeley. It's a non-proven organization. It keeps on growing. There's less. Last I looked, there were 690 members. It's probably past 700 by now from 50 different countries. And this includes companies and universities and nonprofits. And you can, as an individual, join yourself. And it's free for individuals to join. It's free for nonprofits and universities to join. And one of the great things is the RISC-5 International has a YouTube channel with hundreds of talks from this last several years. And one of the ways I've learned a lot about RISC-5 is by watching those talks. So I highly recommend checking it out. One of the things that's quite exciting is that companies plan to ship billions of devices with RISC-5 cores. NVIDIA is already shipping RISC-5 cores for system management tasks in its GPU products. And Western Digital a couple years ago announced that they were going to replace all of the controllers in their storage project, storage products with RISC-5. And one of the reasons that they're doing this is to allow them to innovate in the micro-architecture. Like they have a core now that they're going to be using that has two hardware threads and a power efficient microcontroller. Another reason companies might be interested in RISC-5 is to avoid ISA licensing fees and royalty fees, including the legal cost. And then also to avoid the long delays that can come about with these complex licensing agreements. So it's not usually where you just go and download something. It's usually a rather long process to actually license the core and get it and start designing with it. RISC-5 also gives companies freedom to choose the micro-architecture implementation. So one thing to keep in mind is that only a few companies like Apple, Samsung and Qualcomm have ARM architecture licenses that allows them to do their own custom implementations of the instruction set. Everyone else is just licensing cores. And that doesn't give as much room to be able to differentiate their processor from other companies that are licensing the same core. Companies also have the freedom to leverage existing open source implementations. So since the instruction set is open, there's several open source implementations such as Rocket and Boom out of Berkeley. HH Zurich has the pulp team and they have several popular cores like Risky and Arion in Western Digital has their SWIRF cores, one of which is that microcontroller with two hardware threads, which is quite innovative. But one of the really important things when it comes to instruction sets and one of the reasons why Intel has maintained such dominance with x86 is the software. And RISC-5 is doing really well in that regard. There's already critical mass for software support with RISC-5. So Linux and BSD and GCC and G-Lib C and clang all support RISC-5, real time operating systems like FreeRTOS and Zephyr support RISC-5 and QEMU supports emulating RISC-5 as well. That link there that says well supported software that'll take you to a GitHub repo where RISC-5 Foundation keeps our RISC-5 International now keeps a list of the current state for all different languages and all the different libraries in operating systems with regards to RISC-5. And back at the embedded Linux conference North America in June, Chem gave a great talk about the state of software development tools. So I recommend checking that out as well. So RISC-5 International is based in Switzerland before that there was the US based RISC-5 Foundation. And at the beginning of this year they re-incorporated in Switzerland. And this was to avoid any political issues since many of the members are outside of the US. So with Switzerland they won't have to worry about those sorts of issues. In RISC-5's also become very interesting at the national level. So organizations like the European Union and nations like India and Pakistan have national initiatives to do RISC-5 processor designs. And this is driven by the desire to have sovereignty over technology and also be able to avoid backdoors from other nations. There's also strong interest from chip makers in China. So US companies were banned in 2019 from doing business with Huawei. So you have to think that other Chinese companies are probably wondering who is going to be next in terms of these restrictions. Thankfully for Huawei, ARM is deemed to be a new key origin technology. So it was okay to do business with Huawei, but you know how long will that last and how will the Nvidia acquisition impact all this. So that uncertainty is really driving more and more companies to look at RISC-5 as a way to reduce the uncertainty when it comes to their ability to have their technology roadmaps go forward. So sometimes I hear people ask is RISC-5 an open source processor or an open source CPU? And that's not quite right. So RISC-5 is just a set of specifications under an open license. So the RISC-5 implantations can be either open source or proprietary. But open specifications make open source implementations possible. So we can't have an open source processor for a proprietary ISA like X86 or ARM. So RISC-5 being open makes it possible for us to have open source processors. The RISC-5 privilege architecture has three different modes. So there is the machine mode or M mode, which is kind of the bare metal, which is where you'd have the boot loader or firmware. Then there's supervisor mode or S mode. That's where the OS kernel like Linux would be running. And then finally there is user mode or U mode where applications run. Then there's support for different combinations of these. So M would be just your simple embedded system that's running bare metal. M and U would be an embedded system with memory protection that probably running in R-TOS. And then M, S, and U together would give us a Unix-style operating system with virtual memory. And there's also a hypervisor extension in draft. And that would give us a modified S mode called HS. So the RISC-5 boot flow is similar to probably what you've seen with architecture like ARM, where you have the zero stage boot loader in the SOC ROM. And then you might have a small first stage boot loader that eventually then goes into U boot as the final stage boot loader that jumps into Linux. But something you might not be familiar with on this diagram is OpenSBI. So SBI stands for Supervisor Binary Interface. And this is something as specific to RISC-5. It's the calling convention between the supervisor or S mode OS. So like the Linux kernel and the supervisor execution environment, which would be the bare metal code in M mode. And this allows the supervisor mode software to be written, so that's portable to all different RISC-5 implementations. So the RISC-5 architecture support in the Linux kernel isn't tied to specific RISC-5 implementations as abstracted away by SPI. SPI came out of the Unix-class platform spec working group, which is now chaired by Al Stone of Red Hat. There's frequent meetings, so if you do join RISC-5 International as a memory, and you can do that free of cost, then you can start participating in these meetings and joining the mailing list and keeping up with what's going on. It's now transitioning to something called RISC-5 profiles and platform to be more generic than being specifically about Unix. So OpenSBI is the open source implementation of SBI. And the idea here is to be the de facto implementations. We avoid a fragmentation of different SPI implementations. So SPI is the specification and then OpenSBI is the code that actually implements that specification. And the way that it can hopefully avoid fragmentation is by providing different layers of implementation. So at its core, it's just a library for SPI, the standard. And then on top of that, there's platform-specific libraries for different SOCs. And then there's also a full platform-specific firmwares. So by using this layered approach, it can be adapted for whatever works best for the vendor. OpenSBI provides runtime in M mode, so it's running in that machine mode. And it's typically used in boot stage following the ROM loader. It provides support for reference platforms and also has generic simple drivers for M mode to operate. And something that's very common in the x86 world and is becoming increasingly common in the ARM world, especially like ARM VA for 64-bit ARM, is UEFI. And UEFI is now supported in the RISC-5 role. So the last piece was having UEFI support in RISC-5 and that has landed in 510, which should be released by the end of the year. There's already support in Grubb and Uboo for UEFI on RISC-5. And there's also a RISC-5 EDK2 port that's now upstream in TianoCore. So in short, all the things that you need for RISC-5 and UEFI to go together are there now. RISC-5 also has full emulation in QEMU. It's in mainline and it can boot both 64-bit and 32-bit Linux kernels. QEMU can run OpenSBI, Uboo, and Coreboot on RISC-5. It also supports draft versions of the hypervisor and vector extensions. And the QEMU sci-fi machine can boot the same binaries as the physical sci-fi board, which I'll talk about in a few minutes here. This is a tutorial you can go through about how to run both the 64-bit and 32-bit RISC-5 Linux environment under QEMU. So the Linux kernel was ported to RISC-5 by Palmer and that landed back in 4.15. The development's all done on the RISC-5 mailing list. And you can also, so you can join that. And then you can also check out the archive as well and lore. A great talk earlier this year at the Munich RISC-5 meetup from Bjorn Topol talked about what's missing currently in RISC-5 Linux and what you can do to help. And he made the point that because it's a newer port, it's a great way to learn the nitty-gritty details of the Linux kernel. And it's a fun, friendly, and it's still pretty small community compared to how large the Linux development community is as a whole. And he generated these graphs just to kind of show a comparison here between ARM64 AR64 slash ARMVA and RISC-5. So you can see RISC-5 starting here in 4.14. It's far below the number of commits for ARM64. But when we adjust the beginnings, we can see that it's maybe keeping pace with ARM64 if we get more people interested and more people helping to develop it. And Bjorn had a nice list here of you can run this script in the Linux kernel source directory. And you can see all the kernel architecture features that are still missing or to do for RISC-5. So some of the recent and ongoing work for the RISC-5 port of the Linux kernel. KVM is actually pretty much all done now by Anup and Atish from Western Digital. It's really just waiting on ratification of that hypervisor spec in RISC-5 ISA. There's the EPPFJet and everyone loves EPPF these days. There's also GDB support, Kexec, Kdump, Kprobes and Krepprobes for Ftrace, which I become a big fan of. I highly recommend that if you've not tried that out yet. It's very useful, not just for RISC-5, but just in general. So you don't spend all day having to add in-print case when you're trying to troubleshoot things, generic VDSO support, syscaller support for fuzzing, and then also being able to build with claying instead of GCC. So we talked about the Linux kernel, but what about Linux distros? So Fedora has a project called Fedora RISC-5, which is a port of Fedora RISC-5. And the aim here is to provide the full Fedora experience. And then we're working on this for several years right now. So one of the ways that they do this is by providing Fedora images that can be booted on QEMU, if you don't have any hardware. There's also this board called the Sci-Fi Von Lisch board, and there's a few of them. They're kind of rare, and I'll be talking more about it in a bit, but that's another way that they run it on it. So for Fedora, they're using both a mix of virtualization, powerful like x86 servers, and then a limited number of these kind of expensive pieces of hardware. And there's installation instructions for how you can run through and boot up Fedora RISC-5 under QEMU, so like on your laptop or your desktop PC. Debian has also been working on the port. So Debian has a port. And for Debian, a port means that it can run the huge Debian archive, which is like 20,000 packages. The goal here is to be able to install and run all those packages. And this is a graph that comes off the Debian ports website, and that gray line near the top there is RISC-5. So it's about 95% of those 20,000 packages are now building for RISC-5, which is I think a great sign. And if you don't need a full Linux distro, there's support and open embedded in Yachto project with meta RISC-V, which I think is, Kim Raj helps out a lot with that. There's also Buildroot. So the support is now in the upstream Buildroot project for RISC-5. And if you want to try it out a bit, Michael from Bootlin has a great embedded Linux from scratch in 40 minutes on RISC-5 tutorial that takes you through the process. So we talked a lot about the software and how we can emulate stuff in QEMU, but like we like hardware, right? So like what are the actual chips out there? So Sly-5 is a startup founded by members of the Berkeley RISC-5 team. And then back in 2018, they debuted the FU540. So it was the first RISC-5 SOC or system on chip that could run Linux. So it's had four 64-bit cores that were running up to 1.5 gigahertz, and also one simpler low power core for system management tasks. It has 64-bit DDR4 interface and then some peripherals like gigabit, ethernet. Unfortunately, not USB though. And then also in 2018, the Sly-5 Freedom on Leash board launched. So this was the first Linux-capable RISC-5 dev board. They actually were showing it off at ELC North America when it came out, and we were all very excited about it. The board design itself is open source hardware, which is nice. It was the highest performance available yet. So the SOC has clocked it probably 10 times faster or more than FPGA soft cores. So it's significantly more performance than it was possible previously. However, it was pretty expensive. It would cost $1,000, and unfortunately, it's no longer available. In the chip itself, the SOC from Sly-5 was never sold separately. But the reason for that is Sly-5's core business is designing cores and licensing cores. They're not in the business necessarily of selling SOCs or selling dev boards. That's more something that their customers do. In a little bit of point of clarification here, the term ASIC is often used to refer to an SOC that has a hard processor core that's constructed with traditional silicon fabrication. This differentiates from soft core, which you would have an FPGA. And these, due to their nature, run at significantly slower clock speed. So when we say ASIC, we mean a core that's running quite fast as compared to a soft core and FPGA. And you can actually, if you have the necessary hardware, though it's kind of rare and expensive, you can boot the Fedora GNOME image on this Unleashed board with an expansion board and graphics card. And you get a full Linux desktop. So it's a full Linux graphical desktop on RISC-5, which is pretty neat. But for now, it's a rather expensive hardware setup. But I think the key there is we now know that it works. And we know as the hardware continues to become more available, you'll be able to do this sort of functionality. So one of Sly-5's customers is Microchip. And they designed a SOC similar to the Sly-5 U540. But they also added an FPGA fabric, which is quite interesting. So that gives you a lot more options in terms of hardware design. It has DDR3 and DDR4 interfaces. It has PCIe Gen2, also USB, which is nice, and then two gigabit ethernets. And this is a full commercial product family from Microchip. That's available right now from distributors. And it just launched in like the last month. And if you're wondering, I didn't know Microchip made FPGAs. This is actually formerly MicroSemi, which is now a division of Microchip. And the dubboard to go along with this is called the Icicle. It's available for $500 on crowd supply. And it's shipping not of the people that signed up for the pre-order back in July. And soon it'll be available from the normal distributors, Digikey and Mauser and such. The specific variant they chose for this dubboard, the RIS-5 cores are clocked at 600 megahertz. And it has the larger FPGA variant. So it's possible we'll see cheaper boards in the future that are built around the smaller FPGA parts in this family. It has two gigabytes of RAM on it and eight gigabytes of EMMC to have Linux already installed on it. In fact, I got a preview of one and it comes with open embedded based Linux already set up and booting on it, which is quite fun to see. So maybe you don't have $500, it's just not in your budget, right? So the Kendrai K210 is quite interesting low cost processor. It's a 400 megahertz dual core 64-bit RIS-5 system on chip. It has eight megabytes of SRAM, which is a lot of SRAM, but unfortunately it doesn't have a DRAM interface. There's affordable dev boards available from SIPEDE, such as the one I'm holding here, which is the SIPEDE Max Bit, which is only $13, which is quite nice. Full support's been added in Linux 5.8 for it. This was based on work that some people like Damian Lamal and Christoph Helwig had done. The trick here was to get it to run in such a constrained system. Sean Anderson has support now on U-boot upstream for two of the boards. And build routes used to construct a root FS for it that has busybox. That was done by Damian. It's in the process of upstreaming in the mailing list. And there's a great tutorial from CNX Software that takes you through all the steps you need to do to build the kernel and build the root FS and load it up onto the board. But it's only eight megabytes, so it does run out pretty quickly. Unfortunately, so there is an MMU in this SOC, but unfortunately, it's for a earlier draft spec that's not supported by Linux, which basically means we have to run as MMU lists. The downside here is that that means for user space, there's no shared libraries, which means that we don't really have much space to do anything practical, because we have to have every process has to have copies of the library separately. The solution to that is something called FDpick. And this is what's used for MMU lists on ARM microcontrollers that can run Linux. And a person at Western Digital is working on this. But it's a relatively constrained system. But if you're interested in playing around and getting familiar with RISC-5 on Linux, you know, for $13, I think it's something to check out. And you can do a lot with it for not a lot of money, in terms of exploring like OpenSBI and the kernel and in the libraries and tool chains and things like that. Here's me a few months ago running what was at the time, Mainline Linux, the Cypede mech spit board there with the KT10. So, you know, you're not going to throw out your Raspberry Pi or your Beaglebone, but I think it's an interesting thing to experiment with if you're interested with Linux and RISC-5. Something maybe more practical that's going to be coming up is a project called PicoRio. And this comes out of an organization called Rioslab, based in China, that's a collaboration between the University there and Berkeley. And their goal is to create a low-cost Linux capable RISC-5 platform. And this was introduced back in September at the RISC-5 Global Summit. And they have three phases planned. The first phase of the PicoRio board is to have some samples available by the end of this year. So that's pretty exciting. I think myself and all ours were quite excited when they announced this at the Global Summit. So the idea of more affordable boards coming out I think is really exciting because, you know, just some people aren't going to be able to afford, you know, $500. And we want to get as many people as possible being able to try out RISC-5, importing their software to it, to make it really become more widespread and more common. PSY-5 also has plans to announce a RISC-5 PC on the 29th. So when you watch this presentation, that's only going to be a couple of days from now. There's going to be two talks from some of the founders of PSY-5, and they'll be speaking more about this. It's based around a new SOC from PSY-5, which implements the vector extension. So I think it's the sort of thing that will be able to accelerate inference for AI workloads and things like that. So I don't know what it is yet, but it should be exciting and keep tuned for that. Though I don't, I suspect it won't necessarily be super low cost, but it will be probably pretty significant in terms of the capabilities and power. And then the best RISC-5 chip that I know of that's coming soon is from Alibaba. Alibaba has a chip design division called THead, and they've created a 16-core 2.5GHz RISC-5 processor. They had an interesting paper that came out during Hot Chips about it. If you search for this, you'll find it in Google. And I link to some other articles about it. There's the current draft of the vector extension that's implemented in it, which means it'll also be able to handle things potentially like AI workloads doing inference and matrix operations and things like that. This is expected to debut next year, and also possibly have a dev board as well. But there's not too many options when it comes to chips for running Linux on RISC-5. So one of the alternative tips to that is to use an FPGA. So an FPGA is a field-programmed locator array. So you can think of it as a chip that's just a sea of or an ocean of logic elements that can be rewired to implement whatever logic we want them to. And if we have enough of them, if we have a big enough FPGA, we can even implement a processor core or what's called the soft core. If you're new to the idea of FPGAs, a great talk last year from Hackaday Super Conference was by Dr. Megan Wachs of Sci5. I have a link in there, you can check that out. So one of the problems with FPGAs, like I learned them in school a while back, and you had to use these giant proprietary IDE installations from the vendors. And it took up a lot of space and they weren't necessarily that great piece of software, maybe Windows-specific, but that's changed now. But anyways, some awesome hackers such as Clair Wolf got together and started making a lot of progress in terms of having open source tool chains that can target these FPGAs. So the first one was a small one called Ice 40 from Lattice. And that was part of Project Ice Storm that Clair Wolf led. Now it's followed up by a bigger part from Lattice called the ECP-5. And that was done with a thing called Project Trellis. However, the majority of the FPGAs in the market and the more powerful ones are from Xilinx. So Project X-Ray and Symbolflow are targeting Xilinx Series 7. And Tim Mansell tells me that this is almost ready for prime time. And you can think of it kind of as GCC for FPGA. So the idea here that we have, instead of having to use proprietary tools from the FPGA vendors, we have open source tools to target the FPGAs. So I want to talk specifically about a project that I was involved in with some other people last year. So there's an awesome hardware hacking conference every fall normally. This year it's virtual called Hack a Day Super Conference. And as it has become tradition at hardware conferences and hacker conferences is they have the electronic conference badge and displays your name or plays games or does interesting things like this. This past year we had one with the ECP-5 FPGA. So that's one of the FPGAs that's supported by an open source tool chain. And for the conference it was running a RISC-5 soft core and I had a games engine and you could do all sorts of nifty graphics things with it. But myself and several others were like well that's nice but we wanted to run Linux. So me and several other people got together over the course of the weekend of the conference and tried to see if we could get Linux running on it. The first thing we tried was to use the built-in SPI SRAM chips that were in there but that didn't work out very well. But it was a hardware hacking conference and Jacob Creedon came prepared. Before the conference he saw the design of the badge and made an add on board which is called the cartridge because it was that Game Boy form factor that gave us 32 megabytes of SD RAM. And this is much better like Linux does not really want to run out of SPI connected SRAM like SD RAM is much much better for that. And this is what it looks like when the cartridge is plugged into the back of the badge. And I thought this was quite interesting. Also a great follow on Twitter if you're into FPGAs. Is this is what it looks like when you've wired that ocean of gates or logic elements inside the FPGA to represent a RISC-5 processor core. So I thought it was just kind of giving it interesting to see the macro level. What does it look like when you have all those elements wired up to be a processor core. But in our case we use Python to do this which you might be surprised that you would design a system on chip with Python. So Python has advantages over traditional hard description languages like VHDL which I learned in school a long time ago in Verlog. Many people are already familiar with Python versus the syntax of these HDLs. And I think it's fair to say that there's more software developers nowadays than hardware designers which means if these tools for chip design are easier for software developers to get into we can potentially expand the number of people that are doing hardware design. So specifically Nijan is a Python framework that can automate chip design. So it leverages the object-oriented nature of Python. And it actually produces Verlog code that can be used with existing chip design workflows. So all the other complicated tools that are in the flow of getting a design into an FPGA or getting a chip design off to a fab those all typically expect something like Verlog. So we're just doing the design in Nijan and that produces Verlog. So we don't have to change all of our other tools but we can design in something that's maybe more powerful for us. There's a great talk by Tim Ansel about how he used Nijan in Python to design hardware for recording conferences. So here's a nice example from a tutorial on Nijan that shows us a D flip flop which is a very standard digital electronics concept. And here it is implemented on the left in VHDL. And then here it is implemented on right in Nijan. And I think to me I think the Nijan example is a little bit more understandable to me. You know that maybe because I do a lot more software development than I do to chip design. But I think for the majority of people the one on the right is going to be a little bit more approachable. Which is why I think Python can have a lot of utility and Nijan can be very useful for getting more people into chip design. On top of that we use this thing called Litex. This allows us to build a full system on chip that gets loaded into the FPGA. So in addition to Nijan which allows us to do chip level design in Python. It also adds an ecosystem of cores that give us things like Ethernet controller, DRAM controller, PCI Express controller, SD card video. So all the different pieces that you would have in a system on chip design. There's different modules and we can pick and choose the ones that we need for our application. Specifically how we got Linux loaded onto the ECP5 in the badge actually turned out to be easier than you might think because we leveraged a project called Linux on Litex VexRisk 5 which is a bit of a mouthful. But VexRisk 5 is a 32-bit open source implementation of a RISC 5 core. And it's designed to be FPGA friendly which means that it doesn't, it's conservative in terms of the resources that are precious in FPGA versus ASIC. And it's written in this higher level language called Spinal HDL. And Linux on Litex VexRisk allows us to build an SOC that takes the VexRisk core and combines it with the Litex modules we need to have a full system. And it also, you know, I'm talking about the Hackaday badge which probably none of you have, but it does support a large number of FPGAs on different dev boards. So some of the really common FPGA dev boards which maybe you have in a drawer may already support, Linux on Litex may already support it. And it's really just as simple as cloning this repo, like running a couple commands and then you can either simulate it on your system which is pretty slow or you can load it into a supported FPGA board. And here it is on the badge. So the badge, the serial port in the badge is hooked up to a terminal emulator on my computer. You can see there that the bit stream has been loaded into the FPGA. The kernel has been transferred over, booted up on the soft core and we have our terminal prompt here in busybox. Once we got back from the conference I thought it would be nice to upstream support for this badge. Now, maybe not that useful because, I mean, probably only five people want to do this, but it's a good example of how to add a board to Linux on Litex. To give you a flavor of what it looks like to have like chip level design in Python. This is something called the pin constraints file in the Megen syntax. And then one of the things that was, I thought a nice example of how Litex is powerful is we had an SD RAM chip that wasn't supported yet. But all we had to do was inherit the base class and then just add in the data that was specific to the timings in the data sheet for the SD RAM module. So that's all we had to add to get this new SD RAM chip supported. However, it took like five minutes to boot up, which was not very much fun. So I opened up an issue in Florence who goes by enjoy digital as the maintainer. He's really wonderful. And within like an hour, he posted a fix that made it go 10 times faster, which was great. And just to go back to why I think Python can be quite useful for doing like chip level design like this, like this is the diff, which to me, I can look at that. And I can see that he changed something in the L2 cache. In this instance, it was to make it wider so that it would have to access memory less because SD RAM is pretty slow in comparison to DDR, which most of the other boards are using. And then you notice there is display there and it'd be sad if we weren't using display. So Greg Davil, who's an awesome hardware hacker in Australia, he eventually got the LCD working there. So you probably don't have the badge, but there are a couple of options when it comes to ECP five open source dev boards. One is from a hacker space in Croatia that launched a crowd supply called the ULX 3S. And that's available right now. There's also the orange crab by Greg Davil. And I really like this board because it has 120 megabytes of DDR RAM. So not only is it faster, but you also have much more memory. So Linux will run faster on it. It's also in this neat little small form factor called Feather. But you know, if you're not familiar with FPGAs, you haven't worked with them in a while, like a big FPGA with the soft core running Linux plan out the best place to start. So I highly recommend checking out the FOMU. There's an online workshop for it. It fits inside your SD your USB ports, you can take it everywhere. And it takes you through the example of blinking LED and micro Python and then verlog and then light up. So it's a nice way to get into this whole new road of FPGAs. And if you don't have any hardware, just your computer, you check out Renoad. It's a great piece of software from Ant Micro is an open source project. And it can simulate not only the CPU, but peripherals and sensors. And it can even simulate a network of different nodes. And it has profiles for different dev boards. So like I remember, I said the sci five high five unleash board is is rare and pretty hard to get an expensive. Well, I don't need it necessarily. I can use Renoad in my laptops that only becomes the board, which is pretty awesome. To leave you with here's an interesting concept that I came across. So the idea of a self hosted trustworthy computer. So Gabriel Samlo at Carnegie Mellon has this concept of, okay, we have these open source FPGA tools, which allows us to build a soft core that goes into an FPGA that run Linux. And these open source FPGA tools can run inside a Linux so we can create a system that can build itself that can bootstrap itself, which I thought was quite interesting concept. Definitely check out his talk there about building a more trustable self hosting computer system added in a couple slides here just to tempt you to to watch the talk. And I think that's about all my time for today. So I'm happy to take questions, which I believe is going to be in a chat dialogue in this interface. And then also we should have a slack set up where we can continue talking hopefully throughout the rest of the conference. Thank you for joining me and look forward to chatting with you all virtually. Bye.