 Hello everyone, this is Vishwana Chavan, Assistant Professor, Department of Computer Science and Engineering, Walton Institute of Technology, Solapo. Now I am here to explain the topic Pipeline Processor. At the end of this session, the students will be able to describe the working of pipeline, its different stages and performance. To improve the performance of a center processing unit, we have two options. The first one is with the help of hardware by introducing faster circuits. So faster circuits, which is going to support for enhancing the speed and performance of a CPU. Second option is arranging the hardware such that more than one operations can be performed at the same time. So these are the two options to improve the performance of a CPU. Since there is a limit on the speed of a hardware and the cost of faster circuit is quite high. So and hence we are supposed to adopt the second option. So what exactly pipeline? It is a process of arrangement of hardware. In such a way that CPU performance will be increased. And simultaneous execution of more than one instruction is taking place. We will see the design of basic pipeline. In a pipeline processor, there are two ends. One is input end and second one is output end. In between these two ends, there are multiple stages or segments such that output of one stage is connected to input of next stage and each stage performs a specific operation. Interface registers are used to hold the intermediate results and they are also called latch or buffer. There is a clock, all stages in the pipeline along with the interface register are controlled by a clock circuit. Let us see the different pipeline stages. The first stage is instruction fetch. In this stage, the CPU is going to fetch the instructions from memory location and which is addressed by a specific register called program counter. So the instruction which is fetched from the memory is stored in instruction register. This is the first cycle. The second stage is about instruction decoder. In this stage, the instructions are decoded and the register file is accessed to get the values from registers used in the instruction. The third stage is about execution which is called instruction execution. In this stage, the arithmetic and logical operations are performed. Moving to next stage, fourth stage which is called memory access. In this stage, the memory operands are read or written from or to memory. That is present in the instruction. Stage 5 which is called write back. In this stage, the computed or fetched values is written back to the register present in the instruction. So these are the 5 main stages of a pipeline. Let us see the execution in a pipeline processor. So normally the execution is in terms of space-time diagram. Let us see more detail. The execution sequence of instructions in a pipeline processor can be normally visualized with the help of space-time diagram for example. So if it is based on non-overlapped execution, it looks like this. Then I1 which is having 5 stages, instruction fetch, instruction decoder, execution, memory access and write back. So these are the 5 clock cycles required to execute I1. Since it is a non-overlapped, I2 will begin from clock cycle 6. So fetching of I2 takes place in clock cycle 6. Then decoding, execute, memory access and write back. And hence in non-overlapped execution, it takes for 2 instruction 5 plus 5 total 10 clock cycles are required to execute. This is the case about non-overlapped execution. Now we will focus on if it is overlapped, that is the pipeline, how it looks. So this is the diagram. Let us take 4 instructions. Since it is an overlap execution, the fetching of first instruction takes place in clock cycle 1, decoding in second clock cycle, execution in third clock cycle, memory access in 4 clock cycle and write back in 5th clock cycle. While decoding of first instruction, fetching of second is taking place. Then decoding, execute, memory access, write back. Similarly, in third clock cycle fetching of third instruction, in 4th clock cycle fetching of 4th instruction. Now if you observe this diagram, after 5th clock cycle, we will find that for every clock cycle there is a output of its respective instructions. That is in clock cycle 5, I1 result is available. In next clock cycle, I2, in next clock cycle, I3 and in 8th clock cycle, I4. So in the pipeline, after the 5th clock cycle, for every clock cycle we are getting the results of respective instructions. This is what the main difference between overlapped and non-overlapped. Now think about this question, pause the video and write down the answer. The question is, what are the different pipeline stages? I hope your answer for this question. The answer is stage 1 instruction fetch, stage 2 instruction decoder, stage 3 instruction execution, stage 4 memory access and stage 5 write back. Let us see the performance of a pipeline processor. Now we already came across how overlapped instructions are executing. Now we will focus on performance. Let us consider k segment pipeline with clock cycle time as tp. tp strands time taken to complete one clock cycle and k strands number of clock cycle required to execute the instruction. Let there be an end task to be completed in the pipeline processor in the sense that n is the number of instruction which are supposed to be executed. Now the first instruction is going to take k clock cycles to get the result and the other remained n minus 1 instruction they will take one clock cycle for each instruction that is total it takes n minus n minus 1 clock cycles. So time taken to execute the n instructions in a pipeline processor is nothing but k plus n minus 1 cycles and each cycle takes time tp and hence into bracket k plus n minus 1 into tp that gives total time taken to complete the all the instructions. In the same case for a non pipeline processor the execution of n instruction will be n into k into tp. The speed up of the pipeline processor over non pipeline processor when n task are executed on the same processor is s is equal to performance of a pipeline processor divided by performance of a non pipeline processor. As the performance of a processor is inversely professional to the execution time we have s is equal to ET non pipeline divided by ET pipeline that is s is equal to n into k into tp divided by k plus n minus 1 into tp and hence s is equal to n into k divided by k plus n minus 1 where n is greater too much greater than k and hence s is equal to n into k by n that is equal to k where k are the number of stages in the pipeline. Let us see the efficiency which is equal to given speed up divided by maximum speed up which is equal to s by s max. We know that s max is equal to k and hence efficiency is equal to s by k. Let us see the next term throughput number of instructions by total time to complete the instructions. So throughput is equal to n divided by k plus n minus 1 into tp note that cycles per instruction value of ideal processor is one these are the references I have used thank you.