 Hello, and welcome to this presentation of the STM32 System Window Watchdog. It will cover the main features of this peripheral used to detect software faults. The Window Watchdog is used to detect the occurrence of software faults. The Window Watchdog has a programmable free-running down counter that must be refreshed within a window period that guarantees proper software execution. If a problem occurs and the program time period expires, the Window Watchdog generates a system reset. The Window Watchdog can be programmed to detect abnormally late or early application behavior. Once enabled, it can only be disabled by a device reset. The Window Watchdog is best suited for applications required to react within an accurate timing window. This time window is configurable and can be adjusted according to various use cases. The Window Watchdog can be configured to start either by hardware or software via the option bytes. An early wake-up interrupt can be generated before a reset happens to perform a system recovery or manage certain actions before a system restart. When the Window Watchdog is activated, a reset can occur when the down counter value becomes less than 0x40 or when the down counter is reloaded outside the time window. An early wake-up interrupt can trigger any action when the down counter reaches 0x40. The EWI status register can be used to reload the down counter to avoid generating a reset or to manage system recovery and context backup operations. The PCLK clock from the RCC clock controller is used to clock the Watchdog peripheral. Bits T6 to 0 from the Watchdog control register count down until they roll over from 0x40 to 0x3F, which then generates a reset. Bits W6 to 0 from the Watchdog configuration register contain the window value. Bits T6 to 0 and W6 to 0 are compared in order to evaluate the time to refresh the down counter in the configurable window. If the down counter is reloaded too early or too late, the Window Watchdog will initiate a reset. This diagram illustrates how the Window Watchdog operates. When the 7-bit down counter T6 to 0 bits roll over from 0x40 to 0x3F, it initiates a reset when the T6 bit is cleared. This happens when the application software did not react within the expected time window. If the software reloads the counter while the counter is greater than the value stored in W6 to 0 bits, then a reset is generated. This happens when the application refreshes the counter too early. To prevent a Window Watchdog reset, the reload value T6 to 0 bits must be written while the counter value is lower than the time value window W6 to 0 bits located in the green area. To enable the Window Watchdog clock, set the WWD GEN bit in the RCC APB1 ENR1 register. The Window Watchdog timebase is pre-scaled from PCLK1 APB1, whose maximum frequency can go up to 80 MHz. This clock frequency is first pre-divided by 4096 and the Window Watchdog pre-scaler can divide it again by 1, 2, 4 or 8 as defined in the WWDG CFR register. The formula shown in the slide lets you determine the Watchdog timeout which is derived from the PCLK1 period and the WDGTB pre-scaler as well as the selected Watchdog counter reload value. The minimum and maximum timeout values can be between 51.2 microseconds and 26.2 milliseconds. Once the Window Watchdog generates a reset, a status flag, WWDGR STF is set in the RCC CSR register identifying the source of the reset. The early wake-up interrupt can be used for specific safety operations or when data logging must be performed before the actual reset is generated. The EWI interrupt occurs whenever the down counter value reaches 0x40. It is enabled by setting the EWI bit in the WWDG CFR register. The EWI interrupt is cleared by writing 0 to the EWIF bit in the WWDG SR register. The Window Watchdog is active in Run, Sleep, Low Power Run and Low Power Sleep modes. It is not available in Stop or Standby modes and powered down in Shutdown mode. In Sleep and Low Power Sleep modes, the Window Watchdog clock can be disabled by clock gating by clearing the WWDGS MEN bit in the RCC APB1 MENR1 register. When the microcontroller enters debug mode with the core halted, the Window Watchdog counter either continues to work normally or stops, depending on the DBG WWDG stop configuration bit in the DBG module. Thank you.