 Good afternoon everybody. Let's settle down Wonderful. So a couple of things before I start The material for last week and this week is taken from chapters 3 and 4 of the book. Tomorrow we will be completing all the material that is there in chapters 3 and 4 of the first edition Sam Harris had his book and the video is also recorded for this lecture just in case and it's already uploaded for last week. The slides I have made some slight modifications one that is online is a bit updated but it will the updated one will be uploaded very soon. So let's get moving. What did we do last week? We quickly saw some basic syntax of verilog, how to instantiate modules. Modules are building blocks of verilog. Then we discussed how one can realize or model in both behavioral as well as structural fashion any digital circuit. Then we went through a whole bunch of constructs for example and XR how do we implement them in verilog with the assign statement and towards the end of the week Frank actually started off the basics of sequential circuits. So now today what we will be looking at is how do we actually realize the sequential circuits in verilog. Last week we looked at combinational circuits and this week it will be sequential circuits and tomorrow Frank will again come back to explain how to write test benches for your implementation or rather how to test your code in verilog, how to make hardware faster, how to extract timing characteristics of a particular design. So these things will be done tomorrow today we will focus on how to implement the sequential circuits. So quick recap combinational circuits we all know takes a bunch of inputs, produces outputs based on some logic design. It has no memory but when you want to introduce a sequential logic you introduce a memory element that is you have to remember a certain state so in some sense one can say that a sequential circuit is a combination of the combinational circuit plus the memory element and today we will see how we will design in verilog this entire different sequential circuits we will start with how to define blocks that have memories. You saw last week what are flip-flops what are latches, finite state machines, favorite topics among students and the exam questions and then we will see how to implement these elements in verilog. We will then see one of the fundamental characteristics of a sequential circuit is it's always triggered by a clock signal and we will see how one can implement these in verilog or how one can realize these in verilog remember the two differences latches and flip-flops. Latches are sensitive to the level of the signal what do I even mean by that so latches depend on whether the signal is having a zero or a one but flip-flops are different they get triggered on the edge that is during transition from level zero to level one the circuit gets executed so this is one of the fundamental differences between a latch and a flip-flop and in order to realize all these logic whatever we learn till now such as assign a bunch of combinational constructs is not sufficient we need something more we need new constructs and such as always initial we will look largely at how one can use always and implement all these logic circuits I tried my best to come early and make use of this Wacom tablet so that I can actually draw here so that it gets recorded on the video I failed miserably so I'm going to switch back to blackboards okay I tried my best because I found out that a lot of things were not recorded in the video so I tried my best but somehow it doesn't seem to like me I'll switch back to blackboard apologies for that so what's an always statement so always statement looks like this you have the keyword as such always and then you have an at symbol followed by what we call as the sensitivity list so how do you read this statement you read as execute whatever is there in statement always when any signal in the sensitivity list changes so you always execute statement whenever any signal in the sensitivity list happens so whenever the event is that is mentioned here gets triggered very simple let's straight away dive into how do we implement flip flops so what's a flip flop let's say a D flip flop you have input data 4-bit data here the output Q it's also 4-bit and you have a clock signal typically you use this notation to indicate that it's a clock with the trigger so the V so what happens in a flip flop as I mentioned in a couple of slides before is that whenever the clock signal rises you have to pass the input to the output which basically means that Q gets assigned the value of D every time there is a rising edge of the clock this is exactly how we implement here so we say always you use the always construct at pass edge of the clock what does mean is that whenever there is an up going transition or a positive transition which is from level 0 to level 1 then execute the statement here so the statement will only get triggered whenever there is a rising edge of the clock and when it gets triggered the value Q gets assigned the value D now forget about this symbol it's called the non-blocking assignment until 10 slides just think that this is an equivalent to an equals just think that it's this D gets assigned to Q don't worry about it right now so another thing here is that whenever you use another rule when you use an always block is that all the signals that gets assigned inside an always block in simple terms all these symbols that is all the variables that you use on the left side within an always block has to be a reg okay but note that whenever we say reg it's purely a very large construct it doesn't mean that the eventual circuit that gets realized is going to be a register it could be a register but it could be a simple wire as well so this is just a very large construct and always make sure that any variable you use here within an always block on the left side has to be a register that's it this is one of the fundamental rules that if you apply you will have less errors in your very large code so this was a basic flip-flop with a clock triggered when there is a rising edge of the clock you got the input data D and assigned it to Q now we will look at a flip-flop with asynchronous reset I hope you remember what an asynchronous reset is everybody remembers I assume it's an yes can I so an asynchronous reset is basically the master what happens is that when it happens no matter what the status of the clock is the circuit will get reset no matter what the system status is you send a reset signal which can be a 1 or a 0 depending on how you are going to define it it is going to reset your data that's an asynchronous circuit so how do you define that so what you do is you include positive edge of the clock but in addition to this you will also say I mean this can also be past edge of reset don't I mean it's not a it's not mandatory to actually have only neg edge of reset what it just simply means is that whenever the reset signal goes from 1 to 0 also execute all the statements that are there inside this always block so when there is a negative edge of reset these statements get executed when there is a positive edge of the clock then these statements also get executed also what you can do is if there are multiple statements within an always block you always append it with a begin and an end you actually don't need it for this example because it's just if and an else so it very like understands that it's just one single construct but we will see a couple of examples where you have to introduce the begin and an end it's like the braces in C so what happens here is that as soon as there is the negative edge of the reset then or the positive edge of the clock doesn't matter any of these events happen the circuit checks whether the reset is equal to 0 and if it's equals 0 then your output value q gets the value 0 that is reset or else you simply follow the same procedure of d getting assigned to q so this is a synchronous reset now so we saw till now what's an asynchronous reset now it's a synchronous reset now what's the difference is that even if there is a change in the reset signal the circuit will not reset until the clock is having the positive edge or there is a transient in the clock even if you I mean so in the previous circuit whenever there was a change in the reset irrespective of the state of the clock signal the circuit got reset but here any changes in the reset signal will have to wait until the next rising edge of the clock so it is synchronous to the clock signal and as you can see you don't include the next edge of reset or in this example so you always trigger the set of statements only on the positive edge of the clock this is a very small change but I would kind of tell you how this I don't know how whether Frank showed you how this all looks so let me quickly show it so let's say let's say you have the clock signal I hope it's visible to the last rows last rows are you able to see what I'm writing okay so you have a clock signal and then you have the reset and let's say you have Q the output so when I talk about an asynchronous reset assume that whenever the reset goes high I want to reset my circuit so let me just draw the transience so whenever my reset goes high irrespective of whether my clock is right now in the transient in the rising edge or not in an asynchronous reset system my Q value irrespective of what it was will get reset to zero immediately in the same time frame okay but when I'm talking about an synchronous reset the difference would be so when you are talking about a synchronous reset what happens is that even though the reset is high here the system will actually wait until the next rising edge of the clock to make Q zero so it's always all the events will follow based on the rising edge of the clock and that's the whole difference a small change and this can be implemented with just a small change in the always block by removing the next edge of reset and then you pretty much get you get the whole circuit synchronous to the clock there are reasons why you need both so any questions? simple? difficult? all good? okay so another realization is that you have another signal called the enable also and what you can do here is that so what kind of a reset is this what kind of a reset are we seeing here synchronous or asynchronous? perfect asynchronous it's because you have the sensitivity in the sensitivity list the reset the negative edge of the reset so whenever the negative edge is so whenever you see a falling reset that's from one to zero immediately the set of statements also gets executed irrespective of the status of the clock so it's an asynchronous reset and when you want to introduce enable what you do is you can also use the else if enable then you pretty much assign q to the values of d it's pretty much like an if and an else statement in c or any other programming language very straightforward and also you don't put enable into the sensitivity list because if you put enable into the sensitivity list then the system is not going to not only going to trigger when there is a rising edge of the clock or reset but it's going to start triggering even for enable which basically means is that your circuit is no longer synchronous with the clock or it's no longer going to be sequential so quickly we saw till now flip flops and how do we implement a latch what's the difference between a latch and a flip flop latch is level triggered right flip flop is edge triggered so what you make what what change you make here is you no longer use positive edge of the clock or negative edge of the clock you simply use the signals itself in the sensitivity list what this basically means is that whenever clock changes it doesn't matter whether it's a rising edge from zero to one or one to zero or whenever d changes any bit of d changes this statement will get executed so whenever clock changes whenever data changes it will check if the clock is one then q gets assigned the value of d that's it so it's always level triggered as simple as that so so to summarize the sequential circuit so far what we have seen is we introduced the notion of an always block we kind of implemented how to trigger a bunch of statements with on a clock signal and then what you should also remember is that whatever signal that gets assigned inside an always block a simpler way to remember is whatever signals get are on the left side of an always block assignments you have to define them or declare them as a register this is something that you might want to keep note of for now that is this less than symbol followed by equal is a non-blocking assignment and the difference is that whenever you use the assign which is purely combinational you can simply use the equals but when you are using any assignment within an always block you use the non-blocking statement of course you can also use blocking statement inside but for now let's say that inside an always block you use non-blocking assignments to realize a sequential circuit so you can of course have a whole bunch of always blocks inside module so you can have multiple always blocks for example as you can see here you have an always block which is triggered at the rising edge of the clock and you have a value called special which is the special gets assigned the value of D here and here Q gets assigned the value of normal so what happens here is that as I said anything on the left side of an always block is a register so you see you declare special as a register and you can also include simple assignments in between always blocks for example just like it's a combinational logic right you assign normal equals the inverted of special and normal typically you don't need to define it as register so it's declared as a wire here right and also something that you might want to remember it's not here on the slide but you will end up using it in your lab never assign the same value for example special never assign it within the same module in two always blocks you will have an error in your system because there is a conflict of what actually has to happen so for example never say special gets assigned the value of D in this always block and then in this always block don't say special gets assigned the value of normal so you have two assignments in two different always blocks for the same variable your circuit is going to be throwing up throwing an error so why do you think an always statement memorize so the whole idea behind sequential logic is combinational circuits plus memory element and where is the memory coming in from let's go back to the same flip flop example as you see positive edge of a clock you assign Q the value of D but what happens when the clock is not rising so what happens when there is no positive edge as I showed here so what happens when it's a negative edge or it's a level there is no event happening on the clock the value of Q is basically preserved so there's no change in the value of Q and it's actually memorized so let's go let's take a different example now so now what I have here is another always block which is not edge trigger but I put in my sensitivity list invert or in and data so whenever there is a change in either the in signal or the data signal the following statements gets executed if in this one you get a result of not of data else result is assigned the value of data so when here when in this one you know exactly what the result of result is going to be and when in this zero you also know what exactly the result is going to be in other words you have define all the possible scenarios or you have gone to the circuit what should happen in all the states of in and data and if you do this the circuit becomes combinational so there is no need for a memory here so in order to so in some sense what I'm trying to say here is that you can actually declare a combinational or realize a combinational logic circuit with an always block as well just that you have to fully define for all possible inputs what is your output and then the circuit becomes fully combinational it has no memory at all understood to repeat if within an always block you define for a particular for the signals inside the sensitivity list all possible combinations so for all combinations of the signals in the sensitivity list if you define what the output should be the system is automatically becoming a combinational logic you can use statements such as if then and else which you will not be able to use if you are not using an always block so you will have to live with the ternary operators that we saw last week but here within an always block you can always you can use if then else and case statement and also you have typically when you start programming in very long you have a tendency to use always for everything don't do that use always only when it makes your job easier so let's let's go for let's let's see these two examples a very simple example actually both of them exactly implement the same feature the same multiplexer you use an always with a b so you have an always block with the sensitivity list of a b and select and then you say if select is one you use the result as result gets assigned the value of a else result gets assigned the value of b it's a simple multiplexer but we also saw in we saw last week that you can also implement a multiplexer like this and it becomes a combinational logic so this it so you can implement in both ways but typically this is a much better way for someone who reads it to understand that it's actually a purely combinational circuit so don't simply go for an always block as always but then there is also always construct that there are situations when always block is going to be very very useful consider the seven segment display you will be programming them in your labs you will be using them to display your added outputs to play with your snake implementations so you will have to so depending on the data so here we also introduce the case statement so case is dependent on the data signal so if the data is zero then you assign the value of segments directly a certain value which will actually display this value will actually display zero on the seven segment display so this is basically the set of signals that you actually have to trigger to display zero one two three four five on the seven segment display in your FPGA boards so for this case always block is of great help so because you can directly use case without having to fiddle around with ternary operators and so on another thing that you have to remember when you are using a case and you want to case statement and you have and you want to realize a combinational logic remember combinational logic how do you realize a combinational you have to define or define the result of all possible outputs of the signals in the sensitivity list so you need to have the default here if you don't have a default the system can become a memory element so you have to be careful here whenever you want to realize a combinational logic with a case statement you have to have the default statement and when you say always another point when you use star it's a short form for all signals whenever any signal changes you simply execute this bunch of statements any questions simple to know yep sure you can but you have to be very careful there because if you are going to access just access or read the values it's okay but if you are going to assign in multiple places your circuit is going to be confused the realizer is going to get confused it's going to give you a conflict so you have to be careful but you can do it you can read out so what's a case statement it's like if then else but you can only use it with an always block just like if then else combinational if you define the output for all possible cases therefore you use the default statement so that you don't forget any particular case for which you don't have an output define you can also use case that I'm not going to go deep into it you can check the check the reference here so it's not super important as well so coming to this important part where we kept skipping I asked you to assume that this less than equal is more or less equals so now is the part where we will differentiate between them so on the left side is what we call the non-blocking statements which you have the less than and an equal on the right side are what we call as the blocking statements just the standard equals the difference is that in such an assignment within an always block all these values so all the assignments are going to be made such that A is going to take the value of 1 and B is going to take the value of A at the same time at the end of the block so it's blocking I mean sorry it's non-blocking which basically means that all these values are going to get parallely executed whereas here every statement is a blocking statement what that means is that unless the statement is executed the next statement is blocked it's very similar to the conventional programming language so you have A taking the value of 1 right here and then B takes the value of A the correct value of A so you have B turning to 1 at the end of the block straight away but so the question is why do we even need these statements right you will as and when you start implementing you realize the importance of it and it's a bit more technical so we will if you're interested I will point you to some good literature for that but let's now skip this but so what is important to remember here is that when you say block when you use blocking statements inside an always block with the conventional equals more or less like a programming language all these statements are going to get executed sequentially so I would come to this last statement with an example which is it's much more easier to understand what I mean by that so consider this simple example always at star which is like whenever so all signals are in the sensitivity list whenever any signal changes execute the block you assume that all the inputs are initially at 0 which basically means that P, G, S and C out are all going to be 0 at this point in time now let's say A changes to 1 P becomes 1 G is 0 S is 1 right here because these are all blocking statements so you have the value of P already here by the time this statement is executed so S is going to be 1 here and C out is 0 so at the end S takes the value of 1 now assume that all the blocks that you are having inside all the statements that you are having inside an always block is non-blocking what happens here again all the inputs are 0 and when A changes to 1 P becomes 1 but S is still 0 because all the values are at the same time only at the end of this block so S is still 0 however since P has changed this block is going to get executed again and then S is going to take the value of 1 the only difference is that so that's exactly what I meant by this statement where if you are giving the sensitivity the correct sensitivity list the behavior of both blocks with non-blocking statements and blocking statements will eventually evaluate to the correct result just that it's going to get executed a couple of iterations more that's it any doubts so some rules for signal assignment if you want to realize synchronous sequential logic always use non-blocking inside an always block and when you want to realize combinational logic with the assigned statement you always use blocking statements so you can use a simple equals if you use this statement the non-blocking statement here you are going to end up with an error and if you use an equals here you make sure that you know what you are doing you really want the combinational logic or the kind of behavior that you are expecting to put the simple assumption can be just say I will use for realizing a sequential synchronous circuit I will use only non-blocking statements within an always block easy, straightforward, extremely simple so this is what I meant here if you are going to use an equal inside an always block you know what you are doing you can realize complicated combinational logic and as I mentioned before do not make assignments to the same signal to more than one always block if you have multiple always block don't make assignments to the same signal in more than one block we can start finite state machines right away or we can take an early break and we reconvene at 2.5 I am sure you will be leaving at 2.45 take a break, okay let's take a break now so let's get started there was a couple of questions regarding why would anyone use a non-blocking statement in such a scenario so what I would like to stress here is that you should not use non-blocking statements here it's just an example where I tell what will be the effect if you use a non-blocking statement so don't think that why would anyone use it isn't it wrong why are we even showing this it's just a indication to it's just for you to know that whenever there is a dependency for example you have you write to the value p and then you read from the same value p and assign it to a different value within the same always block always use blocking statement unless you again know what you want to achieve so this is not something that you have to use or it's an option but it's a bad practice when you are going to use dependent statements in the same always block with a non-blocking statement okay let's move on so finite state machines you will have one question in the exam based on finite state machines pretty much 14 to 15 points so kind of important out of 75 so if you remember fsm has three different parts what's called as the next state logic you have a state register and then you have an output logic do you remember last week good I didn't want to take a chance nevertheless so you have two different fsm moor and mealy what is this what is this is it a mealy or a moor why it's a moor why exactly so in a moor fsm you don't have so the outputs depend only on the state and not on the inputs so a quick recap pretty much the same slides what Frank did last week you have so what's so you have these three different parts you have a state register which basically memorizes what is the current state of the circuit since it has memory it's a sequential circuit then you have the next state logic which means that it's a combinational circuit which determines based on some inputs what is going to be the next state and then you have the output logic itself which is also combinational now what we will see is how do we realize this in very long in a very clean manner let's start straight away with an example a divide by three so what we are trying to realize here is a circuit where the signal y is going to go high for every third clock edge so you have here it goes high for one clock cycle and then after that it counts one, two, three and every third clock cycle the output of y goes high so in some sense you can also call it a frequency divider circuit which you will also implement as a kind of a small project a small module in your labs so if you want to realize this circuit as a finite state machine this is how it's pretty much one way of doing it you have whenever you reset let's say whenever the signal is reset my output is going to be one because I will assume that it's the beginning of the sequence then from s0 you always move to s1 on every rising edge of the clock and what is inside these state machines is the output so y is still zero and then from in the next rising edge of the clock you move to the next state again output is zero and then in the third rising edge of the clock you go to s0 where your output is one this is pretty much a very simple finite state machine that we are going to try and realize in very long so we start basically with defining these registers called the state and next state how many states are here three so we need at least two bits to store the values of state the state values itself both the state and the next state so you define register a two bit register state for state and next state parameters you can also kind of to improve your readability you can assign values for each of these states as a constant using the parameter so after this we start with the first part of the FSM it's the state register so what happens in a state we've seen that state register is a sequential circuit and in order to realize a sequential circuit you use the always block we just saw before the break so pretty much the system the circuit will look like this you have the next so at the rising edge of the clock you have the current state being assigned the value the next state so it's kind of a flip flop right so you implement exactly the same exactly that so you say always at the rising edge of the clock and rising edge of the reset so what is this asynchronous reset or synchronous reset asynchronous reset or synchronous reset it's an asynchronous reset because your block is getting executed even for any change in the reset signal then if there is a reset signal is high you assign the value state to s0 and else for every rising edge of the clock you simply switch to the next state this is this three statements these three lines rather is going to be the same for any FSM that you're going to implement so when you're going to do an FSM for your lab project which is most likely four or five you will have to implement an FSM and this is much as copy paste of the state register it's not going to change much so the next one is the next state logic which is as if you remember it's a combinational logic right so for that what we will use is a simple case statement which we have already seen so we will assign based on the current state so it's a very simple state machine so you have based on the current state the next state is very straightforward there's no necessity to check for any input signals nothing so whenever you have s0 the next state is s1 exactly that you just check sorry you just check for the value of state if it's s0 the next state is s1 similarly s1 s2 s2 back to s0 and you include the default to make it a fully combinational circuit any doubts till now and then comes the final part of the FSM output logic and again this is extremely simple here for this particular FSM you're going to assign the value of the output value 1 whenever you are in the state s0 that's it so you have q equal assign simple output logic assign q equals if state is in s0 that's it and since the code is only dependent on the state it's a moore type FSM and quickly I will go through this is the entire code for this whole logic you have the state register which is a memory it's sequential logic so you also use remember you use non-blocking statements here because you want to realize a sequential logic with memory here and then you use the next state logic which is combinational which means that we are going to define the output for all possible values of state so you use always a star and state and the default value along with blocking statements and then you have an output logic here which is basically a simple combinational logic any questions? good then we go to the smiling so this is slightly more complicated example the famous smiling snail example where I think this was also explained in doing the sequential circuits class so what happens here is that whenever the snail is crawling down a bunch of paper tapes with 1s and 0s and whenever it comes across the values 1, 1, 0, 1 it has to smile okay so you cannot make the snail smile but you can at least go out and binary output 0 or 1 where 1 means somehow you can think that it's a smile and 0 is it sad okay and we can realize the exact same circuitry for the same logic in two different FSMs which one quickly which one is a moor and which one is a mealy so both of these state machines are designed for this particular circuitry which one is moor which one is mealy perfect there's actually an easier way which I actually learned a couple of weeks ago which I didn't know after so many years moor for given a particular problem moor state machine always has more states okay moor state machine always has more states this is this was new to me and I quickly looked it up and it's typically the case okay so it's super easy you don't have to worry about inputs outputs nothing you just say if they say if they give you two different state machines for a simple problem you can kind of blindly guess take a 98% guess that if you have more states that's moor interesting okay so what we saw in the previous example was the implementation of a moor finite state machine but now what I would like to show you is how we would implement a mealy state machine so let's go through the same procedure we start with a smiling snail module we have input a output y if you remember in a mealy case all your inputs and outputs are shown on the transition arc so the first value is the input and the second value is the output so here one it's a bad starting point so here one is a and y is 0 so as before we have four different states so we start with we need two bit registers for state and next state and we will make constant parameters for s0 to s3 yeah okay as I said the state register logic remains exactly the same there's no difference from the previous code you have positive edge of the clock positive edge of the reset if the reset is high state always goes to s0 and then if it's not so then at every rising edge of the clock your state is next state this is pretty much going to be the same for all the state machines that you're going to write but the next state logic is slightly more complicated here that's all because the next state logic is not just a simple equals because now you have to figure out based on the input whether you want to move to s1 or s0 so let's actually see how the state machine works so when I reset we start with s0 and based on my so when the snail is going over a 1 it may be because we are going to look for a 1 1 0 1 if it sees a 1 it jumps to the next state now if it sees a 0 then your sequence is broken so you go back to s0 but if you see a 1 if the snail sees a 1 then you say okay 1 1 so you go back go to s2 now if you see a 1 it can it is broken breaking the current sequence but however it may be a start of another sequence so you go but you stay in the same value you will understand this better when I finish so you will now when I see a 0 you jump because you are seeing 1 1 and the next value the snail is seeing is a 0 so it is closer to smiling and all these during all these transitions you have the output always 0 so the snail is still sad and then as soon as it sees a 1 the sequence is complete your output is 1 and it goes back to s1 why do you think it is going back to s1 and not s0 yeah yes and maybe you know what it is but maybe yeah exactly so it is in the middle of an overlapping sequence for example when I have the sequence of 1 1 0 1 1 0 1 I hope let me just quickly just to make sure that you understand what I am talking about so if I have a sequence like this my snail has to smile twice it is because you find an overlapping sequence so it has to smile here and it also has to smile here everywhere else it is going to be very sad ok so if I actually go back to s0 then you are not going to detect this overlapping sequence that is why you go back to s1 because you maybe there is a start off another sequence and when you want to realize this and this is pretty much the reason why you have why the circuit stays in the same state as 2 here so when you want to realize the state machine using the case statement you can include if and else within a case statement so let's take an example s1 if my input is 1 my next state has to be s2 if it is not then my next state is going back to s0 my next state is 0 that's it so you implement exactly this with case and defaults and don't forget to give the default which is always next state is s0 so with this you end up implementing the next state logic completely any questions to la then you might potentially end up with memory with a latch so you will not so what is going to happen here is you don't know if there is so here it might not be a problem because you have defined each and every state so in this case it might not be a problem but if you have let's say 8 so if you have a 3 bit state register but you care about only 5 states and then you have the output is not defined for 3 of them what that basically means that the system doesn't know what to do so it will memorize and it will stay in whatever state it was you might potentially end up realizing a sequential circuit and you will have a different behavior but in this case the default is not necessary because you have completely defined for all the states what is the output but you will end up with sometimes you only use 6 out of the 8 possible values and you don't have the 2 remaining and you don't want a memory for that you don't need to but it makes life easier this is pretty much what we saw where so we saw it here right so both this and this realize exactly the combinational logic both of them realize a multiplexer this takes more effort this is much easier to read you know that it's a combinational logic but sometimes all the statements are great exactly this kind of a scenario where you have otherwise you will end up writing ternary operators and make your code not readable so it's much more easier to write it in an always block that's it nothing more good so the final part of the fsm which is the output logic and here remember that we are implementing a mealy which means your output is dependent not only on the state the current state but also what's the input so you have based on if you are an s3 so if your state is s3 and your input is 1 then the output is 1 it's exactly what happens here so you have if your state is s3 and your input a is 1 then your output becomes 1 and it's a very it's a simple combinational circuit any questions and this is the entire code that we saw broken down starting with 2-bit registers parameters you have the standard state register statement literally you can copy paste it to any different any fsm that you are implementing the next state logic which we saw with some checks for the input values and then the output which depends on the current state as well as the input any question yeah this is the if condition it gets overwritten here you mean yeah yeah so it happens at every clock cycle so the state gets overwritten at every clock cycle so something to remember here is that the always blocks so all these statements gets executed parallely it's not sequential if you are using blocking statements within an always block then you are going to implement you are going to realize it sequentially otherwise what happens here is at the same time when these circuits are getting executed this is also going to get executed so the assigned statement is a simple combinational logic which is going to get executed every time there is a change in A and state so it's always going to be ready to go and all these statements that you see even though they are in different always block both these always blocks are going to get triggered parallely if necessary so for example if the block changes this will also get triggered if the reset changes this will also get triggered because you have used the word use star but just that it has nothing to do so it will just be the same same it will execute it will end up with the same results and however there will be cases where if there is a change in say next state for example this block is not going to get executed because it's going to wait only for the changes in clock and reset so whenever there is a change in clock even this block is going to get executed but when there is a change in the next state this block is not going to get executed so it's really a matter of the sensitivity list here and don't I mean it's very important to get into this mindset especially when you are writing hardware description languages no matter if it is VHD or very long that whatever you write here are all going to get executed at the same time and the only difference is going to be whether it's a blocking statement, non-blocking statement and the sensitivity list of course that's it yeah because you hear this combination exactly so blocking statement blocks only inside the always block good point great actually we are coming to the end of the show great so what did we learn we define sequential circuits in very long we introduced always statements how an always statement can be used to memorize elements we saw what's the difference between the blocking and non-blocking statement and then we saw how to define the various parts of a finite state machine from next state logic the output logic and the state register we saw how to do delatch the difference between flip flop and latch how you can realize a flip flop how you can realize a latch in very long you learned something new that Moore has more states the Mealy output so you remember that there are two Moore and Mealy state machines we saw how to implement both Moore state machine and Mealy state machine in very long and what you will see tomorrow is timing how do you extract timing for all these circuitry how do you define how fast a particular circuit has to be executed what what defines these delays why are 2.4 gigahertz Pentium processors more difficult to achieve or how why is it that 2.4 gigahertz is 2.4 gigahertz clock rate and why we started off with 8 megahertz and so you will see all these timing characteristics of how to make your circuit run faster and also you will see how to verify your very long circuit right using test benches and simulations tomorrow which is very important for your labs as well with that I would like to say that I totally enjoyed teaching you folks it's goodbye from me hopefully for this semester see you