 Hello everyone, so in this vector we will look at the compile so we go with this compile is a command in when compiler that actually carries out the system, we look at what this compile command does, we look at a few strategies of doing the system, we look at some of the options of compile command, so let us go through the flow again, so we looked at in the last lecture we looked at how to set the design constraints, so we were looking at this part, we saw our design constraints, max function, max plan out, max category then we saw how to constraint the design function that is how to define a clock, so just to review the tool will break down all the time path into path group, so that the timing path group are the register path which are constrained by just defining the clock, the input register path which needs set input delay to the properly constrained and again register to output path we need to set output delay, there is a set max area constraint to set area goals, so till this point before selecting the compile strategy, we have looked how to specify the boundary condition, first how to set the library, VTRTL, set the operating conditions by load model etc. the design constraints, so before this point we have not actually performed any synthesis, we are just setting our tool, setting up the constraint, setting up all the desiring operating condition, before the synthesis even goes ahead, now the first step of doing synthesis and after all this is done, after we have gone through the constraints part, the first step is we should know what strategy strategy we want to follow, so I talked about the top down and bottom up and more details in the coming slide, then we go ahead and summarize the design, the last part is what we look in the next sector is how to get, how to report, so now the synthesis is done, now there is a lot of checking we need to do to make sure that synthesis is perfect, we need to check the area report, we need to check the resource user, the user's report, we need to check the constraints whether they are the goals are being met or not, in the next lecture we will concentrate on the analyzing and resolving the known problem, how to report, timing, how to report area and so on, so let us let us focus on the compile in the sector, so the optimization process DC perform is divided it is at 3 levels, so DC will do optimization at 3 levels, starting right from the RTL, so first level is called architecture optimization, second is called logic level optimization, third is called gate level optimization, let us look at each of them in detail, so the first the architecture optimization works directly on the SDL distribution, it will include a lot of high level synthesis tasks such as sharing resource sharing, so sharing common stuff expressions and resource sharing, these two will result into lower area operations because let us say you have multiple adders in your design in your additive description, now just by looking at a plus sign DC will know that which will translate into an adder, this is irrespective of any technology that we use, the things have not gone to the technology level yet, we are still working at technology independent that is at the GTEC level still, so but even at the GTEC level, DC knows that you are using different types of adder, maybe equal adder or a half adder and then it will try to find out whether these adders can be shared across expressions or not, so this is what it does in these first two steps, we will see if it if it can share common sub-expression, if it can share resources, resources can be data path like adder, method line and so on, it will also make decisions about what design the components, what design the implementation to pick up, for example for an adder there are multiple implementation like a ripple adder, a carry looker adder and so on, so it will do some sort of implementation selection, so when we when we say implementation implementation means the design the component will be an adder and the implementation can be one of ripple carry looker adder carry save and so on, reordering of operations to make sure that the AI is minimum, identifying arithmetic expression for data path implementation, few of these things like selecting design the implementation and identifying arithmetic expression for data path implementation, these options are available only in DC-Altra, what it means is that there are two commands for simplicity, one is compile, this is the basic compile command, other is the compile address to Altra command, compile address to Altra command is part of the license which is called DC-Altra, I am not very sure whether it is available for new in the labs, even if it is not available it is not a big problem, most of the trial designs that we look most of the simple designs that we look are the compile command is good enough for this, so earlier few years back there used to be a separate feature of design compiler which used to help us in doing data path implementation, data path means a design which is heavily using arithmetic operations like an arithmetic logic unit of a CPU that is adders, multiplier, subtractive and so on. So DC had a separate feature which was helpful in optimizing this part of the design effectively, now those all those features are now brought into they are available in compile Altra, so compile does a good job, compile Altra does an excellent job on the data path operation, so few of these features are not available in compile, they are available in compile Altra, so except for design and implementation all these tasks occur only during the optimization of an unmapped design, this is the important part here unmapped design. What unmapped means is that still at this level DC has not started selecting the technology that we take yet, we are working still at the G tech level, the mapping has not occurred, so design a netlist that consists of G tech part is called unmapped netlist, a netlist that is mapped into is select has already selected the technology that already standard says is called a mapped netlist, so all of these optimizations still work at the unmapped level, however DC might do some changes to the design implementation even at the gate living stage, even at the map netlist, apart from those all these steps all these optimization processes and at the G tech stage, high level synthesis tasks are based on the constraints on a real coding style, we have seen that we can force resource sharing, how we can force resource sharing at the RTL stage itself. Obviously our constraints will determine what design and implementation is selected, for example if we have a very lag setup constraints, when it is low plot then DC will do ripple adders because they are lower in area, but they are again slow. If let us say our constraints are very aggressive, when DC will not use ripple adders, it will use some other type of adders like carry look at or carry share that are better in performance in tone. So after this high level optimization takes place, the netlist we get is the G tech netlist. Second level of optimization is the logic level optimization, again this also works on the G tech netlist. Now it consists of the two processes, let us look in the reverse order, let us look at the flattening process, when flattening what DC will do, if you pick up a pick up a combination search, pick up a combination design and it will represent it using a two level sum of product expression. So if you go back to your Boolean agenda, any function can be represented in sum of product form, when I say sum of product form, I mean the under due sum of product. So for example, let us say you have a function which has been input A, B and C and you have three input function will have eight states and that function let us say for five of these those states. So that total in total eight states ranging from 0 0 0 to 1 1 1 and out of those five five states the output is 1. Now the sum of expression will now contain the under due the under due sum of expression will now contain five five expressions. For example, it will have A, B, C, flattening complement, decouplement is something of that right. Now you could further use Boolean and they are better reduce this, but what DC does is, it will use during the flattening process, it will use the two level sum of product expression without the reduce, without reducing the difference. What it does, this is carried out independently of constraint and it is very useful for speed optimization for high performing process, why? Because there are just two levels of logic between input and output although the area is more. So for timing critical parts where you have such combination expression DC will use this process to make sure that there are minimal levels of logic between input and output so that the speed is of a primary important tip and the area is more corresponding. Now as opposed to flattening DC will use structuring now to reduce the sum of products into something which is more optimized based on the area. So the process of structuring will add intermediate variable. So when we reduce the sum of product expression we get intermediate variable and logic structure. So it will add those intermediate variables which can result into reduced design example. Structuring is again constraint based now see flattening is independent of constraint and structuring is constraint based why? Because DC will only do the structuring for the parts of the design that are not timing critical. For the parts of the design DC will use that DC knows that okay I can reduce the area without affecting the timing it will do. So if you notice the major part of the design will be structured it will not be patterned why? Because for almost all the designs majority of the timing parts are not non critical where few say there are few let say 5 percent of the parts will be timing critical 95 percent will not be timing critical all those 95 percent will get the advantage of structuring. So during this process DC will search for sub functions that can be factored out it will evaluate those factors based on the size of the factor the number of times the factor appears. So it will factor out the expression it will also see whether these expressions these factor these factors can be reused. So this will DC will turn the sub function that more should use the logic into intermediate variables and it will factor them out although the language here is a bit complex but the process is exactly same as the one we use to reduce the expressions using Boolean arithmetic on paper. Let us look at the third stage of optimization which is called the gate level optimization. Now gate level optimization works on these data techniques to reduce a technology specific network. Now why does the so DC already optimize a lot of stuff in people. Now when it goes to when it goes to picking up the system now it it will do some kind of optimization depending on what kind of technology they do. So first of all it will just try and map stuff it will map all sequential logic in the class it will map and gates and gates or gates or gates and so on from the cells on it it will pick up cells in the target library then it will go on to do the day optimization. The goal here is to fix me as a correlation and this part does not fit design rules. Next it will come to design rule fixing. Now here DC will try and fix all the design even if it sees a time inversion. So what it means is that although the design rule fixing as a as an optimization step comes after the optimization but as we have looked we saw in the earlier lecture design rule fixing takes a higher priority DC will try and fix all the design rules even if it means violating the time inversion. The last of the goal is the area code it is to make sure that the area is met after all these steps have gone through but there will be a step for area recovery where on a design which is already all the design rules are fixed let us say already meet timing goals DC will try and recover as well but in the process of area recovery it will not violate the design rule or the optimization rule. So this is just we states the priority of optimization that DC uses. Now so we saw different levels of optimization now let us see what are the different compile strategies available to us. So there are three there are two basic compile strategies one is called the top-down compile, second is called the bottom-up compile and one could use a mixture of both of these which is actually used mostly in industry for the mixed compile. Top-down compile as the name suggests starts from a top-level design so all the parts of the design all the different admin files are written and there is only one compile side. Here DC will attempt to compile attempt to sympathize complete design in one go. The bottom-up compile again makes use of divided counter approach where it is up to us to choose what designs we want what sub-designs we want to compile first and then we will use these compile designs and go top and go top-level compile. So mixed compile again uses both of the features of both the part of the let us see in detail we will see few comp few compile script first. So let us take one example of a design where so your design is called top in the top-level RTL file top.d it contains two instances U1 is the instance of design U2 is the instance of design V. Design V in turn contains instance U3 module C instance U4 module D instance U5 module E. Operating condition we have selected worst case which is expected we have selected a valid module we are targeting a clock frequency of what we have. So here let us not be concerned to concerned about what the input output course of the design has assume there is a clock assume there are a number of inputs and a number of outputs. So for all inputs we are targeting an input delay time option now again we are targeting an output delay time option we are targeting an input dry strength. So now please note input dry strength and output load on the final problem of the input dry strength we are targeting there is a cell called buffer called IV we are targeting that all inputs will be driven by we are assuming that all inputs will be driven by this buffer IV we are targeting to synthesize for an output load of 1.5. Now the first step is to develop the environment constraints and the so for at first we will start in developing constraints for the top level design. Let us look at the top down compilers so we are assuming that all these RTA files are written at the same time and the compile command is issued at the top level. So we will set the current design to be top and issue a compile command. Before that we need to make sure that we read libraries correctly we set the environment constraints and the design constraints which is defined by these specifications. So let us look at the script so the the first two commands first command says the operating condition, second command says the by load model, B says the driving cell to be this buffer IV which is written in the specification all inputs so design compiler fine time all such tools use PCL language as their base. So all the commands here all the expressions here will are are tickle expression. So if you do not know tickle at present you will learn during this course you will learn how to use as and when you practice working on design compiler in fine time you will come to know of the various expressions you will do various commands in tickle. I would suggest reading some basic material of tickle before attempting the last it will make the understanding a bit easier. So first two sets the operating condition and by load model the last two sets the driving cell let us not look at the set right now this one will set the load for all outputs all inputs and all outputs are collections. So when we use this with square gates this collection will return an array of a collection of all the inputs all the input ports of the design similarly all outputs will return a collection of all the output ports of the design. So these the ones marked in blue are the environment conditions we said the environment conditions we said the operating condition by load input conditions that is driving cell in the output. The last one set drive 0 ok let us look at the creation then we come to the timing condition. Since the target frequency is 40 megahertz we create a clock we create a clock of 25 minutes period. So period is 25 nanoseconds here one can ask that how do we define the units let us go back to the library slides and see that the units are the library is 12. So the unit nanoseconds so period is 25 nanoseconds the port the input port is clock here. So assuming there is an input port called CLK a clock CLK is created at that port we said the input delay to be free as written in the specification input delay is always with respect to some block here there is only one clock CLK. Now here this line tells the DC that I want to set this input delay on all inputs except clock except the input CLK it does not make sense the CLK is the point where we create a clock it is not correct to set an input delay there and CLK is also an input port. So the command all inputs will return the collection of all inputs remove from collection with remove the port clock it will remove the port clock from the collection all inputs. So this is how we so this is a very standard sort of command to apply input delays if you want to have a single input delay for all input you must be careful to remove the port on which you are creating the clock from this list. Set output delay is simple again set output delay of 2 again with respect to the clock CLK on all the outputs. So this is the constraint file in which we have defined all the environment conditions plus all the timing conditions. Now usually it is a it is a drivable not to do any design rule fixing on the clock. Why because clock usually finds out to almost all the registers in the designer. Let us say you have a single clock and you have a thousand register thousand clock. So this this port clock will be driving it will have a fan out of thousand. So it will have a big design revolution of port which is driving a thousand cell. But design compiler is not the tool to fix this usually this fixing happens during physical design when an actual clock tree is built. That is why we should make sure that DC should not fix anything on the clock network. This command tells DC to do exactly that. It is telling DC that the drive is 0 on the clock that means the clock port has an infinite right strength. So please do not fix it. In the newer versions of the design compiler there is no need to give this command. There is no need you can choose to ignore this a create clock command itself will imply that DC will not touch the port which has defined on it. So such type of networks the clock network the reset network which have high fan out and which we know that a tree would be built in physical design high fan out create a score. We want to exclude such nets from design rule fixing and these nets are called ideal network. So you could use a command called set ideal network on on these nets as in when you work on the designs you will know on these lines. So there is a command called set ideal network which you can use to specify such nets. But please remember for the newer versions of design compiler it is not needed to explicitly set an ideal network or a set drive on a clock network DC as soon as you give create clock DC will assume it is an ideal network right. So this is the command file which will tell DC what are the environment condition and what is the time difference. Now let us look at the let us look at the process of clock down compiler. Clock down compiler is very very simple it is just one compile command the flow is you read in the entire design read in the entire design apply the constraints and compile the design there is however one negative form. If the design is picked and then free and CPU intensive it will take a large amount of time for DC to compile. In my experience I have seen few blocks that are so big and so complex that if you perform a top level compile on those it takes multiple days for the compile command to run. Now you do not want that because even if you have a small problem to fix and the design takes let us say day to day to compile then if I issue a command now I will know only tomorrow what the problem is. So you will waste a lot of amount lot of large amount of time in debugging first kind of design. So it is not desirable to have two larger design go through top down compile. However in your labs and all ideally you would use top down compile because it is very very simple compared to the we will see the bottom of a code which is slightly more complex it is very simple you do not have to worry about interlock dependency. So let us say a design like this you do not have to worry about the interface between u 1 and u 2 how to constraint is because the compile is happening from the top level. So in your in your labs you would mostly do a top down compile but if you get time then you should try a bottom of compile at least one just to understand the flow. So let us look at top down compile script read in the design read in all the all the weblog file it is a good practice to have one module per file which is being followed here. So module A is into A dot B module B is into B dot B. So we need all the weblog file we need the top dot B please note this script is using read the weblog you could use allies elaborate I would suggest using allies elaborate. So that is the recommendation because it gives the much more the allies elaborate combination will give much more insight into the design exploration right. So you can view all the warnings easily and so on it sets the current design to top and performs a link command. Now what link command does this command will try and see if there is any type of logic in your design for which it does not find a module level description. For example if you forgot to read in design E dot B then the link command will tell you that there is an instance of some module E for which it is not able to find the description. So link is the one that actually will tell you if you have any module description missing right. Assuming you read a read in all the files correctly you source the constraint file. So this default dot call is nothing but this file we are talking about. So and assume that the libraries in all are correctly set up in the in the dot nothing to the top. So as soon as we invoke DC the search path and link path are already set we read in the design we set the current design to be top we link the design to make sure that it elaborates perfectly we source the constraint file. Now we do a compile we can do compile instead of compile Eltra. So we what we did is we just followed this rule the library is a part of source dot some of it is set up that is the link library and target library set up correctly. We read in the design we define the design environment we set the design constraints and now we are applying compile. We selected the compile strategy to be top down now we are using either compile or compile. So we use compile or compile Eltra compile Eltra this will compile the design. So as you see the top down approach is very very simple you can just take the flow chart you should just know the commands. So actually you can use this script this complete script as the starting both. So you can from this slides you can copy the script and use it to make your own top down compile strip for your own design. You have to just replace read the law here by let us say analyze command for all your RTL set the current design to be top elaborate the design and do whatever you want to do. Now let us look at the bottom of compile the bottom of compile is used for big designs where you do not want to compile the design in one group because it takes sort of amount of time in memory the advantages are clear that it will you can use divide and counter approach it requires less memory than top down compile. It allows time budgeting I would say this is an advantage as well as as well as disadvantage because time books budgeting itself requires some effort we will see what time budgeting is the bottom of compile though on the other hand it might need multiple iterate to get it to work why we will see. So in the bottom of the strategy it needs manual revision control the decision control here is in the context of that you have to make sure that since you have different iterations so for each of the iteration you have to store the constraint file you have to make sure that there is some kind of revision control in process so that you know what changes from one release from other. So the idea is in bottom up that first we choose lower levels this is smaller design the smaller sub design and compile them then we read this compile design as part of the top level design and now we compile the top level and applying the top level constraints and we check for version. Now the effort from from design compile is reduced because in title top level design all the sub designs are already compound they are pre-compiled. So what it is doing at the top level is just compiling the user it is just synthesizing the user so it is effort is reduced. Now it is possible that doing this after you compile the top level you see that there are no design volition so everything is fine this is most desirable outcome but usually it will not happen for complex designs or for designs with high performance it will not happen so you have to go and perform one more iteration at least to make sure that the volitions are removed how to do that let us see. So the first the first part of the flow is we have to develop so any design that goes through compile or synthesis so compiling synthesis is at two terms I will keep on using the changes. So any block synthesis size must have a constraint file everybody should agree with this right because without the constraint file there are no goals without the goals synthesis does not make sense. So when we so we have to develop both a default constraint file for the top level and a sub design specific constraint. So the default constraint file here will include the global constraints such as clock information in private load estimates that means it will contain all the environment conditions. The sub design specific constraint file now they will reflect the time editing for example let us look at this figure in there. Now here I want to if I want to do a bottom up complete bottom up I have to compile A, C, D and E. So when I compile for example when I compile the the design C I know the clock assuming that the same clock comes here. So assume there is a port called CLK CLK. Now this CLK will go to will go to C it will go to D it will go to E it will go to A. The clock is ok in the simpler part but now C will have some inputs it will have some outputs it will have some inputs coming from that the A or it has some outputs going to C or vice versa. Now we need to find the input delay and output delay for these codes. Now input delay of 3 and 2 input and output delay of 3 and 2 at the top level do not mean that same values will apply at C because we do not know what C is interface to D or to A or to any other block is really is right. So we have to study we have to know what C does actually and we have to allocate some time budget for the input and output for C this is called time budget. So let us say there is an there is an interface between 3 and D. Now we have to see what let us say it works it is a so there is a register and C with riser register and D and there is some combination logic in between distributed between 3 and D. Now we have to know what part of the combination logic is in C and what part of this combination logic is in D. And according to that we will do some kind of time budgeting we will define input and output delay. Now obviously this is not an easy thing to do for a big design which has lot of sub design. So what we do is at first we start with some growth of delay. So for this exercise let us assume that this input and output delay are applicable for each of the sub design. So we will use these values for each of every design here just to make us make things simpler. So we compile the sub designs so this is the way we will form the sub design constraints we will compile the sub design independently then we will read the top level design and any compile sub designs not already in the bin this is just to say that because we use remove design commands a lot in this process. So we have to make sure that all the designs are read before the top level design is read. We will set the current design to top level we have to link and apply the top level constraints. If the design needs these constraints we are done what if it does not then comes the second iteration. Now we apply a command for characterize with the cell instance with the worst violation. Now let us say if we do not meet the timing constraint we find out what is the cell with worst violation and we apply the characterize command. Characterize command now so the first iteration has already taken place design compiler has all the maybe all the designs in the memory it knows the interface between all the sub designs. So now the characterize command will enable DC to extract the input output delay for example for each of the sub designs and we can use the write script command to write these values. So write script when we write out the script using characterize command DC will write out let it I write out a for design C I write out a script command I will say write script for this design after issuing the characterize command. So what DC will do it will write out the input delay, output delay, clock information, boiler model, operating condition and so on the input driving condition the output load condition because DC has the information about each of the sub designs. So to write out all the constraint the complete constraint for us. Now in the second iteration we have to use this constraint file and be synthesized why because the first constraint file that we formed was just an extension. The second iteration has much more accurate value and it will mostly result into a better synthesize necklace. So we use this script we read in the remove design on minus or just tells that we need to remove all the previous design which is logical. Again we read in the RTL design. So we have to recompile from RTL it will result into a better optimization. We set the current design to the characterize sub design and recompile using the saved script of the characterization data. We have to do this for all these sub designs that tail timing right this is the script. So it again uses a TICL contract. So they are not too difficult to understand they are much like Perl or somewhat like C. So here we saw their file design maybe 3DV. Now the idea is specific comment the idea is to compile this is the first iteration we are compiling each sub block independently. This is a for each which will run through all this block this is a for this is a for do nothing depend on a for you. So for each block in all block we read in the block source. So we set the variable block source we read this file we set the current design to this block we link we show the default constraints because as I told you before we are using the same set of constraints to start with. So whatever the constraints have a top level we are using for each of the sub design. So input output delays remain same the clock remains same this is the first estimate. So we source this block constraint block script. So there they can be separate block level constraints which you can form for sub design you could you could read them here. So we read the default constraints and we read the sub design specific constraints you might have here and then we do a compiler. So this whole construct here this complete construct here is doing the first iteration that is it is compiling all these small sub design. Now we go ahead and read the top level design set the current design to be top we link and we write we write out the first part. Now why did not we use the compile command here? It is assuming that top level does not contain any build up in the top level is just a structural format that means the top level is nothing but it contains the module instances and bias which is a very good assumption. The idea is that there should not be any build up in the top. So the compile effort is saved there is no need to compile anything in the top level because all the sub designs are already compiled. The write command will write out a ddc for the ddc is a binary format you can also write a value of format. So we write out the first part ddc. Now we apply the constraints at the top level the top level constraint and we check the timing this is for checking the policies. So what this this part is doing this first slide is doing it is compiling all the sub designs it is reading the top level and it is applying the top level constraint. Now applying the top level constraint do not mean you have to both the system. Why because the top level the design is already compiled it is available in lecture format we just want to check the only thing we want to do here this here is you just want to check if the top level design meets time. So we check for timing violations if there are no timing violations then we are good but what is their timing violation this is the second part of the script. So now we select all incentives and we use the characterize command. With that you see that characterize all these instances. So now for each of the blocks we so this for each of the blocks we set the the current design and we write this one. This write script will only work after characterize and characterize may take some time. We are telling you see that characterize all these instances that means find out what the constraints are for each of these instances what are the environmental conditions for each of these instances dc will do that and then for each of the blocks we write out this script. Now what we have to do we have to do a second part compile. Now for each of the block we clear memory we read in the well log we read in the well log here. We read the we set the current design to be this block we apply a default constraints. Now these default constraints are no timing constraint in this case they are complete we are setting the operating condition and we are setting the violent. We are not setting the input of today. Now we read the this now we read the script that is written out that after first class we are sourcing it yeah this is very suitable. There might be any block level specific constraints we can we will see in unit 5 what they could be unit 4 and 5. These might be some timing exception something about we source it here and then we compile this block again. So this is the second part. So the first part was with estimated constraints the second part is with characterize. Now the last part of it is exactly same as this we will read the top level design we will link we will source the top level constraints and we will check them we will check the variations. So we see that a bottom up is comparatively a bit more complex than the top top down approach. So my recommendation if you can do top down if it is well within the limits of the CPU time and the memory usage please go ahead do not even think about doing bottom up top down is much better in terms of area and timing optimization if the design is not large not too large. So in fact we do chip level like this let us say R chip has multiple blocks let us say one is USB other is let us say a CPU third block can be an impact decoder. So what we do is a USB a CPU and an impact decoder individually are very very big blocks we cannot synthesize this from top down what we do is we synthesize USB separately we synthesize CPU separately we synthesize impact decoder separately and then we do top level synthesis. So at a USB level or a CPU level at an impact decoder level it is a top down but at a chip level it is bottom up synthesized meaning that USB is synthesized already if you synthesize already you enter decoder is synthesized already we just read in the these networks at a top level and do a top level compile assuming that a top level has will have some blue logic in our case. So similarly you could also have a big level compile where we take the advantages of both top down and bottom up. So use top down for small block use bottom up to tie a small hierarchy into larger block this is one example for example a bottom up compile can be used for the and a b c and d are all bottom up compile for example that means a is compile separately d is compile separately c is compile separately d is compile separately but we define timing values for a b c and d so that the top level can be read in after reading in the address for a b c and d. So if you look from the top it is bottom up if you look from the a level of b it is top down. So these are just some terms so albeit it is all being almost all being the mixed level strategy for this level but for your block practically please use the recommendation is to use top down. Now let us look at what happens when you have multiple instances in your design. So in a hierarchical design often there are multiple instances of same model for example in this top design u3 and u4 both belong to the model c there are two instances of c and is usually other is u4. So what are the loaded designs in memory a instance u1 c instance u3 u4 d instance u5 and b instance u2 how to be resolved. Now the first thing you should understand is that although u3 and u4 belong to the same module c the environment conditions of u3 and u4 are different why? Here u4 might top to u5 and might top to u1 this u3 might top to only u4 alone. So although the module level remains 2 that the system remains 2 that then you have an added difference that means you have a new design new design and input adder. Now this 8 bit adder although it has same module you might have multiple instances of the same type adder one of the adder might work at a lower frequency other adder might work at the higher frequency what it means? It means that although the logic level both of them are same but when it will come to implementation one adder will be completely different from other. So how does BC resolve it by default or what other steps can we take to resolve the system? So first is a unicupy method this is the simplest of the method in which the tool is automatic. So this the process of unicupy means that each of the copy of the module so there are multiple instances of each copy is a unique copy the single assume each copy is a unique copy. So it will do something which is called unicupy method. Let us see we will see it in detail what it means. Second process which we could use is the compile once do not take method we will see what it means. Third is the unicupy method. Let us see in detail. So now in case of unicupy what DC will assume as soon as it sees U3 and U4 belonging to the same module see it will make two different copies it will copy in C into C0 and C1 and it will remove C. Now for all practical purposes what we did is create separate unique designs. Now this design top does not have any multiple instances this process is automatic as soon as you do a compile command as soon as you do a compile command DC will start looking for multiple instances it will start applying this will remove the original design from this after it created unique design. This you can only stop this by setting a don't touch command on some design if the design is don't touch if you use a command called set don't touch on a particular design DC will not be able to apply the design. So this is again an automatic process and it is the most desirable process in the sense that you should use this we call thing in most of the cases there are very special cases in which you will use any of these two other techniques but this is the most famous technique and it is recommended that you use almost all the second is compile once don't touch method. So what it means is that we compile once that means let us say a design C has three copies we compile C separately separately not as part of the top domain we compile C separately and then read this netlist use this read this compile netlist as part of the top domain and since this C is already man we set a don't touch on this. Now DC will not do since we have set don't touch on this DC will not do anything to it. So we should only do this if the environment around the instances are sufficiently simple that means all the designs all the copies of that all the instances of that design should work on similar frequency or almost in frequency and even the environment conditions even improve out the full specifications after otherwise you will see violation in one instance and not see any violation in the other instance. Now let us say you have an 8 bit adder again one works at 100 megahertz another works at 200 megahertz if you use this approach then first question is you have to since you have to synthesize this adder separately what frequency would you do common sense would tell you use 200 megahertz why because 200 megahertz implementation will work for 100 megahertz but now 200 megahertz will have more area than 100 megahertz. So in this case it is not desirable to use support it is desirable to use the use of adder but if both adders work at 100 megahertz you should use the support. Now in this method we compile the design using the environment of another instance and then use the send code set do not touch them on. So these are the steps we characterize the set design we should use the characterize command as a second step as a second iteration just try to get it for bottom up it is the same case we compile the reference of design we said do not touch command on these and compile the entire design for example let us see we set the current design to be tops we characterize U2 U3 that is U2 U2 slash U3 this design. So we will characterize only one of this this only one of C 3 or C 4 we need to characterize only one. So we characterize U3 we set the current design to be C we did a compile obviously one thing is missing here and this is the reading this constraint. So we characterize U3 reading the constraint for U3 compile U3 again we set the current design to be top and then set do not touch on U3 and U4 U3 and U4 and then we again compile it of them it might seem a bit confusing at first but the essence is that one of the sub designs you already compile and you do not want DC to type it further to modify it further as a start of the problem this method in essence is very similar to the bottom of the if you compare these scripts they are almost same you use the characterize command you use the write script command you compile the search time and then you set do not touch on the search time. So set do not touch part is the only unique part how it is the ungroup method this method is the same as unify method almost but it will remove the level of hierarchy so this actually ungroup command is not tied to the unify system process that means ungroup command you can use it to remove the hierarchy and any part of it so here what we do is we remove this hierarchy that is earlier the design was this you had U3 U4 U5 now what we could do is we could ungroup U3 and U4 what it means is that the hierarchy U3 and U4 will be removed now if U3 and U4 is removed all the tests are part of the the design is automatically ungrouped because now the module C does not exist the design C does not exist the module boundary C is dissolved that is what ungroup does even you could ungroup U5 if you want you can ungroup U5 ungroup is not tied to the unique system process so by doing ungroup in this particular specific example we are unique to find the design explicitly so this is one another way doing that but again so ungroup has one more advantage is that when you ungroup the design now DC can combine the combination elements of both U3 and U4 and optimize it more effectively so obviously the more hierarchy the design has the more artificial boundaries it has and the more it will prevent DC to optimize that is why we say that the design should be logically partitioned in such a manner that it helps DC in optimizing the design and not the other way so we saw one example how to logically partition the design how to keep the combination logic and the relative sequential logic together in the same module we have already seen that in one of the lectures so we saw three commands we saw three methods of solving multiple instances unify compile ones don't touch ungroup I would again recommend to unify that is the default you don't have to specify any separate command the compile command itself will do it well now let's look at the compile command compile command has these many options no map and all that I would recommend that you go go to the decision and read the manage I would discuss the most famous options that are part of the compiler so one is the compile effort this is the map effort this is called the compile effort the default option is medium design compiler will find a good mapping but it will not use some of the Pt and Pt and Pt is medium is appropriate for getting a quick idea of your area from timing it should be used for most cases let's say if you feel that you have you are still left with some operation or you feel that you should get a lower area still you can use a map effort height please note by using map effort height there are times will increase they might increase significantly from the category so it will use some of the strategies that it did not use in the medium so this part is used for some critical design right other is the incremental compile incremental compile test we see that incremental compile is usually the second pass onwards that means at first you should run without the incremental compile option that is the whole compile process should take place and then let's say now after the compile is done the whole compile is done now you want to feel you want to think that okay now I feel that one of the input delay is slightly low I want to increase that you can do that and then do an incremental compile what this will do is incremental compile the portions of the design that are already mapped are exempt from logic level optimization but it will use a new constraint new input delay constraint to fix any timing model it will try to fix any time model that might arise out of changing a small constraint let's say changing an input delay output delay and a routine design will be either same if no improvements can be made or slightly better in terms of design method there are some cases where designer operators are re-elected also so such a swap if that swap can improve the optimization part based on the constraints so incremental compile is just to see if you made small changes to your constraint you can use this minus incremental compile option to quickly get an improved net list if possible so some figures in let's say for a design it takes a task to do a full compile it might take just one hour to do an incremental compile please do not think that let's say if you want to increase the clock frequency increasing the clock frequency is not a small change it's a big change in such cases I would recommend go for a full compile but for small changes such as changing the input delay a bit or changing the driving cell of some input a bit or changing the load on the output code you can use incremental compile there is one option called boundary optimization if you enable the boundary optimization DC will optimize across height of the boundary this means that a module function in RTL so the design implementation of a module could now be different from RTL of a set design on the top level so in most of the cases where boundary optimization is enabled it might happen that input or output ports are complemented as a result of this process and thus the design the necklace of that sub design will not be functionally equivalent to the RTL so you could use this carefully if we if we output and input ports are complemented then the port names are changed port names of the sub design not the top level design using this variable another option is scan this specifies that the compile command should use the scan the flop now when you use the when you do the first level of compile without scan now a flop a non scan flop and a flop with scan functionality as area difference the one with the scan will have a larger area somewhat larger area now a non scan design ultimately will be scanned right so for getting the complete accurate idea of the area figure you should use this option why because in this option DC will start using the scan flop it will not do anything else it will just use scan flip flop it will not this scan change it will not do anything else so now this netlist which has the scan flip flop will give a better idea of the area of the actual area right so I am assuming that if you are not familiar with scan you could to read some basic stuff on scan what are the type of scan technique and what are the basics of DFT what is the difference between a scan flip flop and a normal flip flop this course does not focus on DFT it will assume that you have some basic knowledge of it so by accounting for the by accounting for the impact of internal scan function from the start this test will eliminate the need for future reopening so it is a good thing to have so apart from these options there are multiple options exact map and so on you could read more about it there will be examples so as and when we proceed in this course we will see some of the examples and then I will explain the option this option is very important very interesting gate clock so I will have a couple of lectures on power we can discuss this gate clock during this during the power difference so this gate clock is used to save power save dynamic power we will see how and we will see what this option does so so this is so we saw the different compile strategy top down bottom up we saw how to resolve multiple instances using the unit math process or compile one and don't touch the input command then we saw the action compile command so there are two commands as I said before compile and compile extra in this lecture we have seen the compile command in unit 4 we will see the compile extra command you might not use compile extra command but the compile extra has a lot of advanced synthesis features so between unit 4 and unit 5 sorry unit 3 and unit 4 just before unit 4 I would recommend you to be comfortable with this command so you can understand the advanced features only if you understand the basic features so this compile command has lot of basic features read about this compile command try out different variations see what each of this option does to your network does to your optimization read more about it and when we start unit 4 it will help you to understand the compile extra command and some of the advanced synthesis features log in thank you