 Hello and welcome to this presentation of the STM32U5 General Purpose IO Interface. It covers the General Purpose input and output interface and how it allows connectivity to the environment around the microcontroller. The number of GPIOs depends on the STM32U5 product and package. Refer to the product datasheet for availability of peripherals according to package size. The maximum frequency for very high-speed capable GPIOs is 166 MHz. It is 133 MHz for the other GPIOs. VDDIO2 is the external power supply for 14 input outputs. Port G15 down to 2. The VDDIO2 voltage level is independent of the VDD voltage and must preferably be connected to VDD when PG152 are not used. The LPG-PIO allows dynamic input-output control in stop-to mode thanks to low-power DMA. Up to 16 input outputs can be configured as LPG-PIOs. Some input outputs have the capability to increase their maximum speed at low voltage when configured in HSLV mode. They are identified by the suffix H in the datasheet. The IO HSLV bit controls whether the input output speed is optimized to operate at 3.3V default setting or at 1.8V. HSLV equals 1. Caution, the input output HSLV configuration bit must not be set if the input output supply, VDD or VDDIO2, is above 2.7V. Setting it while the voltage is higher than 2.7V can damage the device. The input output HSLV bit can be only set when the corresponding option bit is activated. IO VDD HSLV or IO VDDIO2 HSLV depending on the input output supply. There is no hardware protection associated with this feature so it is recommended to use it only as a static configuration for fixed input output supply. High speed low voltage should be disabled unless all input outputs connected to a particular peripheral support this capability. The input output commutation slew rate affecting rise and fall times can be adapted by software depending on process, voltage and temperatures conditions in order to reduce the input output noise on the power supply. The compensation cell can be used only when VDDIOX is within the range of 1.6V to 3.6V. Three compensation cells are embedded, one for the input output supplied by VDD, one for the input output supplied by VDDIO2 and one dedicated to GPIOs with HSPI alternate functions AF capabilities. The input output compensation cell generates NATE bit value for the input output buffer, 4 bits for NMOS and 4 bits for PMOS which depends on PVT operating conditions, process, voltage, temperature. These bits are used to control the current slew rate and output impedance in the input output buffer. By default, the compensation cells are disabled and a fixed code is applied to all input outputs. The following sequence should be implemented to enable the compensation cells. One, the HSI is used by the compensation cells and must be enabled. Two, enable the compensation cells in the CIS-CFG compensation cell control status register. Three, when enabled the compensation cell tracks the PVT and the 8-bit code is available in CIS-CFG CCVR once the ready bit is set. Four, if the code selection bit is cleared, the input output receives the code from CIS-CFG CCVR resulting from the compensation cell. To reduce the power consumption, it is recommended to copy the code from CIS-CFG CCVR to CIS-CFG CCCR. After the result is ready, set the code selection bit and disable the compensation cell. When the code selection bit is set, VDD input output codes are received from the CIS-CFG compensation cell code register and not from the cell which reduces the consumption. The following slides indicate how to select the O-speed value in the GPIO port output speed register according to the following parameters. VDD IO power supply range, high speed low voltage mode enabled or disabled. For each O-speed value, the maximum frequency also depends on the capacitive load. The same assumptions apply to all tables in order to perform coherent comparisons. 50 picofarad for O-speed equal to 0, 30 picofarad for O-speed equal to 1, 10 picofarad for O-speed equal to 2 and 3. The larger the capacitive load, the lower the maximum frequency. This presentation does not provide the exhaustive list of all combinations. Please refer to the datasheet. The table in this slide is relevant when the VDD IO power supply is greater than or equal to 2.7 volts. The first column contains the value to be programmed in the O-speed field. The second column applies to all input outputs except 5 volt tolerant input outputs with USB Type-C power delivery function. When very high speed is chosen, a second parameter has to be taken into account, the very high speed capability. Very high speed configuration should not be selected unless all input outputs connected to a particular peripheral support this capability. The third column applies to 5 volt tolerant input outputs with the USB Type-C power delivery function. This table is relevant when the VDD IO power supply is in the range of 1.58 to 2.7 volts and high speed low voltage mode is enabled. In comparison to the table on the next slide, the maximum frequency is higher when HSLV is enabled. This table is relevant when the VDD IO power supply is in the range of 1.58 to 2.7 volts and high speed low voltage mode is disabled. The third column applies to 5 volt tolerant input outputs with the USB Type-C power delivery function. Note that the maximum frequency of these FTC input outputs is always provided for a 50 picofarad capacitive load. This table is relevant when the VDD IO power supply is in the range of 1.08 to 1.58 volts and high speed low voltage mode is enabled. This table is relevant when the VDD IO power supply is in the range of 1.08 to 1.58 volts and high speed low voltage mode is disabled. When the trust zone is active, each input output pin of the GPIO port can be individually configured as secure through the GPIO-X SECC FGR register. When the selected input output pin is configured as secure, its corresponding configuration bits for alternate function, mode selection and input output data are secure against a non-secure access. In the case of a non-secure access, these fields are Rata 0 and writes are ignored. Input outputs with peripheral functions are also conditioned by the peripheral security configuration. In peripherals for which the input output pin selection is done, through alternate function registers, if the peripheral is configured as secure, it cannot be connected to a non-secure input output pin. If this is not respected, the input data to the secure peripheral is forced to zero and the output pin value is forced to zero, thus avoiding any secure information leak through non-secure input outputs. For input outputs with analog switches directly controlled by peripherals, such as the ADC for instance, if the input output is secure, the input output analog switch cannot be controlled by a non-secure peripheral. If this is not respected, the switch remains open. This prevents the redirection of secure data to non-secure peripheral or input output through the analog path. The pin function is generally controlled by the GPIO alternate function registers. However, the so-called additional functions are directly selected and enabled through peripheral registers not involving the GPIO module. Some of the paths between the input outputs additional functions and peripherals are not blocked if the input output is secure and the peripheral is non-secure. Therefore, it is recommended to configure those peripherals as secure, even when not used by the application. The list of these additional functions is indicated on the right. The GPIO module filters out accesses to its memory mapped registers according to the security level, but not the privileged level. The STM32U5 supports low-power background autonomous mode, LPBAM, which allows peripherals to be functional and autonomous in stop-0, stop-1, and stop-2 modes without any software running. In stop-2, only 16 low-power GPIOs remain functional. Each of them can be enabled independently by programming its alternate function as lower GPIO. Then, LP GPIO-specific registers are used to capture data when configured as an input or to force the state when configured as an output. The security attribute is programmed in the associated GPIO security configuration register. An example of LPBAM is shown on the right. A low-power timer periodically triggers a DMA transfer, which writes data from SRAM4 to LP GPIO registers in order to generate a particular waveform. Making a LED blink is an example. GPIOs are active in run, sleep, stop-0, and stop-1 modes. Low-power GPIOs are active in run, sleep, stop-0, stop-1, and stop-2 modes. In stop-3, standby and shutdown the only available configuration is input with internal pull-up, pull-down resistor, or floating input. When exiting shutdown mode, the input-output configuration is lost. When the microcontroller is under reset, most input-output pins are forced onto an analog input mode. Thank you for attending this presentation on STM32U5's GPIO and LP GPIO. Please refer to the following presentations for more information if needed. USB Type-C Power Delivery, UCPD, Power Management, PWR, Low-Power Background Autonomous Mode, LPBAM