 Hello and welcome to this presentation of the System Configuration Controller. STM32WL5 devices feature a set of configuration registers. The System Configuration Controller gives access to the following features. Remapping memory areas to Cortex-M4 address zero, multiplexing GPIOs to the internal interconnect DXTI signals, certain robustness features, SRAM2 write protection and erase, the configuration of the 20 mA high-drive IOs used for the I2C Fast Mode Plus and peripheral interrupt pre-masking for the two CPUs. Pictured here is the 4GB linear address mapping of the STM32WL5 microcontroller. The flash memory is up to 256 kilobytes in a single bank configuration. The SRAM total size is 64 kilobytes. It is split into two parts. SRAM1 is 32 kilobytes, starting from address 0xx2000000 and SRAM2 backup RAM is 32 kilobytes, starting from address 0x2000800 and also aliased at the Cortex-M4 address 0x1000000. Both SRAM1 and SRAM2 are located in the usual ARM memory space for RAM on the S-Buds. SRAM2 can also be accessed directly through Cortex-M4 data code and instruction code buses, allowing zero weight states used for code execution. The memory remap at Cortex-M4 address 0 allows the boost of the performance thanks to instruction and data bus access instead of using the system bus. The memory remap at address 0 is selected using the mem mode bits in the system configuration remap register. They allow the selection of either the main flash memory or the system flash memory, the SRAM1. Here we have the STM32WL5 bus matrix. The bus masters are shown on top, the Cortex-M4 core, the Cortex-M0 plus core and the two DMA controllers communicate with the bus slaves, shown on the right via the circled intersections. The flash memory is read through the accelerator. Cortex-M4 instructions are fetched through the instruction bus and literal pools are read through the data bus. The SRAM1 is accessed by default by the system bus and can be accessed through I-Bus and D-Bus when it is remapped at address 0, shown by the dark blue circles in order to increase performance. SRAM2 is accessible through the I-Bus and D-Bus allowing zero weight state code execution and through the S-Bus. The AHB1, AHB2 and AHB3 peripherals are also accessible through the S-Bus. The Cortex-M0 plus also reads the flash memory through the adaptive real-time accelerator or ART and has access to the SRAM1 and SRAM2 memories and the AHB1, AHB2 and AHB shared peripherals. The two DMAs can access all memories and peripherals. Different bus masters are able to access different memories and peripherals simultaneously via the bus matrix, enabling high performance computing operations. Simultaneous master accesses to the same bus is handled via round-raven arbitration. There are three Cortex-M4 boot modes, user flash, system memory bootloader and SRAM1. Which are selected by the nboot0 option bit or the boot0 pin, the option bit named nboot1 and the option bit named bootlock. When the boot0, nboot1 and bootlock option bits are set to 0, the STM32WL5 holds the Cortex-M4 and boots on the Cortex-M0 plus. The standard method to get the STM32WL5 Cortex-M4 core booting from user flash is to set nboot1 equals 1 and boot0 and bootlock option bits to 0. There are two Cortex-M0 plus boot modes. One is defined by the secure boot reset vector and the CPU2 boot option. The other boot mode starts from system memory secure firmware install. The two modes are selected by the nboot0 option bit or the boot0 pin, the option bit named nboot1 and the option bit named cboot2 lock. When the boot0, nboot1 and bootlock option bits are set to 0, the STM32WL5 holds the Cortex-M4 and boots on the Cortex-M0 plus secure firmware install located in the system memory. The standard method to get to the STM32WL5 booting on the Cortex-M4 core in user flash and then the Cortex-M0 plus booting is to set the C2 boot bit in the power controller. The memory address the Cortex-M0 plus boots from is defined by the secure boot reset vector and the CPU2 boot option. This allows the Cortex-M0 plus to boot from any word aligned address in user flash or SRAM memory. The boot0 pin or nboot0 option bit is selected by another option bit, nswboot0. The on-chip bootloader allows the user to program the flash memory through a serial communications peripheral. The supported protocols are USART and SPI. The on-chip secure firmware install allows the user to securely install Cortex-M4 and Cortex-M0 plus software in the flash memory. The 32 kilobytes of SRAM 2 is particularly suitable for performance, integrity and safety and low power operations. From the Cortex-M4 core, the SRAM 2 is accessed through the data and instruction buses without any remapping, which enables code execution at zero weight states. The SRAM 2 memory is accessible by both CPUs through the S-Bus allowing RAM address continuity between SRAM 1 and SRAM 2 memories. The SRAM 2 supports parity check. The data bus width is 36 bits with 4 bits available for parity check, one bit per byte in order to increase memory robustness, as required, for instance, by Class B or SIL standards. Class B and SIL are safety standards. Class B is for home appliances and SIL for the safety integrity level. The parity bits are computed and stored when writing into the SRAM memory. Then they are automatically checked when reading. If one bit fails, a non-maskable interrupt or NMI is generated. The same error can also be linked to the break input of the timers. The 32 byte SRAM 2 content can optionally be retained in standby mode. The SRAM 2 memory is also suitable for secure applications. It can be write protected with a 1 kilobyte granularity. The SRAM 2 can also be read out protected via the RDP option byte. When protected, the SRAM 2 cannot be read or written by the JTAG or the serial wire debug port when the boot in system flash or boot from SRAM memory is selected. The SRAM 2 is erased when the read out protection is changed from level 1 to level 0. Please refer to the system memory protections training for further details. The SRAM 2 can be erased by software by setting the SRAM 2 ER bit in the SRAM 2 system configuration control and status register. The SRAM 2 can also be erased with the system reset depending on the option bit SRAM 2 RST in the user option bytes. Part of the SRAM 2 can be made secure via user option bytes, only giving the Cortex M0 plus core exclusive access to those areas. The system configuration register 2 contains the control and status bits linked to safety and robustness such as the SRAM 2 parity error flag and the control bits to steer some error detection events to the timer's break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events include a flash error code correction event, a power voltage detector event, an SRAM 2 parity error event, and the Cortex M4 hard faults. The system configuration controller manages the selection of the GPIO as interconnect EXTI signal. This can be used as asynchronous external interrupt or event with capability to wake any MCU up from the stop state and also as an internal interconnect trigger signal to peripherals. See interconnect matrix training for more information. Other configurations are the I2C FAST mode plus 20 mA drive enable on the I2C 1 and I2C 3 IOs. The high drive mode can even be used when the pins are not used as I2C alternate functions. For instance, they can be used to drive LEDs. The IO analog switch voltage booster can also be enabled. Peripheral interrupts sharing the same NVIC vector have a mask to prevent them from interrupting both CPUs. In addition to this training, you can refer to the reset and clock control, power controller, interrupts, flash and system memory protections, timers, I2C trainings. For more details, please refer to application notes AN2606 STM32 microcontroller system memory boot mode and AN4435 guidelines for obtaining UL-CSA-IEC 6335 class B certification in any STM32 application.