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Published on Feb 15, 2013
http://www.zuken.com/cadstar - This video is a real time demonstration outlining the new and improved process for constraining Enets for minimum and maximum allowable Single ended Impedance, within a schematic. The constraints are then used by the PCB designer using P.R.Editor XR HS to verify and control trace widths based on actual layer stack details using the supplied field solver. Impedance templates are demonstrated to also control Zdiff or differential mode impedance characteristics.