 Hello and welcome to this presentation of the STM32F7's Ethernet MAC peripheral. This peripheral is in charge of the media access control layer of Ethernet communication. The peripheral presented in these slides is a media access controller or MAC for Ethernet protocol. It is fully compliant with the IEEE 802.3 standard. The peripheral is involved in applications based on Internet networks. Such applications rely on the TCP-IP layer model as presented in the diagram. The MAC is in charge of the link layer of the TCP-IP communication model. Upper layers are managed by software. For example, transport and Internet layers can be managed by the popular lightweight IP stack. Finally, the physical layer or FI is supported by external components and linked to an RJ45 connector. The key features of the STM32F7 Ethernet MAC peripheral are presented in this slide. The peripheral supports both full and half-duplex modes of operation at either 10 or 100 megabits per second. Auto negotiation between the peripheral and the external FI enables automatic configuration of the operation mode. The external FI is supported through two interface types. The typical media independent interface or MII and the reduced MII that needs half as many pins as the MII. Among the advanced features supported by the peripheral, we can list frame filtering based on MAC address or VLAN tags, precision timing protocol support with high precision time stamping of frames, and several network statistics registers available to monitor the connection quality. In addition to the previous features, the peripheral brings several types of heavy processing offloading. It supports automatic management of preamble and start-of-frame tags, check some checking for received frames, and check some's computation and insertion for transmitted frames. A functional low power mode reduces power consumption by stopping the peripheral until special packets are received. This enables a network-controlled system wake-up. This slide presents the offload processing managed by the peripheral on an Ethernet datagram. You can see that most of the non-payload part of the datagram is efficiently managed in hardware. The preamble and SFD are basic synchronization patterns and are inserted or deleted automatically. MAC address filtering is recommended to select only the frames that are relevant for your application. The MAC supports multiple filtering options for unicast or multicast address frames and perfect or hash filtering. VLAN tagged frames are supported. Received frames are signaled to the host after VLAN tag comparison. Payload is composed of data from transport or internet layers. The check sum is computed or checked for IPv4 headers and TCP UDP of ICMP payload. Finally, the CRC is computed for the whole datagram without taking into account the preamble and the start of frame tag. The precision timing protocol has been developed to support high precision synchronization between several nodes of an Ethernet network. The targeted precision is approximately one microsecond. This level of precision can only be achieved by hardware support for packet time stamping. STM32F7 supports PTP messages for synchronization and acknowledge. A 64-bit register indicates the current value of the system time maintained by the MAC. A pulse per second signal or PPS can be driven on timer 2 so that the timing drift between slave and master clock can be measured. The external PHY is controlled by the peripheral through the station management interface or SMI that allows read and write access to PHY internal registers. This interface supports the MDIO protocol on a pair of wires. Read and write operation codes are available. Two types of interfaces are supported by the peripheral, both supporting full and half duplex operations at 10 or 100 megabits per second. These interfaces are the classical media independent interface or MII that requires 16 signals between both devices and the reduced MII that requires only 7 signals and then allows IO saving. A functional low power mode enables power consumption saving by stopping the DMA and transmit path clocks. The receive path of the peripheral remains active in order to detect special wake-up packets. This feature enables a system wake-up from sleep or stop mode controlled by the network. This slide presents the peripheral block diagram. The Ethernet peripheral embeds its own DMA for autonomous direct memory interface. Internal FIFOs for RX and TXQs for data flow management. A media access controller or MAC supporting most functional features detailed in previous slides. Offload engines, precision timing protocol, power management or PMT and MAC management counters for statistics gathering. And a PHY interface block supporting media independent interface or MII and reduced MII. The Ethernet MAC peripheral supports various interrupts. All these interrupt lines can be masked and converged to the same output signal as you can see on the diagram. For transmission and reception interrupts, a distinction is made between normal and abnormal operations. Abnormal operations refer to process aborted or FIFOs in overflow or underflow state. Special MAC features have their own interrupts. In low power mode, wake-up packet reception is signaled on the PMT line. Any update of MMC counters can trigger an interrupt too. And finally, an interrupt line is dedicated to the precision timing protocol. Here is an overview of the peripheral status in each of the low power modes. Only PMT mode is available in stop mode. In this mode, the peripheral waits for wake-up packets. The Ethernet is compliant with the following standards. IEEE 802.3 2002 for Ethernet MAC. IEEE 1588-2008 standard for precision networked clock synchronization. And RMII specification from the RMII consortium.