 So, welcome to this lecture on programmable logic devices in the course digital system design with PLDs and FPGAs. The last lecture we have seen the simple PLDs which has registers which allows one to implement data path and sequential circuit. Also we have seen some kind of fitting exercises because not all resources are there how some techniques are used to fit the design optimally in those structures and how like a what is available today a versatile simple PLD like 22V10. We have seen that in detail and as I said mostly we have seen this because when we go to CPLD without much explanation because we have learnt all the basics and it is very easy to understand them looking at this evolution of these simple PLDs to CPLD that was the idea. So before getting on to the CPLDs and maybe some slight exercises we will look at the last lecture slides quickly. So the last lecture we have basically we have seen this structure we said this can be this can implement output by enabling this disabling it can be input and this product term can control it as output or IO like a read bar can make it as a input then read bar is why it is output and this can be used for cascading like you have more than 7 product terms then it 7 can be implemented here an inversion second inversion and that can be tapped here you can implement and so on. Also this can be used for cascading can be used for feedback we have seen you can build a cross coupled latch between these two sections using a NAND gate here going to the NAND gate here and coming back to the NAND gate there and of course with set and reset input it is possible. So we have listed all that all those facilities and we have looked at the cascading scenario suppose we have 17 product terms one way of doing is that you implement 7 here take that 7 and put it to 1 NAND gate and then you are left with 6 product terms that you implement in 6 NAND gates then that is make 13 and we need 4 more. So take this and put it here and you the last section will use 4 NAND gates and these two are disabled by retaining the connection or the fuses. But this will incur 1, 2 and 3 pass delay so it is not a good idea so the ideal thing will be to implement 7 here, 7 here and you take both these 7 product term to a third one and use NAND gate to cascade it and use the rest 3 here ok. So that will make a kind of 2 pass and you can go all the way in a 16, 8 kind of device maximum you can use one last section with a 7 NAND gate for cascading and rest all section with the previous section with 7 NAND gates so 7 into 7 49 product terms can be implemented with 2 pass delay and that is what we said. If you chain it you will get 8 pass with 49 product term but if you do a 2 pass like that then you will get same 49 product terms but with a very minimal delay that is how you cascade it and we also have looked at the symbol PLD like 16L8, 16R4, 16R8 and these are all with the registers and which is not used and 22V10 nowadays the Atmel you know manufactures them and basically the feature is that it is a very wide decoding that means a product term can have the NAND gate can have 16 inputs and it is complement and this was used in chip select decoding you know in a scenario like this you have MUP, your memory or peripherals so you will connect the address pass maybe this has 20 address say 12 are used for addressing the location 8 are used for decoding so you want me to decode 8 address line higher address line and that is where this PLDs were used and this is the control and data but nowadays what is happening is that many a time these are built into the SOC and this is also built into the SOC which kind of throw out the use of devices like these 16L8 and much more than that you know nowadays the peripherals are not directly mapped to the memory space they have a serial port okay. So you have a serial clock and the IO data in and out and this support I mean the support is elaborate addressing is through the data frame and you can have multiple slaves multiple masters all that you know so this kind of you know removed the need for the simple PLDs you know that is why it is not used very much. And for understanding we have looked at the 16R4 it is nothing but 16LH structures but at the output you have some 4 flip flops and so you have a combination section and registered section a common clock and an output enable important thing is that the Q bar is fed back into this array. So essentially what can be done is that you can have a state flip flops a next state logic with all the inputs and the present state fed back so you can implement the counters okay with the next state logic here and this is the state flip flop and you can even implement a state machine because this feedback the present state can be decoded in this array and generate the more kind of output with combined with the inputs because everything is available here combined with the input you can make it milli output okay. So that is how the data path and if you have a register combinational circuit register even that can be done you can start with inputs going to a register that output is kind of you know computed with a combinational logic that output can go to another flip flop and you can imagine parallel kind of data within the constraints suppose you have a device like 16R8 then you know that is not shown here but then you have all the registers then you can have maybe little more data bus width in that case and we have seen how this is mapped you know data path combinational data path. So you start with the source register with inputs coming in because the inputs are available to every with every kind of section then that present state is fed back and then you have an exit the combinational logic the output go to the destination register. And if you have a state machine you have the flip flop input and the present state comes here and output and the present state goes to output logic. So exactly same you have the inputs you have the state flip flop the feedback is here. So input and the present state is combined in an exit logic and goes to the state flip flop the present state and input is again decoded to produce output. So it is a it looks like you know this structure itself is converted into this form and it is very nicely so it is a nice kind of architecture wherein the sequential circuits can be easily implemented in a PAL and whether you look at this way or this way does not matter you know maybe this is ideal because you have a you know kind of say if you view like that you know you have the next state logic and output logic here all the inputs and the present state is coming. So this form the next state logic and rest of the part forms the output logic okay. So that is how the sequential circuit and data path maps into this and one thing I said that suppose you are implementing kind of say two product terms here okay. Say take an example x is AB bar and CD and that x is implemented here and y is nothing but this x plus two other product terms. So one way of implementing is that x you implement two product terms y you implement the feedback maybe x you implement here that x you combine in one product term and implement the next two product terms here but then the delay will be two pass. So it is easy if we can replicate that product terms here substitute okay. So that is what is done here. So instead of using a node here already implemented node we substitute this product term and straight away implement that because the product terms are available okay. So this is called virtual substitution but this can go wrong like in the case of an XOR because in this simple structure there is no XOR and AXOR B is AB bar or A bar B and when you take three XOR then you will end up with four product terms NXOR 2 raise to N-1 product terms. And so if it goes on expanding then suppose you have say 10 XOR gate then you will end up with 2 raise to 9 which is 5 tall product terms which may not be available in a simple PLE. So when you implement XOR kind of circuit priority encoder the arithmetic circuit where XOR is there if substitution is kind of implemented then there is a problem and this is like it is better to implement kind of do not do the substitution like you implement AXOR B then in the next section you XOR with the C because you implement two product terms in one and bring it here and do the XOR another two product terms here then you know keep on expanding you know. So that is why that the substitution may have to be turned off to avoid this kind of cases and the last we have seen is the 22V10 which combines the utility of symbol combinational device like 16L8 and 16R8 wherein you have something called a macrocell which is nothing but flip flops with bypass. So that this section can be used along with the register or directly okay and you have the clock common clock to the flip flop and the feedback can be from internally if it is the flip flop is used if it is bypass then the feedback is from here okay and if you are using all section like combinational kind of logic then this clock is not required that is used as input the variable product terms first section has 8, 10, 12, 14, 16 and then it is mirrored down. There is a product term controlling the asynchronous reset and another product term which is controlling the synchronous preset so quite versatile and we have seen what is inside this. So basically and or then there is a register but there is a MUX wherein you can use the combinational output directly or the registered output and you can use the combinational or its complement Q or Q bar and this allows you to apply the De Morgan's theorem and optimise the product term. Suppose you are using section with 8 product terms and you implement Y so normally say if you use Y then you implement Y here go through this inverter this inverter you get it. But suppose that has more than 8 product terms you implement Y bar here I mean Y bar here it may reduce to say less than 8 and you can implement it here then you invert here. So this section allows a product term optimisation and this is the feedback MUX choosing the Q bar or the input and this is the product term which is controlling the tri-state enabled. So this combines this can act as a 16L8 or 16R8 you know that kind of flexibility is there and this is available now this can be used. So the features we have seen you have variable product terms asynchronous preset you can use it as combinational or registered output product term optimisation and an example we have seen like there is a Y with 4 product terms so you do the De Morgan's theorem then minimise it you end up with 2 product terms. And these are the kind of delays you have propagation delay when it is used as combinational kind of section this is the delay of the tri-state gate then you have the flip-flop which set up and hold time the TCQ we have discussed this and the kind of reset delay with asynchronous reset and all that okay. And then without feedback we can kind of you can work out you know suppose you have a combinational section with feedback then you have to kind of add all that delay in you know with feedback you will have some extra delay because there is a MUX and that we added to that. So that is the timing of the PAL-22V10 so I am putting a kind of question this is an exercise kind of thing question is that is it possible to implement an 8 bit odd parity generator in a PLD-22V10 that means parity generator has 8 data inputs and 1 parity output. So you know that this parity generator is nothing but you know you have suppose you know I1, X or I2, X or I3 like that it goes okay. So first thing when you try to address that there are 2 things to check you know you have a 22V10 okay that you know the 22V10 internal. So you have kind of 12 inputs dedicated input 10 dedicated output we have to check whether input and outputs are you know sufficient to implement this function. And second thing to look is that whether the number of product terms are enough okay. So let us check that you know and the IO requirement is that number of inputs is 8 because it is an 8 bit parity generator but we have 12 dedicated outputs. So 8 is okay now sorry this is 8 less than so in a hurry I put it greater so 8 less than 12 so you have you know that is sufficient and number of output is 1 less than 10 output of 22V10 this should be enough. So I apologise this you treat it as you know less than okay and we do not have any XOR gate in 22V10 neither in the combinational and or section nor in the macro cell anywhere okay because there could be some PLDs where there is an XOR gate you know at the output we will see that in CPLDs okay. So there is no XOR so we have to the tool has to kind of expand this in terms of and or gates okay. Now we assume like for this we assume that we are implementing the substitution we are expanding it okay that is what we assume that we are assuming that it is expanded okay substituted. So XOR of n-variable that means we are not implementing intermediate nodes okay we are expanding it. So maybe that assumption one can write here. So for n variables we have seen just in the previous lecture there are 2 raise to n-1 product terms. So that is why if the odd number of input bits are 1 then the output is 1 so from there you can understand that. So for 8 bit inputs we need 128 product terms because 2 raise to 7 product terms are there but if you look at the total product terms available in a 22V10 PLD is 8 plus you know 8 into 2 plus 10 into 2 12 into 2 14 into 2 16 into 2 okay. And that we will end up with you know 120 product terms but we have 128 product terms much more than that we have to cascade okay. And we have 10 sections so one we use for cascading then we have 9 sections for cascading. So we have to use a section with 10 product terms for cascading. So we are left with 120-10 product terms. So we have only 110 product terms hence these resources are not enough okay. So it cannot be fitted okay. So provided I mean we are assuming that we are expanding we are keeping the delay minimal we are not kind of implementing the intermediate node you know it is possible that you implement an XOR gate then cascade it to the next XOR gate cascade it to the next XOR gate then it will be possible to implement but then it will incur lot of delays okay. So you can approach various other ways you know you can think of a tree implementation you know wherein you can start with some 4 XOR gate to input XOR gate then it goes to the kind of a logarithmic reduction can be applied then it is possible to implement. But I am discussing the case where normally the tools kind of substitute expanded in that case it will not be able to fit in and that is the case with minimal delay but a cascading some kind of chain cascading or kind of logarithmic kind of cascading binary kind of you know 8, 4, 2, 1 that kind of cascading will work with you know this 22-bit and fitting maybe you have to kind of manually little bit give attributes to do that. So that is I mean one advantage of knowing the architecture and the tool is that you can work quickly work out whether something fits in and that I want to highlight because if you have no idea of the architecture you will not be able to exploit these kind of situation okay. So if you know that using the tool attributes using some kind of coding techniques you can get out of the kind of you know bad situation to implement something and which many times people ignore and that is true when we go to CPLD or FPGA to know the architecture. And we also know that given something whether it really fits in whether the device is able to kind of implement that thing and the resources are enough you can do a rough kind of estimate wherein whether the given circuit given logic fits into the device so that is possible. So that is the advantage of learning the architecture learning how the circuit maps into that and I have taught you when we discuss VHDL we know given a VHDL code how an RTL circuit or the equivalent logic circuit can be inferred. So if you apply that knowledge and somebody has given a VHDL code so I am sure you can work out the logic which that the tool synthesizes and you check in the target device whether it can fit in all this can be kind of even in a complex design when you break into pieces you can estimate it it does not take much time. And you can rightly choose the devices and something goes wrong like if like you try to fit something in a 22V10 and it says that it cannot fit. So looking at the reports you can make out what is going wrong you know maybe the implementing it as an internal node or using some different cascade structure you can implement old thing with minimal delay all this can be done it is a very simple kind of device, simple cases but having that knowledge will enable you to do many optimization which a novice or those who are just working with the tool with some kind of VLOG or VHDL will not be able to do it okay. So applications of the SPLE is that you can implement some glue logic glue means that you already have chips for say microprocessor memory some embedded system but some random logic some simple logic you need to implement for whatever reason such things can be combined in an SPLE. Now it may not be related maybe while interfacing one chip you need some kind of translation of the bus protocol or some small thing all that can be implemented many things together can be implemented. Because there are you know 22ios and 10 outputs so many things can be done okay. And it definitely you can implement counters small state machine the disadvantage is that such kind of wide decoding the AND gates with lot of inputs are not required in many cases and the number of flip flops are less you know that you take this 22v10 there are 10 flip flops and practically you cannot do much with the 10 flip flops you cannot have any kind of memory implemented here. Suppose you need a shadow register that cannot be implemented so the because of the lack of registers this though the logic is quite the logic section gives you a lot of product terms but lack of registers limit the use of these devices okay. So that is about the applications of symbol PLD like 22v10 then let us look at the programming technology that means that say 22v10 like devices can be fuse programmable but nowadays it is not used of not very of any kind of practical interest earlier there were fuses I have shown in the initial slide a fuse and you know passing a large current and blowing it then there were IP prompts again is not very much used. These were kind of devices which can be electrically programmed and once you program it to raise it you expose the silicon die through a glass window through to the UV light and some 5 to 10 minutes of exposure will kind of remove the programming okay. Once again this was quite famous maybe 20 years back or 15 years back wherein all the memories if the prom will have a window and you program it and when you want to erase it you expose it to UV light for some time like you cook the you cook the device then it gets erased and not very much used at all not used at all now not required but then we will have a look at those transistors just for the learning purpose because the next technology is kind of related to it okay it is a variation on that. So, the another technology used is EEPROM where it is electrically programmable electrically erasable okay here it is electrically programmable UV erasable but here it is electrically programmable electrically erasable okay basically and there is flash transistor which is kind of similar okay it is not much of a difference construction wise it is different and there are number of erase cycles is more in flash than the EEPROM number of times you can reprogram is more in flash but then kind of the data stability will be more in EEPROM where there is you know there is less susceptible to noise and all that but then again this bit historic nowadays everybody use flash. So, if you use if you ask me the current technology is the flash all these are of kind of little bit historical interest but nice to look at it because the way evolution has happened will teach you something. So, we will look at those these the fuse we have seen these three we will look at it okay. So, this is the EEPROM transistor this transistor is used to construct the AND gate and the OR gates okay and as I said as I mentioned it is a wired AND gate it is a wired OR gate okay. So, we will see how this enables one to implement that wired structure. So, I think you are familiar with the CMOS transistors. So, this shows an N channel or NMOS transistor where there is a substrate is P type. So, normally you will have a big substrate and you will have an P well in that there will be N channel N channel and normal transistors will have a insulator here silicon oxide then there will be a gate polysilicon or copper gate on top of it and normal case there will be only one gate and you what you do is that source you ground drain you give a supply say 3 volt or 5 volt then you apply 5 volt here because of this electrical field the electrons will come here and N channel is formed conduction happens okay. Now, in this EEPROM transistor there is silicon oxide there is a gate which is a polysilicon which is floating which is not connected to anything then there is silicon oxide there is a normal gate control gate. So, the normal case it will act as an N transistor you ground the source you apply the drain voltage you give a gate voltage which is above the threshold voltage because of the electrical field which is to the positive side and electrons come here form a channel it conducts okay. Now, this floating gate allows you to completely turn it off okay when you turn it off it acts like the blowing the fuse okay that is basic idea okay we will see that but why we turn it off is that this control voltage will have no effect on the conduction okay that is how we kind of blow the fuse okay. So, what is done is that you ground the source and you apply the positive voltage to the drain and a brief positive pulse is given here like say the supply voltage is 5 volt maybe you give a 6 volt or 8 volt pulse for a short duration because the electric field is high and this layer is very thin it is only very you know kind of it depends on the technology okay and this is shows that 150 angstrom but it depends on the current device technology compared to the normal silicon oxide thickness it is less okay and what happens is that because of that field electrons travelling to the drain will tunnel through this thin insulating layer and get trapped here okay because it is a conductor okay get trapped here and then you stop it and what happens is that because some electrons are sitting here now to form a channel here you need to apply more voltage here. So, if you apply a 5 volt the gate voltage channel would not be formed and there is no conduction. So, it is like a transistor which in the absence of this captured charge it act like a normal end transistor and when you program it to be off by capturing the electrons then it does in conduct even if you apply. So, it is like blowing the fuse now we use this transistor to build a wired and or wired over structure that is how it is programmed off okay. So, suppose you want to say a particular input does not affect then you just program it off and we will see that structure and to erase it there is no easy way in the case of apron transistor. As I said there is a like these silicon die is in a chip there will be a window on top of it and you expose it to UV these electrons because of the UV radiation will get enough energy and tunnel back and get out you know that is how it is raised okay. So, we will see how a wired structure is formed okay. So, now take this AND gate so what we are trying to build is an AND gate okay with say 32 inputs okay or some kind of some number of inputs and so many AND gates goes to an OR gate okay. Now, these AND gates are built using this transistors okay and it is a wired structure we will see that so this is how it is formed. So, this shows a assume that this line is an AND gate okay this line is another AND gate okay. So, there are 32 inputs then there will be 32 vertical lines as shown in the picture and at the and the between that those vertical lines are connected to the gate of this IPROM transistor. The drain is connected to this common line the source is grounded okay all NMOS transistors with floating gate and this line is pulled up through a resistor or a transistor acting as a resistor you know you can have an NMOS transistor with the gate connected to the VDD can act as a resistor. So, do not think that the resistor is implemented as a passive it can be an you know active circuit because in a single die you can implement transistors easily than again bringing in the passive elements okay. Now, suppose and these vertical lines are connected to the input suppose this is connected to I1 I1 bar I2 I2 bar and so on. Now, if you do not program it off you see when this line is high any of the vertical line is high this transistor will be on and this line is pulled low. So, the logic is that if you retain some connection if you do not program it off if that line is high the output is 0 okay. So, if input is high any one of the input is high output is 0 it is a wired NOR okay. So, it is a NOR circuit okay. So, NOR is like you know there is a OR gate and a NOR gate okay. So, these bubbles are not there but what we want is an AND gate okay. So, we know that again we have you know studied the gates and function but if you invert the A and B okay then it will become an AND gate automatically. So, this structure if you give one input directly it will implement a wired NOR structure because any input is high this line is 0. So, that is a NOR gate but if you invert the input instead of I1 you connect I1 bar then instead of I2 you connect I2 bar then automatically it implements the AND function wired AND function okay. So, that is what is shown normally it is a NOR gate but you invert the inputs then you will get an AND gate as far as the active high circuit is concerned and that is nothing but Y bar is A bar or B bar okay which is nothing but you know Y is you know it is applying the De Morgan theorem if you invert then you get the AND gate okay. Now, that is very easy to do in a PLD because you see that all the inputs are inverted both input and the complement of the input is there. So, how it works is that suppose you connect A this line act as A bar and this inverted line act as A okay. So, you want to program A to this you know this AND gate then what you do is that you retain the connection of you know A bar and you blow the you do not you know put off the connection for you know A. So, instead of where you want to use A use A bar where you want to use A bar use A and since both are available it is a matter of swapping the position of the programming okay. So, that is what I have shown for I1 the I1 bar is used I2, I2 bar is used. So, that is very simple for a like an AND gate with 32 inputs you need 32 EEPROM transistors with a single line with a pull up transistor and similarly you replicate that you know structure you have kind of 7 product terms then 32 into 7 which all goes to an wired OR gate and the same structure is there it is a wired NOR gate. So, you put kind of here you have say 7 input OR gate. So, same thing you know these 7s are going to 7 these kind of transistors with a single line pulled up and you put an inverter inverter you can put with NMOS and PMOS or 2NMOS then you get an inverter. So, this wired OR is nothing but a similar wired NOR with inverter. So, you see how this is programmed using the transistors alone it is very easy that is how it is implemented in a PLD or CPLD and things like that and so wired NOR with input using compliments transistors are EEPROM. So, when programmed there is no connection when you program it off there is no connection and the fixed OR that is the programmable LAN fixed OR is nothing but wired NOR followed by an inverter normal N type transistors are used. So, it is very easy to implement it does not I mean you do not have to worry whether how to kind of implement the 32 input AND gates it is not very complicated logic in terms of transistors okay. Because the wired versions are implemented and let us look at the flash or EEPROM transistors the construction is similar but the gap between the floating gate and this channels are low okay. And you can also see that like if you see the construction will be little different it kind of little more extent over the channels this source and drain. Now what happens is that similar operation you know you just ground the source apply the drain voltage and you give a programming pass of little higher voltage to this gate. So, these electrons there is a field from drain to source there is a field from sorry source to drain electrical field from the substrate towards the gate and because of higher voltage the electron get trapped here. So, it is programmed off but you want to erase that what you do you do not have to expose it to UV you do the opposite okay. You ground the gate you ground you know let it be floating and you apply a higher programming voltage to the source then these electrons tunnel back and you can electrically erase also in the circuit. The advantage with this transistor is that it like you kind of you can electrically program it and you can electrically erase it is very fast than exposing it to UV. The flash is kind of flash and EEPROM the construction wise little difference is there. But one only one problem is that when you program it off this because of the construction even if the gate voltage is less than the threshold voltage it conducts okay. So, this can only be used kind of cut it off and you need a normal transistor in series for really controlling the wired implementing the wired NOR function. So, this is how when you use flash or EEPROM use a normal N transistor for forming the wired NOR structure or wired AN structure with inverse appropriate inversion. And you in series you connect this kind of the flash cell or the EEPROM cell to cut it off when you do not want one input to be connected to this AND gate then that you program it off you know that is how the flash or EEPROM structure is used. So, and the programming interface the programming standard is it used ZEC file it is a company's name it is a standard ASCII file fuse pattern will be 0 and 1 where there is connection it will be 0 where there is no connection will be 1 and the normal pin of the PLD is used for programming. So, there are the address basically you have to address this fuse location or the transistor location to program it. So, there is an address line data line read write line and the program pin. So, how is a higher programming pulse is applied to this program pin then it gets in the program mode then you give address data read write signal in the appropriate kind of with timing it gets you know program then you can use it as a normal device with IOs being used as user IO ok. And the program you put it in the programmer you can erase it and reuse it. So, that is the whole about the SPLD. So, what we have seen today is in the just the previous part is that we have looked at the various you know the one example of fitting and we have taken a kind of parity old parity generator. And we have assumed that we are kind of expanding it in terms of product terms than implementing it in a node and we have found that 8 bit old parity generator with expansion cannot be implemented in a 22-bit. But with internal node you know kind of 1 to 1 picture of a chain of 8 2 input XOR gates or you know you can cascade 4, 2, 1 of 2 input XOR gates all that can be implemented. So, that gives you kind of freedom and as I said that kind of give you an idea how to know the architecture of a device and how to map from even from a VHDL code down to the level of fitting. After some practice you can even start kind of working this in the mind even in a complex circuit by part you know you can take a paper and start working out whether how many flip flops are required, how many sections are required, how much delay it will incur and all that can be calculated you can estimate a rough estimate can be worked out without blindly going to the tool and coding you know playing with the tool and all that it is all possible. But you know you can do that yourself you know that is advantage. Then we have seen the programming technology the fuse we have seen we have seen the EPROM transistors how a floating gate allows the transistors to be cut off that means it can program off the transistor and the same transistor is used to implement a wired AND gate and wired OR gate. Essentially it is a wired OR gate for AND gate we kind of invert the inputs and it is very easy in PLD because all the inputs and their complements are available. So wherever the fuse for or programming for A is done in the A bar section and for A bar you do in the ALA section that is all the difference. So appropriately tools you know take care of programming it and we have looked at and that the problem with the EPROM is that you have to UV raise it takes time more than that you have to take the you know expose the device after some time the device will become unusable. And EPROM and flash allows you to electrically program and electrically raise it and we have seen that structure also. But it conducts normally so we put a normal transistor to form wired AND gate and wired OR gate and put this in series to program it off and that is a basic idea. And symbol PLD applications we have seen it is used for blue logic it is you can implement counters and FSM and it can be used for very small logic. But the lack of flip flops does not you know enable it to be used in complex application. So that is the symbol PLD with this knowledge we can quickly grasp the complex PLD and that is my idea. So let us look at the complex PLDs okay. Now the first thing to look at is that you see that when you say complex PLD say you take this 22V10 structure okay. Already we have a section with 8 product terms, 10 product terms, 12 product terms, 14 and 16 product terms. And as I said most Boolean function does not need all these kind of product terms and the product terms are very wide you know this can implement up to 20 variables and it is complement it is quiet you know complex. Now when you say complex PLD we do not need to scale this up it does not mean that we make a say 100V50 or something like that. It makes no sense you know you have 100 dedicated inputs with maybe say 300 vertical lines and some 25 product terms with you know 100 section it makes no sense it will be wasted it is there is no use okay. But we already know that this structure can implement counters, FSM and you know it can implement the combination logic when you bypass it. So it makes sense to have you know this 22V10 like structures as a building block put multiple of them together and somehow interconnect them. That means that there are set of IO pins, there are set of 22V10 like structures. You should be able to connect the inputs to here or some other section take the output of this section to the input of the next section. So the idea is that maybe in one section you implement a counter and you decode it and that goes to an FSM in another section through a you know kind of IO switch and that section goes to some you know the FSM output goes to control some other thing and so on. So instead of a big PLD the CPLD is we can say is not a big PLD it is a kind of you know hierarchical PLD you know. So it is not like you have multiple SPLD sections interconnected. The requirement is that output of any block a SPLD block should be able to go to one or more input of other blocks to cascade and any input signal should be able to go to the one or more input block okay. So basically you have in a complex PLD or CPLD it is a hierarchical PLD. So you have simple PLD sections interconnected by a switch you know that is called CPLD. And you have a product term RA that means basically AND gates basically product MRA and product M allocator or a distributed that means these product terms are not permanently connected to an OR gate. Depending on your need it can be connected to an OR gate it can be connected to an XOR gate because we have seen the simple PLD kind of lack an XOR gate and that is a major disadvantage because when you try to implement expand XOR gate in terms of product terms it goes out of hand. So it makes sense to have dedicated XOR gate for parity for product term optimization for arithmetic circuit all that it is useful. So XOR gate and so this product term allocator allows you to use AND gate to an OR gate to one of the input of XOR gate or there are macro cell where in flip-flops are there maybe one AND gate can reset the flip-flop one AND gate can set the flip-flop depending on your need. So this allocator we can say it is a small switch which allocates this product term to various need whether it can be used directly outside to the OR gate XOR gate or the flip-flop controller so that nothing is wasted okay. So if you permanently connected connect some AND gate to an OR gate say there are 5 AND gates it is connected to an OR gate but we are only need one AND gate but we could have used that another AND gate to the input of an XOR gate okay. So this allows flexibility this allocator or a distributor nothing but a switch which connect the output of AND gate to the various inputs of the OR gate XOR gate flip-flops and things like that. And a macro cell is like a 22V10 which has a flip-flop with bypass and so on and the IO cell is nothing but IO pin with the tri-state gate with an input so it can be used as output input IO can be used for feedback. And there is a programmable interconnect which interconnect this simple PLD section. So huge switch which take the output of one section to the input of other sections any input signal can be taken to the input of any sections and so on. So that is the programmable interconnect so basically any CPLD you look at it there will be multiple simple PLD section a interconnect which interconnects the IO pins and the PLD section. Within this PLD section you have a product MRA basically AND gates a product M allocator which allocates AND gates to the various combinational and registers you have registers with feedback then the IO pins you know that constitutes a CPLD and we will see some example of the commercial CPLD available today and see how this is kind of this architecture is implemented okay. So basically as I said these are kind of simple PLD section interconnected and if you look at the silings manufacturer then you have two series of devices XC9500XL okay. This is a CPLD which was there from very beginning and the cool runner two series of family. The architecture is similar only thing is that as the name suggests it has very low power dissipation that is why it is called cool runner and when it comes to Altera they have a series called Max 3000, A max 7000 and there are very different variation max to max 5 all that. So there are at least four families and Atmel has 80 of 15 series you know with some numbers. Latest semiconductor has ISP Mac 4000 ZE family. So you have quite a bit of choices between silings Altera Atmel and Latest Semiconductor and if you look at the architecture it is all kind of similar architecture at least I know that this silings architecture and Altera architecture are somewhat kind of similar. So for this kind of discussion I will take the max 7000 as an example to show you the architecture which is can be easily applicable to the silings architecture there is no much difference at all. If you look at the data sheet you would find that it is quite similar and whatever I am discussing for this can be applied to this both of these okay. So maybe that we do in the next lecture because we are kind of coming to the close of this lecture. So the complex PLD is not a big simple PLD because it makes no sense because simple PLDs already has lot of product terms which support lot of inputs. And what we need is that and we have seen that counters state machine random logic can be implemented. So when there is a medium kind of or low complexity some particular circuit we will discuss that what kind of application can be used. Then it makes sense to have multiple simple PLD section interconnected and we have seen what kind of interconnection. The IO pin should go to the input of any section, output of any section should go to any of the input of the other sections okay. So that we can kind of interconnect this section to implement some reasonable logic. So it has a PLD section multiple PLD sections interconnect RA, a product term RA which is composed of AND gates, product term allocator which allocates the AND gates to the OR gate XOR gates of flip flops, a macro cell which consists of various you know the XOR gates, the OR gates, the flip flops, the bypass and so on which allow with lot of more control, more flexibility than a CPLD. That means you are able to connect a global clock or a product term clock, global reset or a product term reset. So you have more flexibility in CPLD than in a simple PLD. So we will and we have seen some kind of you know available products from the Xilinx, Altaira, Atmel and Lattice semiconductors. And as I said in the next lecture we will take an example of Mach 7000 series of Altaira. We will see the architecture, we will see some kind of code how it maps into this device and so on. And then we will wind up the, we will see the application where it can be used and then we will wind up the PLD part and we will move on to the FPGA and we will find what is the difference between the PLDs and FPGAs and so on. So I urge you to go through this portion for yourself you imagine some kind of logic, work out how it fits in. Maybe I have told an example of a priority circuit, maybe you can think of a counter how it fits in, what is the basic Boolean equation, how it fits in a PLD like 22V10, what is the delay and so on. So I wish you all the best and thank you.