 Hello and welcome to this presentation of the STM32 Ciclic Redundancy Check Calculation Unit. It covers all the features of this unit, which generates a code to detect errors. CRC stands for Ciclic Redundancy Check. The CRC Calculation Unit is used to generate a CRC code on 8, 16, or 32 bits of data using a configurable polynomial value and size. The CRC-based techniques can be used to verify data transmission or storage integrity. The CRC Calculation can also be used to compute the signature of the application software during run time to be compared with a reference signature generated at link time and stored at a given memory location. Thanks to the full configurability of the STM32 CRC Calculation Unit, software overhead is reduced to a minimum. Additionally, the DMA controller can be used for back-to-back CRC calculations over a large block of data while the CPU is performing other tasks or in sleep mode. The CRC Calculation Unit integrated in the STM32 features a fully programmable odd value polynomial with a programmable size of 7, 8, 16, or 32 bits. The initial value is also fully programmable allowing for very flexible run time CRC code generation. The peripheral can be configured to support the big or little endian formats of the input and output data supporting various communication protocols. The CRC Calculation Unit is connected to the AHB bus interface for an optimal performance. It contains a single 32-bit register which is used for both writing and reading by either the CPU or DMA controller. The initial value, input output bit reversal, and polynomial coefficients are configured by the software during the initialization phase before starting a new CRC calculation. The CRC computation engine will hold the result of any previous CRC calculation which then becomes the initial value for the next calculation, thus allowing a new CRC computation of a data block. The input and output format is fully configurable to reduce the software overhead. It allows the application to manage different endian schemes. The input data can be reversed and performed on 8, 16, or 32 bits depending on the rev in 1 to 0 bits in the CRC CR register. For example, input data 0x1a2b3c4d is used for CRC calculation as 0x58d43cb2 with bit reversal done by byte, 0xd458b23c with bit reversal done by half word, and 0xb23cd458 with bit reversal done on the full word. The output data can also be reversed by setting the rev output in the CRC CR register. The operation is done at bit level. For example, output data 0x11223344 is converted into 0x22cc4488. The CRC data register includes an output buffer, which allows for immediate writes by the CPU or DMA peripheral of a second data word without waiting for any wait states due to an active CRC computation. The CRC data register can be accessed by word, right-aligned half word, and right-aligned byte. The duration of the computation depends on the data width. 4 AHB clock cycles for 32-bit blocks, 2 AHB clock cycles for 16-bit blocks, and 1 AHB clock cycle for 8-bit blocks. The DMA controller can be used for writing to the CRC engine. This offloads the CPU for other tasks and can be used for back-to-back calculations for verifying code or data integrity. This slide summarizes the power modes in which the CRC calculation unit is available. The CRC calculation unit needs the main AHB clock to operate.