 Hello, and welcome to this presentation of the STM32 Universal Synchronous Asynchronous Receiver Transmitter Interface. It covers the main features of this USART interface, which is widely used for serial communications in embedded systems. The USART is a very flexible serial interface that supports asynchronous UART communication, SPI or Serial Peripheral Interface Master Mode, and LIN or Local Interconnect Network Mode. It can also interface with ISO, IEC 7816 Smart Cards, and IRDA devices. It also provides certain features that are useful when implementing Modbus communications. Applications making use of the USART benefit from the easy and inexpensive communication between devices, which only requires a few pins. In addition, the USART peripheral is functional in low power modes. It comes with transmit and receive FIFOs with capability to transmit and receive in stop modes. The USART is a fully programmable serial interface featuring the following configurable parameters, data length, parity, number of stop bits, data order, baud rate generator, and a configurable oversampling mode by 8 or by 16. The USART can operate in FIFO mode, and it comes with transmit and receive FIFOs. You also have the option to use basic RS-232 flow control with CTS or clear to send and RTS or request to send signals. The RS-485DE, or driver-enabled signal, is also supported. The USART supports a dual clock domain allowing wake up from stop mode and baud rate programming independent of the peripheral clock or PCLK. This also allows the peripheral clock to be throttled along with the core clock without disrupting communications. The USART features a multi-processor mode which allows the USART to remain idle when it is not addressed. In addition to full duplex communication, single wire half-duplex mode is also supported. The USART also offers many other features including auto baud rate detection, receiver timeout, and supports several modes which will be described later in the presentation. This is the USART block diagram. The USART clock source, USART KERCK, can be selected from several sources. The peripheral clock, or APB clock, the PLL2Q, the PLL3Q, the high-speed internal RC oscillator, or the low-power internal oscillator CSI, or the low-power external 32.768 kilohertz crystal oscillator. The USART clock source can be divided by a programmable factor in the USART-PRISC register. TX and RX pins are used for data transmission and reception. NCTS and NRTS pins are used for RS-232 hardware flow control. The driver-enabled pin, or DE, which is available on the same I.O. as NRTS, is used in RS-485 mode. The clock output, or SK, is dual-purpose. When the USART is used in synchronous master slave mode, the clock provided to the slave device is output input on the CK pin. When the USART is used in smart card mode, the clock provided to the card is output on the CK pin. The USART has a flexible clocking scheme. Its clock source can be selected in the RCC, and can be either the peripheral clock, or APB clock, the PLL2Q, the PLL3Q, the HSI, or CSI, or the LSE clock. The USART clock source can be divided by a programmable factor in the USART-PRISC register. The registers are accessed through the APB bus, and the kernel is clocked with USART-KERCK, pre-scaled or not, which is independent from the APB clock. The USART receiver implements different user-configurable over-sampling techniques for data recovery by discriminating between valid incoming data and noise. This allows a trade-off between the maximum communication speed and noise clock inaccuracy immunity. Select over-sampling by 8 to achieve higher speed, up to USART-KERCK-PRES-8, where USART-KERCK-PRES is the USART clock source frequency. In this case, the maximum receiver tolerance to clock deviations is reduced. Select over-sampling by 16 over 8 equals 0 to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to USART-KERCK-PRES-16. The maximum BOD rate that can be reached is 12.5 megabod when the clock source is at 100 MHz and over-sampling by 8 is configured. With other clock sources and or higher over-sampling ratio, the maximum speed is limited. The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. The USART supports 7, 8, or 9-bit data lengths. A frame starts with one bit, where the line is driven low for one bit period. This signals the start of a frame and is used for synchronization. The start bit is followed by 7, 8, or 9 data bits. If parity control is enabled, the parity bit is transmitted as the last data bit and is included in the data length count. Finally, a number of stop bits, 0, 1, 1.5, or 2, where the line is driven high, end the frame. The standard frame was described in the previous slide. This slide shows an example of 8-bit data frames configured with one stop bit. An idle character is interpreted as an entire frame of ones. The number of ones will include the number of stop bits. A break character is interpreted on receiving zeros for a frame period. At the end of the break frame, two stop bits are inserted. The USART supports full duplex communication, where TX and RX lines are respectively connected with the other interfaces, RX and TX lines. The USART can be configured to follow a single wire half-duplex protocol, where the TX and RX lines are internally connected. In this communication mode, only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus, it acts as a standard I.O. in idle or reception modes. This means that the I.O. must be configured, so that the TX pin is configured as an alternate function open drain with an external pull-up. In RS232 communication, it is possible to control the serial data flow between two devices by using the NCTS input and NRTS output. These two lines allow the receiver and transmitter to alert each other of their state. The following figure shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half-duplex communication. Both signals are active low. For serial half-duplex communication protocols like RS485, the master needs to generate a direction signal to control the transceiver or physical layer. This signal informs the physical layer if it must act in send or TX or receive or RX mode. In RS485 mode, a control line is used. The driver-enabled pin is used to activate the external transceiver control. DE shares the pin with NRTS. To simplify communication between multiple processors, the use art supports a multi-processor mode. In multi-processor communication, it is desirable that only the intended message recipient should actively receive the message. The devices not being addressed are put into mute mode. The use art can enter or exit from mute mode using one of two methods, idle line detection and address mark detection. The use art can also communicate synchronously. It can operate as an SPI in master or slave mode with programmable clock polarity or CPOL and phase or CPHA, and programmable data order with MSB or LSB first. The clock is output in case of master mode or input in case of slave mode on the CK pin. No clock pulses are provided during the start and stop bits. When the use art is configured in SPI slave mode, it supports the transmit under-run error and the NSS hardware or software management. The use art can be used in smart card mode based on a half-duplex communication. The clock is output to the smart card on the CK pin. It supports the T equals zero protocol and provides many features allowing support for T equals one. Both direct and inverse conventions are supported directly by hardware. The use art supports IRDA specifications, which is a half-duplex communication protocol. The data from and to the use art is represented in an NRZ or non-return to zero format, where the signal value is at the same level through the entire bit period. For IRDA, the required format is RZI, return to zero inverted, where a one is signaled by holding the line low and a zero is signaled by a short high pulse. The SIR transmit encoder modulates the non-return to zero or NRZ transmit bit stream output from the use art. The SIR receive decoder demodulates the return to zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the use art. The use art only supports bit rates up to 115.2 kilobits per second for the SIR end deck. In normal mode, the transmitted pulse width is specified as three sixteenths of a bit period. The use art receiver is able to detect and automatically configure the BOD rate based on the reception of any one of the following characters. The received character can be any character starting with a bit at one. In this case, the use art measures the duration of the start bit from falling edge to rising edge. Any character starting with a 10XX pattern. In this case, the use art measures the duration of the start and of the first data bit. The duration is measured from falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes. 0X7F character frame. In this case, the BOD rate is updated first at the end of the start bit, then at the end of bit six. Or a 0X55 character frame. In this case, the BOD rate is updated first at the end of the start bit, then at the end of bit zero, and finally at the end of bit six. In parallel, another check is performed for each intermediate transition of the RX line. The use art supports a receiver timeout feature. When the use art doesn't receive new data for a programmed amount of time, a receiver timeout event is signaled and an interrupt is generated if enabled. The use art receiver timeout counter starts counting from the end of the first stop bit in case of one and 1.5 stop bit configuration. From the end of the second stop bit in the case of two stop bit configuration. And from the beginning of the stop bit in case of 0.5 stop bit configuration. The use art can operate in FIFO mode, which is enabled or disabled by software. It is disabled by default. The use art comes with a transmit FIFO or TX FIFO and a receive FIFO or RX FIFO, each being 16 words deep. When the IRDA and LIN modes are used, the FIFO mode is not supported. Provided that the TX FIFO and RX FIFO are clocked by the kernel clock, it is possible to transmit and receive data even in stop mode. It is possible to configure TX FIFO and RX FIFO thresholds, mainly to avoid underrun overrun issues while waking up from stop mode. The use art is able to wake up the MCU from stop mode when the use art clock source is the HSI, LSE or CSI clock. The sources of wake up can be a specific wake up event which is triggered by either a start bit or an address match or any received data. An RX NE interrupt when FIFO management is disabled or FIFO event interrupts when FIFO management is enabled. Receive FIFO full interrupt, transmit FIFO empty interrupt, receive FIFO threshold interrupt, or transmit FIFO threshold interrupt. Several errors can be generated. The overrun error flag is set when an overrun error occurs. The parity error flag is set when a parity error occurs. The framing error flag is set when a framing error occurs. The noise error flag is set when a noise is detected on the received frame. The auto-baud rate error flag is set when the baud rate measurement failed. The end of block flag is set when a complete block is received. The wake up from stop mode flag is set when the wake up event is verified. The lin break flag is set when a lin break frame is detected. The transmit FIFO not full flag is set when the transmit FIFO is not full. The transmit FIFO empty flag is set when the transmit FIFO is empty. The transmit FIFO threshold flag is set when programmed threshold is reached. The receive FIFO not empty flag is set when the receive FIFO is not empty. The receive FIFO full flag is set when the receive FIFO is full. The receive FIFO threshold flag is set when the programmed threshold is reached. The DMA requests can be generated when receive buffer not empty or transmit buffer empty flags are set when FIFO management is disabled. The DMA requests can also be generated when the transmit FIFO not full and receive FIFO not empty flags are set when FIFO management is enabled. Several errors can be generated. The overrun error flag is set when an overrun error occurs. The parity error flag is set when a parity error occurs. The framing error flag is set when a framing error occurs. The noise error flag is set when a noise is detected on the received frame. The auto-baud rate error flag is set when the baud rate measurement failed. The underrun error flag is set when an underrun error occurs in synchronous slave mode. The USART peripheral is active in run mode. The USART interrupts cause the device to exit sleep mode. The USART is able to wake up the MCU from stop mode when the USART clock is set to HSI, LSE, or CSI. In standby mode, the peripheral is in power down and it must be re-initialized after exiting standby or shutdown mode. The STM 3287 devices embed eight USART instances. USART 1, 2, 3, and 6 have a full set of features. Instances 4, 5, 7, and 8 do not support synchronous and smart card modes. This is a list of peripherals related to the USART. Please refer to these trainings for more information if needed. General Purpose Input Outputs Reset and Clock Controller Power Controller Interrupts Controller and Direct Memory Access Controller