 Welcome to the lecture series on advanced VLSI design course. In my previous lecture I discussed about the various issues in VLSI test, why VLSI test is important, what are the cost implications and we have analyzed that what is the typical cost it incurs in terms of a money when you test a chip on an expensive tester and we figured out that it is typically somewhere from 2 to 5 cents per second and so that means here if you test your device for about a minute then it may come to say 3 dollars that is roughly 150 rupees. So that means here the reasonable time that we can use to test a device could be somewhere from few seconds to minutes. And we have also seen that in order to apply all possible test vectors it may take billions of centuries which is impractical so our task is to bring down this time from billions of centuries to few seconds to few minutes to make it cost effective and practical. So as we discussed in last lecture that the typical test process starts in the following manner you have a device or circuit under test, you have automatic test equipment, you apply test stimuli from automatic test equipment to the circuit under test, collect the response from circuit under test and then compare with the golden response that you have stored on your tester and now here if this matches with the collected response then device is good otherwise device is bad and hence we have to reject. So only we have to ship out good devices. In last lecture we also discussed that what are the various requirements, what kind of fault coverage we are looking at. So and we discussed that it is governed by the defective parts per million parts we are looking at and so therefore it varies from application to application like in automotive application this defective parts per million that we commonly called as DPPM is somewhere like or it should be very close to 0 though here we cannot achieve 0 so it should be close enough to 0. Now so what we demand from the test that we have a device under test we apply some stimuli we collect the response. So now here a response of a good circuit would be given by this function when you apply input at x1, x2 and xn. So this is your fault free function and that you designed. In case there is a fault here function evaluates to f alpha or in case of defective function evaluates to f alpha. And now here what we want that here we want to find out a stimuli that can give me two different kind of behavior of f and f alpha. So that these are distinguishable and we can say that my device is good or bad. So that means here the task is to find out a stimuli that can distinguish faulty and fault free behavior. And that stimuli is called as test for a fault or or or defect. So but here you keep in mind always that whenever we refer a test until unless it is said explicitly it is the detection. So that means here we are interested in detection whether chip is fault free or chip is faulty not in diagnosing or locating the fault. That means here what kind of fault it is and where exactly it is in the chip. So diagnostic test we will talk in separate lecture later. So now here if you come to look at say 3 input NAND gate. Now here this is the truth table of a 3 input NAND gate. And so now here if you apply say all 3 0s output should be 1 and then here this way it sorry this is the 3 I mean say a function truth table of a 3 input function. So now here what we want that here in order to test it we have to apply all possible 8 combinations. But as we have seen in the last lecture that we cannot apply all exhaustive test set and hence then we have to find out or we have to select a few test vectors that can target the kind of faults or defects we are looking at. So when we cannot apply the exhaustive test set then our best bet is to target likely faults. So now here we define couple of definitions faults and error. So actually we are looking at the defects and defect is defined as physical flaw in the device in other words like here sorted transistor or an open intravenant. This defect has logic level manifestation that means here and that is defined as fault that means here a line may be like permanently stuck or connect to logic level 0 or it can connect to logic level 1. Now the so when it manifest as in logic level so that means here it causes an incorrect logical output value of the function so that means here there is a defect, defect manifests itself as a fault and then fault manifests itself as a incorrect output or incorrect evaluation of the logical function. So now here we so now the question is as we know that there are numerous defects those are possible and we cannot target all the defects. So now the and these defects they depend on the circuit layout and process control and difficult to obtain all possible defects some of the defects may not be known from the newer technology. So now we have to simplify the problem by targeting only the logical faults and logical faults are the manifestation of these defects. So you have a physical defect and then you that manifests itself as a fault you model those fault and that appears as a logical fault. So now here we model these logical faults and hence we work around those. So one of the simplest model could be we can assume that a defect can cause signal line either it connect to permanently to logic high or permanently to logic low. So this is the implication of the defect and hence we can model that as a stuck at zero fault or stuck at one fault that that we express as as a zero as a one. So now here we there are two questions first thing is how good this model itself is. So that means how close it is to model the real defects and then here what does it buy us we have to evaluate based on that. So now here if you look at the say a four input NAND gate this four input NAND gate can have four inputs so four input lines and one output line. So now if we say that defect may manifest in such a way that any line can either permanently connect to logic zero permanently connect to logic one. So hence there are five lines they can either connect to logic zero or can connect to logic one hence we may have ten different faults those we represent as a zero that means here line a stuck to logic zero a one that means here line a stuck to logic one b zero means line b stuck to logic zero b one means b line b stuck to logic one. Now here if you look at the if I apply say all once as input. So here if I apply all once as input in that case here what we expect from this gate if there is no fault in that case here output should evaluate to zero. So now if a stuck to logic one zero then what will happen the output y will be one. Hence I can produce the distinguishable fault free and then faulty behavior. Hence this vector all once can detect this particular fault a zero look at b if b stuck to logic zero in that case again here the out it will produce output as one when I apply one one one one as input and now here again we are getting for distinguishable faulty and fault free behavior. Hence this fault is also detected by this one in the same way c stuck to zero d stuck to zero can also be detected look at the output if output is if I apply one one one one here then my fault free b output should be zero. Now if the output y is defective and it stuck to logic one then the once I apply here one one one one output would be one. Hence I will have distinguishable for fault free and faulty behavior. So this particular vector can detect fault a stuck to zero b stuck to zero c stuck to zero d stuck to zero and y stuck to one. In the same way if I apply a vector zero one one one the output of this gate would be one if this a stuck to logic one in that case here because this line is permanently stuck to logic one so that means it does not have any effect of what I apply at a primary input a and b c d are already one one so now here output would be zero. So I have distinguishable faulty and fault free behavior hence the a stuck at one is detectable. Now look here at the output output a so if I apply this zero one one one output is one if y stuck to logic zero always it will produce output zero right so that means here this gives me the faulty and distinguishable faulty and fault free behavior hence this can also detect y the stuck at zero fault at line y. So now here if I look at this so in the same way a vector one zero one one can detect stuck at one to at b and stuck at zero at y. So now here if I look at these four vectors so these five vectors they can cover all these eight or ten fours right. So now here if I look at this number ideally if you remember if I want to test it exhaustively I may need sixteen inputs to test this gate. Now if you look at this number five is the total number of lines you have so that means here the total number of inputs plus one. So now here what it gives you what it buys out to you is that here now you can convert your exponential complexity into a linear complexity so that means here you need test vector which are linearly proportional to the number of inputs you have. So this is for one gate if you look at a complete circuit things are pretty much like this not exactly n plus one this may this would be n plus one for single output circuit single output fan out free circuit. If it has fan out in that case here this number will be slightly more that means here you have to add the number of fan out points. So that means here if you can model your defect using a stick at fault you can convert the test complexity from exponential to the linear and that gives us big relief. So that means even if you have millions of gates you may have millions of faults that means you may need millions of vectors to test it and millions of vectors may be applied in reasonable time. So and that is why we look at we model the defects as a faults which are the implication of these defects. So now what the means these fault model is what this can model if you look at this circuit which is a TTL logic and the stick at fault model was given way back in early means late 50s or in 60s and at that time here technology was bipolar technology and this worked very well for bipolar transistors as well as n MOS. This is still it is relevant for CMOS technology except few additional faults that may occur in CMOS. So now here how I justify that say there may be a defect so that means here if this transistor source that is the defect but the implication of that defect would be like here this output C would be always give you the logic 0 hence we can say that the implication of the defect that this transistor is short is stuck at zero fault at logic at output C. In the same way if this point is open in that case here that the implication of that would be so this transistor would not conduct and then here you will get high potential and high potential means here the C is stuck at zero. So now here defect is here this is open but here output is stuck to one in the same way if you look at the MOS logic if this transistor source in that implication of that is like here A is stuck to logic 0 if this transistor is open in that case here due to this open always this is in the pull up mode and then C acts as always is stuck to logic 1. So now here the defect is this transistor is open but here this implicate in terms of in the form of stuck at one fault at output C. So this tells you that a defect multiple defect can have the same implication so that means here multiple defects can be modelled as a single fault so that means here there is no uniqueness relationship between defect and fault and this model worked very well for bipolar and for N MOS but here and it works reasonably well for CMOS except a few more faults that we have to target separately. So now here if I can model a fault like this then I do not need to look at what kind of defects can occur in the in the during the manufacturing I need to test only for the modelled fault and modelled faults are proportional to the number of lines we have or number of signal lines we have like for example in this circuit we have total 12 lines so like here a b d e g h i j k and z. So these are 12 different lines and any line can either stuck to logic 0 or can stuck to logic 1 hence there can be 2 faults. So now here at 12 different fault sides there can be 24 total faults total single stuck at fault. Single stuck at fault means here we assume that at a time there can be only 1 fault there cannot be multiple faults that is our assumption. So by from this we infer that here now the number of faults are proportional to the number of number of a signal lines we have keep in mind that fault at the stem of a fan out branch and at the fan out branches are different because they have different implications. So you have to treat them different fault sides. So if you look at this like here for example in this AND gate there are 2 inputs and 1 output this is the truth table and now if you look at the truth table if you have both input 0 0 output is 0 then here if you have both input as 1 1 output would be 1. Now look at how it evaluates when a stuck to logic 0 b stuck to logic 0 z stuck to logic 0 a stuck to logic 1 b stuck to logic 1 and z stuck to logic 1 these are the responses under these conditions. Now look at faulty and fault free behavior. So fault free behavior here is 0 and for all these fault free means faulty behavior is also 0 that means this is not distinguishable so that means this input cannot distinguish cannot detect these faults only this can detect this fault where we have the different fault free and faulty behavior. This vector can detect these 2 faults whereas this vector can detect these 2 faults this vector can detect all these 3 faults so that means here 1 vector can detect multiple faults like here this vector can detect 2 faults this vector can detect 3 faults or 1 fault can be detected by multiple multiple vectors. So now here the question is that how many test vectors I need to detect all the faults so that means we have to choose a smallest set of test vectors that can detect all modelled fault keep in mind modelled fault. So from this one we have to choose a smallest set that can detect all possible faults like we show in earlier example that for a 4 input NAND gate we need 5 test vectors. So now you have modelled a fault and you have a relationship between the fault and test vectors and the objective is to find out a smallest set of vectors that can detect all possible modelled fault here in this case all 6 faults. So this is one of the fault model which is called as single stuck at fault. Now there are there are other fault models in this single stuck at fault we are assuming that there can be 1 fault at a time in the circuit that may not be very reasonable assumption but people figured out by experiments that if you detect all single stuck at fault large number of multiple stuck at faults are can also be detected and because of the nature of multiple stuck at fault we cannot target all the possible multiple stuck at fault and number of possible multiple stuck at faults are 2 raise to the power 3 raise to the power N minus 1 that is this 3 raise to the power N minus 1. And now here N is the number of fault sites single stuck at fault sites you have or number of signal lines you have hence now this is exponential again here we are going from linear complexity problem to exponential the this is not possible. So now the experimental study says that if you detect almost all single stuck at fault you are likely to detect 80 85 percent multiple stuck at fault that may be good enough. There are other faults like here a transistor can be open or that can be be short and these are are detected by by some different methodologies that may we may may discuss some sometimes later. Then other a kind of circuit we have is memory memory is very special type of circuit and it has a special functionality or is special function to perform that is it stores a value that can that is logic 0 or 1 and it retain that until it is changed. So that that means here you have a complex or dense array of memory cells they are storing some in information and they retain that until you write it back. So now now because of the limited functionality in place of modeling every a fault at every signal line as a stuck at 0 or stuck at 1 we go for functional fault model and that functional fault model needs to check whether all the cells are able to detect able to store value 0 able to store value 1 able to make transition from 0 to 1 or 1 to 0 and the memory address decoder works fine that means here address decoder should address to single cell and proper cell which you want to address. These are the various different fault models for PLA kind of a programmable logic array kind of circuits here we may have some more faults like stuck at fault is already there may be a cross point or there can be a bridging the other a kind of circuits that we have in practice are like microprocessor microcontroller or that kind of devices which again here is supposed to perform some kind of operation which is very limited in nature like here a microprocessor executes couple of instructions in some specific way. So it is not very random and hence here we can make use of functional fault model. Then as we discussed earlier there are some faults which may or may not be there during the manufacturing time they may implicate while it is operating or your system may not have any kind of logical fault but it may not meet your timing requirement and those are performance related faults and those are modelled as delay faults. Then the analog circuit or mix signal circuits we have and for mix signal or analog circuit we do not have a specific fault model generally we do specification based testing. So they have different kind of fault again here the modelling of faults in an analog circuit is open challenge. So now here we discussed what kind how we can model a fault and how close that is to your defect implication and what it buys us. What it buys us is it can convert the exponential problem into a linear problem so that means here now I do not need to apply to raise to the power n pattern I may need to apply only n plus 1 pattern which is linear and that is a great relief. So now the question is how I generate those test patterns that is very important problem as we discussed earlier that now here say this pattern 111 this can detect stuck at 0 here, stuck at 0 at B, stuck at 0 at C, stuck at 0 at D and stuck at 1 at Y. Now from this I apply this one and I see what is my fault T and fault free behaviour if I do that simulation so that means here one entry value simulation and then here simulation for each and every fault and see where we have distinguishable fault T and fault free behaviour and then based on that we say that this vector can detect these faults. Now if I ask question other way round how if I know that they may be a stuck at 0 fault here what is the test vector which can detect this is stuck at 0 fault. So that means we have to device a mechanism to find out these test vectors which target one particular fault. There are various ways and one of the way is at algebraic method algebraic method is based on Boolean algebra. So if you have function f that has n inputs x 1 to x n and now here the function evaluates to f of x 1 to x n and the it evaluates based on the value of x 1 to x n. I can decompose the this function in two functions here using the Shannon's expansion theorem say with respect to each and every variable. So with respect to x 1 I can decompose as x 1 dot f of if I replace x 1 by 1 then x 2 sorry this is x 2 x 2 to x n and plus x 1 bar f of 0 x 2 to x n sorry this is x 2. So this to get x 1 plus x 2 to x n this is gives you the two different factors these are defined as co-factors. So that means this function evaluates to this function if x 1 is 1 this function evaluates to this function if x 1 is 0. So that means here if I want to detect a fault at x 1 what I want that the behavior that I can obtain by having two values at x 1 0 and 1 should be distinguishable otherwise I cannot detect that fault. So that means here this function and this function should be orthogonal to each other. So that means here this the x 4 operation of this function and x 4 operation of this function must be different. So that means x 4 operation must be must evaluate to 1 and that is defined as Boolean difference. So that means Boolean difference with respect to a given variable where your fault site lies should evaluate to 1. So if you do not have fault it evaluates to some value if your fault in that case here it should evaluate to different value. Now then what should be the test vector? So we know that this x i if fault is at x i and your Boolean difference with respect to x i is del f upon del x i. So assume that fault is stuck at 0. If it is stuck at 0 in that case here that fault should be excited. Excited means here you have to have distinguishable means the different value should be applied at that fault site. So that means this x i must be equal to 1 and this Boolean difference must also evaluate to 1. This says x i dot del f upon del x i this should evaluate to 1. This gives you the test vector for stuck at 0 fault at x i at x i. If fault is stuck at 1 at x i then because here if you apply 1 in that case here you are not going to change anything. So you have to have opposite value. So that means here x i must be 0 and that fault effect should be propagated to the output. So that means here del f upon del x i this should evaluate to 1. That means here this is x i bar dot del f upon del x i this should evaluate to 1. This gives you the test vector for stuck at 1 fault at x i. Now let us take a small example. So these are the two conditions. Take an example here. This function I can write as x 1, x 2 plus x 3. Assume that there may be a stuck at 0 and stuck at 1 fault at x 2. That means I have to find out whether the Boolean difference of this is 1 or not. If a Boolean difference is not 1 that means x 2 has no role to play in making a decision or in evaluation of this function. That means x 2 is a redundant input here. Now look at and how I can obtain this Boolean difference. If I put x 2 equal to 1 then it will evaluate to x 1 plus x 3. If I put x 2 equal to 0 in that case here it will evaluate to x 3. So now here Boolean difference would be x 3 x 4 with x 1 plus x 3 that is x 3 bar x 1 that should be 1. So what it research into? Always this Boolean difference must be 1 that means here x 1 should be 1 and x 3 should be 0 if you want to detect this fault. Now here if you want to detect stuck at 0 fault that means x 2 must be 1. So you have to have just opposite value and if you want to detect a stuck at 1 then here x 2 must be 0. So now the test vector for stuck at 1 would be 1 0 0 and test vector for stuck at 0 would be 1 1 0. This way I can mathematically or using Boolean algebra can generate test vector for a given fault. So now here I know that this circuit has 1, 2, 3, 4 and 5 fault side that can be 10 different faults and I can detect a test for individual fault using this Boolean algebra. But manipulation of Boolean expressions for a fairly simple big circuit or large circuit is not so easy. So then we need to find out a way, a method which is scalable for large enough circuit and then the way is algorithmic way rather than algebraic way. So and there are couple of algorithmic methods presented in the literature like first came in 1968 that is known as D algorithm which was given by Roth from IBM then in 81 another algorithm came that is known as Podem which was again given by Goel from IBM then in 1984 the another better algorithm came which was given by Fujiwara and then there are couple of other algorithms. One of the popular algorithm was Socrates which uses the learning process then spirit again this was from Fujiwara and his group. So all these algorithmic methods are based on three principles or three steps. One is the fault sensitization, fault propagation and line justification. Fault sensitization mean here you have to sensitize the fault that means if you are looking at say this is your AND gate and your fault is here. So say this is stuck at zero fault. How I can sensitize this? If I apply here zero can I sensitize this fault? I cannot because this circuit can never produce different value under the faulty and fault free condition. So hence this is this cannot be. So now here sensitization condition is that you have to have just opposite value to the fault. So now here you have to have one. So this is the fault sensitization. Now can I observe the fault effect here? I cannot observe fault effect here. So now you have to propagate this fault effect to one of the observable point and observable point is the primary output. So you have to transfer the fault effect to the observable point. So here I have distinguishable fault effect. If it is faulty then here I have zero. If it is fault free in that case I will have one. The same thing I want to propagate to the output and in order to propagate that to the output here the another input to this gate must be at the known controlling value and known controlling value for the AND gate is one. So if I put it at one in that case here output would be determined by another input. So now here if I can have distinguishable faulty and fault free behavior at this input that would propagate to the output and I can look at the output. This is known as fault propagation and now here this is the case when this is the primary output. Say this is not primary output there is one more gate out after this. Now again I have to propagate this to the primary output. If I propagate this to the primary output here again I have to put it at the known controlling value and known controlling value is one. Assume this is also coming from another gate and now here what I want? So I cannot justify value one here. I can justify value at the primary input and these two are the primary input. So I can justify this value one by justification at the primary input and now here I justified all the values at the primary input. There are four primary inputs and I justified all those and those are in one line hence here this is known as line justification. So the third process is line justification. So these are the three important factors in this. So now here an algorithmic method to generate a test is based on path sensitization and path sensitization follow these three steps. Fault sensitization, fault propagation and line justification and as I said that here there means these are the couple of algorithms there are many more. So the general structure is you have to begin from a fault and justify that value at that location and then you have to propagate that faulty value or distinguishable faulty and fault free value to the one of the primary outputs and then you have to justify that. So if like here for example in this circuit say there is a fault at line D and that fault is assumed that it is stuck at one. So now here if it is stuck at zero so the fault at D is stuck at zero then here what I want in order to sensitize this fault I need to have value 1. So I have to justify value 1 here how I can justify that value 1 in order to justify I have to go back to the primary input. So what gives me 1 here I can obtain value 1 here only by assigning a equal to 1 and b equal to 1. So I assign the a equal to 1 and I assign just justify value b equal to 1 and because these 2 are the primary input it is doable. Now so this excite my fault now I have to propagate this fault effect to one of the primary outputs and it has only one primary output. So I have to propagate here in order to propagate here. So I have to propagate it here and now because this is inverting gate so now here the see I use a symbol D this symbol D is just notional thing say this D has distinguishable fault and fault free behavior. So now here I can propagate it to the output. Now in order to get it propagated here we know that here I need known controlling value here and known controlling value of no gate is zero hence I have to justify value zero here. I cannot justify value zero here or say put it other way I do not have any control here. So I have to go back to the primary input and see how I can justify that. So now in order to justify zero what I want both input must be must be 1. One input is already 1 if I assign another input as 1 in that case I can justify value zero here and hence I am done my fault effect will propagate to the output and I can get a test factor that is a 1 1 1. So this is the basic of all these algorithmic methods to generate a test. So if I look at what are the difficulties with this here there are as we know there are three steps fault activation or sensitization fault propagation and line justification. So now here what are the difficulties with the fault activation I have look at the previous approach here. If I previous figure here if I want to have one here I have to go back to all the way to the primary input and assign some value here. So this problem converts into line justification problem. So fault sensitization or fault activation problem is a line justification problem. What are the difficulties of line justification problem we will discuss will be later. Other step is you have to propagate fault effect to one of the primary output how you can propagate. So if it is fan out free circuit in that case here it is easy because here you can always target one output and like you have to follow a path. But in a circuit wherein you have several fan outs you can propagate fault effect to any of the output through any of these fan out points. So that means you have to make a decision that how through which path you have to propagate the fault effect to the one of the primary output. It is like you from say department to hostel you want to find out a way and that way is the easiest one. So you hit to a crossing and then you have to see which way I should go should I take left or should I take right. And now here if you are not familiar with that location sometimes your decision may be good and you reach to your hostel. If you are not familiar and your decision may be wrong. If it is wrong then here and you may end up in a forest. So what you do? You have to come back to the same point. So now here and then again explore the another path. So now this process can be a decision making process or so now there are two things. One is the propagation is a decision making process. Second thing is once you made a decision you have to have assign the known controlling value to the another primary input of that gate. So and that means at intermediate point you cannot justify. So you have to go back and justify at primary input. So now that problem again here converts to a line justification problem. Now look at the line justification problem. Now line justification problem can be either a decision making or that can be an implication. Say look at this gate output is a C and now you may need to assign say one here. If you need to assign one here in that case you have only one choice A equal to 1 and B equal to 1. That is just by implication that if you want C equal to 1 you have to have A equal to 1 and B equal to 1. That is simply implication and whereas the if you want to assign 0 here there are two ways. One is if you or rather I can say three ways that A can be 0 then it gives you C equal to 0 or B can be 0 then you will also get C equal to 0. If both are 0 in that case also C equal to 0. So now here and this is the decision making process because you have to assign either A equal to 0 or B equal to 0 and then this may so that this may be the decision and decision may be right or this may be wrong. If it is wrong in that case you have to come back to the previous decision making point and explore the another one. So this gives you the nutshell the difficulty of test generation process. You are making several decisions and these decisions are may or may not good and if they are not good in that case you have to back track to the previous decision making point and explore the another opportunities. So now here I briefly will discuss D algorithm that was given by Roth in 1968 1966. This was the first complete ATPG algorithm. So what does this mean that if test exist for any given fault it gives you the test vector otherwise it will say that there is no test for that particular vector and those faults are redundant faults those are coming from redundancy in the circuit. This is based on decalculation that uses the 5-valued algebra and because here we want to propagate a composite value that contains faulty and fault free output. So that is described by 5-5 symbols assume. So now you want to list the output as a composite value that is fault free and faulty. So now here fault free can be 0 then faulty can be 0, faulty can be 1 and faulty can be x if you are using 3 values 0, 1 and x. So now here fault free may be 1, fault free may be 0, 1 and x. So 1, 1, 1 and now here your fault free may be x and fault free may be 0, fault free may be x and faulty may be 0, faulty free may be x and this may be 1 and this is x and this is x. So now here you have both 0, 0 that is assigned with a symbol say 0 because this gives you the indistinguishable faulty and fault free behavior. Here also you are getting both 1, 1 in that case here assign a symbol 1. Here this gives you fault free value as 0, sorry 1 and fault free fault free value as 0. This is assigned with a symbol D. This is just opposite to this now here this is assigned with a symbol D bar and then the rest of the values wherein you have at least 1 x or assigned combined in 1 and make x. So these are the composite values it uses. Now here it heavily dependent on implication it tries to use implication as much as possible and implication as I said that here like if you want to have if you have 2 input of an AND gate as 1, 1 then output is always 1 and if one input is 1 and another. So that is the implication and for that implication it maintains an implication stack and then because at various points you are making a decision and if your decision is wrong. So you have to backtrack and for that backtrack here you have to again maintain a stack that can bring you back to the same previous decision point. So now here it tries to search the solution space. Now here like how the decision making process works like for example in this circuit here if I say there is a stack at 0, stack at 1 fold present here that means I can represent that by a composite value and that composite value and that composite value is your d bar where in the fold free value is 1 and fold free, fold free behavior is fold free 0 and fold free, fold free value is 1. So now here you will have d bar then first you have to excite it excitation means here you have to have value 0 here in order to have 0 you have to have all 3 value as 1. So that is line justification problem. Now at this point there are 2 fan outs you can propagate through either through this one or through this output. So but at the same time you have to imply. So now here this one can imply as 0 here. So again here let us say now you would like to propagate this through gate g5. Now if you want to propagate through g5 in that case you need to have value 1 here in order to have 1 what you want? You want both of the values as 0 but there is a conflict here because it has already assigned value 1. So that means you end up with the conflict and then come back to the previous decision point and your previous decision point was to transfer the fold effect through this path. Now you have to explore the alternate path and alternate path is through gate g4. If you look at the exploring through g4 in that case you want one value here and now here in order to have 1 here both of this input must be 0, 1 input is already 0 and now here this is justified hence you will get input x. Here d can be anything whether 0 or 1 then a should be 1, b should be 1, c should be 1 and e should be 0. This is the test vector for this particular fold and now if you look at the decision making process there was one decision point wherein you could have transferred the fold effect through either g5 or g6. You decided to go through g5, you failed then you return back to the same decision making point and now you explore through g6 and you succeed and that gives you test vector in the same way. So now here in order to look at whether my fold effect is present in the circuit or not we maintain a stack that is called as a d frontier and this d frontier will have both of these get g5 and g6, we explore one. So you take out one and then explore the another one. Now here this is another example of line justification say you have stuck at one fold here at line h and now here in order to excite this I need to have 0 value here and in order to propagate this you need to have e and f as 1, 1 this will propagate here and in order to propagate means through this gate you need to have 1 here and 1 here. Let us say you want to justify this one first by using the line justification in order to have 1 here you may have either 1 here or 1 here. So let us say you assign 1 here. So now in order to have 1 here you need to have both 1 here. Now that has implication so m would be 0 and then this n would be 0 and if m and n are 0 and this o is already 0 by this implication. So that means here this r would be 0 and hence your fold effect will be lost. So now that means your earlier decision was not good. So that means here like assigning 1 here was not good. So now come back to the previous point and now in place of this you assign 1 here. If you assign 1 here that you can easily justify by assigning 1 and 1 here and now you are done. So now in order to assign then now you are done here but you have to still justify this 1 here. In order to have 1 here say you want to have 1 here and in order to have 1 here you may want to have 0 here. If it is 0 then again you are done and so now here you have to maintain a list that is called as J frontier that which are the gates who has assigned output but unassigned in port. So this way you can generate test using the algorithm and so now you have to have you need to go through these 3 steps of fold sensitization, fold propagation and fold line justification. This algorithm gives you a test vector if it exists always. Hence it is a complete algorithm. Though in worst possible case it may explore the entire solution space hence this is NP complete problem but in the observation is that most of the time within the few back track you can generate the test hence here this problem is doable. Now we stop here we will carry it forward in the next lecture. Good day.