 Let's start with theory. In the picture you can see basic setup of the embedded system. There is external memory and STM32 device assembled on PCB and it is connected to PC programming tool through a stealing debugger. The question is how to transfer data from PC to memory. For that purpose we have external loader application. External loader is piece of code which configure STM32 device for transferring data from computer to external memory. Loader must have suffix stldr for programming tool STM32Q programmer and it should contain functions for initialization, read, write and erase operation. As mentioned loader application file must be added to programming tool. The programmer calls function in the following segments. Firstly it is needed to initialize STM32 device. Mainly Quad SPI interface to allowing communication with external memory. Then the programmer calls read and write operation which transfer data from PC to device or from device to PC. It depends on the user action. Now we will have a look to few slides about Quad SPI interface available on STM32 devices. Quad SPI interface use 6 pins in total for data lines. This is why the name is quad, one clock signal and one chip select. It allows us to extend memory space of our embedded system for example graphic data or additional code because it is possible to execute code directly from Quad SPI memory. Additionally amount of manufacturers is growing and external memories are used more often. More complete theory about Quad SPI is covered in application note AN4760. Advantages are better throughput compared to classical SPI. It makes sense since classical SPI use only one data line. If we compare Quad SPI and FMC memories, Quad SPI memories are cheaper with smaller packages because it does not require so many pins and it can reduce PCB area and developers effort as well. Here you can see typical usage of Quad SPI communication. First is instruction. In this phase a command 8-bit instruction is sent to the flash memory specifying the type of operation to be performed. This command is fully configurable. Address phase. In this phase the address is sent to the flash memory specifying the address of the data to be read or written. Alternate byte. This is an extra phase offering more flexibility. It is generally used for controlling the mode of operation. For instance one byte can be sent continuously to keep the Quad SPI device in the operating mode. The demicycle space is needed in some cases when operating at high clock frequencies. This phase allows to ensure enough turnout time for changing the data signal from output mode to input mode. Data phase. In this phase the data is sent or received from or to the Quad SPI memory. The data phase is fully configurable allowing to send, receive or both any numbers of bytes to or from the Quad SPI memory device. Quad SPI can operate in three modes. Indirect status pooling, flag and memory mode. Indirect mode is based on CPU register access mechanism which must be fully handled by user application since there is no an antonymous access to memory. Status pooling flag mode can read external memory status register and pool autonomously for end of operation. The example status register of memory contains write in progress bit. In status mode peripheral automatically wait for clearing this bit after write operation. Memory mode is only for reading operations. In this mode external memory seems like internal. So any HAB masters can read data antonymously and also execute code from external memory. That was almost all about Quad SPI theory.