 So, welcome to the third lecture of digital system design with PLDs and FPGAs. The last class we had a brief revision of the basic subjects. So, let us quickly run through those slides before today's lecture. So, let us move on, essentially we talked about the major constituents of the digital design. To start with we will look at the function and there are two parts. One is a combination logic, higher level blocks we said. All those blocks which you have studied in the basic course. Then we have the sequential elements like flip-flops, registers, memories and all that. This is constitute the function part which you have to learn thoroughly and we have looked at the minimization using some algorithms. Single output minimization like Karnoff maps, Koin-McLoosky, Espresso and for there are multiple output multi-level minimization which is based on this algorithm but then it involves many other steps. We had a brief look at it. Then we looked at differentiating between the gates and the functions. The gates are able to implement. Then we had basically it is bringing the de Morgan's theorem into our concept and we have seen that the NAND and NOR are universal gate and we have seen some example of AND OR is getting implemented using NAND-NAND gates. And also we have seen how advantages is to conceptually think like that then you will not waste gates if you bring this into concept while designing some simple logic circuits. And we have looked at the encoder, the decoder, the multiplexers, the tri-state gates and we have seen what is a tri-state gate and some care need to be taken when you are busing or multiplexing using the tri-state gate. You have to pull up or pull down. Then we have looked at the multiplexer and demultiplexer and real life that it may not be like a textbook picture. Then we have looked at the difference between latch and flip-flop. Latch is transparent, flip-flop is edge-triggered. We have looked at the timing that is the second important constituent of the design. And for combinational circuit what is the timing, it is a propagation delay and for sequential circuit flip-flop there is a propagation delay called TCO and at the input you have to meet some time called setup and hold time for the flip-flop to transfer the input to the output properly. Then we have looked at something called hazards where in unexpected outputs you will get glitches which I said there is static 0 hazard and static 1 hazard in a sequential circuit is not a problem because we latch the output after settling. But this is just a model in real life and there is an unbalance path delay at the input of an AND gate or an OR gate this glitches can happen. So one has to wait for it to settle before latching on to a flip-flop or a register. You can have dynamic hazard for a single change in the input there could be multiple glitches at the output instead of one pulses. Then you have electrical characteristics basically voltages and current we have seen output voltage, output currents, how it is the voltage is related to the current. Then we have seen the noise margin, the fan out how to calculate the fan out, the power dissipation for a switching power dissipation not the leakage power dissipation, expression for the power dissipation in a CMOS output stage. So that is where we have dissipation of the whole circuit. So we can attack at a lower level at the transistor level at the power dissipation at the circuit level we can reduce the power dissipation. The third level is that when you have a system complete embedded system say with the processor with lot of peripherals and all that and a particular circuit particular system may not use all the peripheral at the same time. So it is possible to power down the peripherals or the modules which are not working or you can freeze the clock of some registers or memory so that it reduces the power dissipation or you can reduce the clock frequency of the unused blocks so that the power can be brought down. It does not stop there maybe when you are designing the whole architecture you can take care that the architecture is designed such that the power dissipation in the system is reduced. So that can be handled at the architecture level ultimately one might think it stops here but does not stop there. When you choose the algorithm for some computation you can choose an algorithm which reduces the power dissipation. There could be like you have a multiplication there are different algorithms you can use for multiplication but there may be algorithms which reduces the power dissipation but it may be slow. But if our primary aim is to reduce the power dissipation then you can choose an algorithm which reduces the power dissipation. So the low power design can attack at all these fronts you know these transistor level circuit level, the system level, architecture level and at algorithmic level the power can be reduced. And this is a very major focus in the current VLSI design even in devices like FPGA one would like to have low power dissipation but this is not the focus of our course. So I will give a I mean I have given a taste of it and if you want low power to know about low power VLSI design you have to go and credit a course which talks about it or read a book in the low power design domain. So let us move on what is the next issue in design. So that is the high frequency design. You know that in high frequency the tracks or the lines or the wires within on a PCB or a chip can act like transmission lines. So there could be reflections so unless we take care maybe your logic is correct the timing is correct everything else is taken care but because of the high frequency the wires can act like transmission line if there is impedance matching problem there can be reflections which can corrupt the signals. So this has to be taken care in high frequency design. Similarly there can be crosstalk like when you have two wires running parallel for long distance then one signal in the wire can be coupled to the next signal. So you can imagine what can happen if the clock line is running close to the interrupt line of a processor then that is disaster. So this has to be taken care the crosstalk. Similarly there is in the noise analysis there are ground loops the ground currents say there is an analog component and there is a digital component in the chip the switching current of the ground can pass through the digital ground can pass through the analog that can create problem in the analog circuit. All these has to be taken care and that is done in the back end tool in the back end design there are special tools for it. And this is also an important area one need to know in VLSI. So let us move on to the next technology that is the device technology. So our course is about PLDs and FPGAs so it is let us have a look at what are the device technology available. One thing is the application specific integrated circuit or ASIC and this is normally supposed to be full custom. So that means it is designed from scratch you know almost everything is designed at the gate or flip flop level maybe they will use some library cell but most of it is designed from the scratch. The problem is that it has a very huge cost because one has to set up the EDA tools for design tools for it people have to work on it and the foundry has to set up and the chip has to be fabricated. So it has a huge non recurring engineering cost that means it is a one time cost is huge and that has to be amortized over the number of the chips produced. So if the chip is produced only 10,000 you cannot possibly make an ASIC and get money out of it because each chip will cost so high. So the ASICs are designed only where there is high volume like you have the desktop CPU or the mobile phone SOC chips and so on. And this also take a large turnaround time from the you know finalization of specification to the first chip it may take one year, one and half year, two years and so on. So this ASIC is a huge costly affair but once it is designed it can be made to work at very high frequency like you have three guards, processor chips that is because it is ASIC it is custom designed. Many times people do not have such luxury they do not have the number to justify such a cost then one can go for semi custom design that is a mask programmable or standard cell that means the foundry will give you some standard design and you make your system based on that standard design and the foundry has all the layout for those blocks. So it is quick when you send out the interconnection of the standard cell or the array of gates it is quickly interconnected at the foundry. So this works for the medium volume it has medium NRE cause medium turnaround time the field programmable gate arrays. So this is the device technology so the next I want to touch on the current state of the VLSI technology you must have learnt that the PMOS is slower than the NMOS because the whole mobility in PMOS is less than the electron mobility in NMOS. But you know that with the current technology like strain silicon the PMOS is getting faster strain silicon means the silicon lattice structure is strained by some deposit on top of silicon so the lattice structure you kind of stretches so that the electrons and the holes can pass faster. So the PMOS is getting faster and the current feature size is the technology wise is 22 nanometer and if you look at the indel core I3, core I5, core I7 is fabricated in this 22 nanometer and the next technology which is coming which people are working the manufacturers are working is 14 nanometer where the inverter delay is of the order of 5 to 7 picosecond. So you know how fast this technology is going to be. But now the present trend is not to make things faster you know that we are reaching the limit so one cannot expect this to go down considerably in the same scale as before. But people are using parallel multiple core for computation you know that the indel current chips as the quad core and you know 8 cores and things like that. The present trend is not on the row speed but to have multiple computational units parallely working whenever possible ok. So which is many a times possible because there are in a processor or even in a mobile phone there is multitasking. So it will be good if you can you know listen to the music on a cell phone at the same time you are going for a walk and you want to capture the picture. So if both can work parallely it is very good you know it is very bad you are listening to music then you click a picture if the music stops yes nothing catastrophic happens but the user experience might get interrupted. So I am not greatly talking about the social implication of the technology but the good things can happen with the multiple core parallel computing and things like that. So let us move on next is the design methodology we will have a look at it we have already touched upon it but then let us have a look at the design methodology of the VLSI and FPGA. So as I said there is something called front end design and which goes basically from specification to the gate and flip flop level circuit or the net list or we can say from algorithm we design an architecture and we go to the logic circuit in terms of the gates and the flip flops and this is many a times called logic synthesis this step of going from an architecture to the logic level circuit is called logic level synthesis. Then the moment you have it the circuit here that the front end design is over then we go for the back end design. In the back end design this gate and flip flop level net list is converted to the chip mask not in one step first the logic circuit is converted to the transistor level circuit and this is called physical synthesis that is the physical transistors are synthesized out of the logic circuit. And thereafter the each transistor and the interconnection is designed in detail in terms of the mask which is required for the fabrication. So that is the back end design as far as the VLSI integrated circuits are concerned but if you take the FPGA we do not go for this step the FPGA has already the logic circuit built in as logic resources with the wires laid out with switches in between. So you literally you know go in one step from the logic circuit to the configuring the FPGA. So for FPGA this physical synthesis and chip mask is not there we directly go from this circuit level to the configuration of the FPGA directly with of course there is a step involved in translating this circuit mapping it to the resources of FPGA interconnecting it and so on. So that is the back end design for FPGA so we talked about the front end design and the back end design. So let us continue as I said in a digital design there is a data path where the computation happens it is made of registers and combinational circuit registers holding the value combinational circuit computing it. And there are controllers or finite state machine which control the data movement in the data path there could be multiple controllers or a single controller depending on the need and in VLSI design we have metric or we have constraints these are the constraints the area normally one would like to have a smaller area. So that the chip is smaller you can make more chips and reduce the cost and when the chip is small it will be compact and the delay will be less the wire delays will be less and the power dissipation will be less. So these are conflicting requirement it is not that you can have small area small delay and small power. So where one go for small area some block you may get a larger delay and when you go for a very fast circuit you may end up with a large area and large power dissipation and if you have looked at even very simple example like an adder say you have studied ripple adder you know that suppose we have an 8 bit ripple adder it use 8 full adders cascaded. So the area is very less you know what is in a full adder full adder use 2 exclusive or gate and 3 AND gates and an OR gate ok at the maximum. So such 8 stages but it is you know that it repulse through 8 stages in the worst case one state delay is say 1 nanosecond the worst case delay of addition will be 8 nanosecond. But you can go for a carry look at adder which has only 2 step delay so you anything you add you will get in 2 steps may be 2 nanosecond. But you know that when you go to as you go from the 0th bit to the 7th bit the whole circuit gets exponentially larger and larger and it occupies lot of area the carry look at adder is not very seriously used because of this problem it occupies huge area. So just an example saying that these are conflicting requirements you do not get everything low it is very difficult you have to make a trade off between the area and delay. So let us move on so the next thing I want to talk is this thing called system on chip which is or SOC and many a times you have a word called intellectual property or IP. So you know that earlier may be 10 years back a system was designed in a on number of boards you have a box or you have a rack based system where are the multiple boards like earlier if you looked at the computers there are motherboards there are daughter boards. But now it is shrunk to a single motherboard everything is built on the board and if you look nowadays on to the motherboard there are very few chips you have a processor chip and a peripheral chip which is also getting kind of integrated into a single chip. So the complete system of the desktop CPU can go as a single chip may be the DRAMs DDR3 memories will be outside but things are shrinking. So the complete system will be on a chip it will reduce the power dissipation it will reduce the area the cost will be reduced the delays will be less and the power dissipation will be less. And same thing is happening in the FPGA domain also in the ASIC domain you have system on board in the FPGA domain you have programmable system on chip ok. That means you have in FPGA domain also you have lot of processors peripherals are built into FPGA and you design your custom design on the FPGA put it together for a system which is called programmable system on chip and some manufacturers called system on programmable chip and so on ok. So if you take a system on chip it has lot of things typical you know I am taking an example it may have one or more processor cores. So it will have a communication maybe there is a processor for basic communication there is a processor for control there is some DSP for computation there could be multiple cores of DSP or control processors and so on. There are lot of peripheral devices like memory controller, UR, USP, the timer and so on IOS and so on. There will be one on chip bus architecture because lot of peripherals need to be interconnected. So there will be some kind of bus architecture on the chip like if you have an ARM you have an AXI bus in an ARM based system maybe like in a PC you have the PC chips of the local bus within for connecting the memories and you have network interfaces maybe you have Ethernet interface or a Wi-Fi interface and Bluetooth interface and so on. Then there could be custom hardware for packet processing, signal processing like Kodak you know you have a TV setup box which has an H.264 or Mbeck for decoder that is required and ultimately you have the software, the real time OS or the OS, the network protocols stack, application software everything in a flash memory in the chip within the chip. So that is an SOC so do not get you know if you do not know what is system on chip typical system on chip is like this and let us move on to the next key word which is many a times called intellectual property which is related to smart related to system on chip because when you have a complete embedded system it is very difficult to design from the scratch and you know that the way the short time duration in which the cell phones are coming into the market with newer and newer chips and it is very difficult to design a complete system in 6 months. So most manufacturers when they design a system on chip they use already design components of CPUs, of peripherals, of Kodaks and so on and they buy it from somebody who have already designed it and just put it together for as they require. So that is called intellectual property these are this designs which is already done is called the intellectual property there are different type of soft you know intellectual property one is a soft IP, soft IP would mean suppose you have a suppose a memory controller win VHDL or verilog you can buy and use it, it is very flexible because you can change it depending on the license but then you have to synthesize it you have to do the front end design, back end design maybe it may not be depending on your tool and your the way you design it may not end up in an optimised design and it may not give the desired delays it can be slow. So soft IP is very flexible but it may not give the performance. The next is a firm IP which is nothing but a synthesized IP that means the logic circuit is synthesized. So it may be optimally synthesized with the minimal logic circuit. So it can work faster but the changes are difficult now because earlier it was a hardware description language you could easily change the design. Now you have to change in the synthesized design in terms of the gates and flip flops it is cumbersome it is a better option than soft IP in terms of performance but flexibility is less. The last category is a hard IP where this is literally not the synthesized circuit literally plays and routed IP. So you can directly place it in the silicon the mask is ready for that circuit. So you integrate this hard IP with the other hard IP at the back and to level. So the advantage with this hard IP is it is already tightly integrated very optimally placed and routed. So it can be very fast but you know that any change in this hard IP is very difficult because it is already kind of physical synthesis is over the transistors are over chip masks are ready to change it is quite tough. So these are the IPs but the present the design friend goes for the IP design and people make IPs and sell it to other people you know the ARM chip the ARM processor this is an IP this is not a chip mostly you buy from the manufacturers the ARM consortium give it to whoever wants it they license it and they ask for some royalty and people are very happy with it because there are lot of peripherals and the processor along with the peripherals can be integrated and there are lot of standard IPs available standard OS available for ARM processor. So let us move on this is the next technologies that is something called dynamic or run time reconfiguration which is very much talked about researched pretty much. So this can work in FPGA and as ASIC level and the basic idea is that a part of a device is reprogrammed to implement a different functionality that means take an example say you have a SOC which is used in a mobile phone and suppose you are working with a Bluetooth okay then that Bluetooth part of the hardware is programmed into the chip okay. Now suppose after some time instead of Bluetooth you are connected to the Wi-Fi okay the wireless network not the Bluetooth and you are not using the Bluetooth at the same time. Then what is done is that at the run time dynamically this Bluetooth part of the hardware is removed and the Wi-Fi part of the hardware is put. So you can save lot of area and reduce the power dissipation and the cost and things like that this can happen this is supported in FPGA but you can even do this cleverly in ASIC which saves area which allows reconfiguration maybe you can even think of a system level reconfiguration like you have a general purpose device maybe it can act as a cell phone after some time it can act as a general computing device like a tab or a pad like that. So it is quite advantageous here the important thing is that the reconfiguration time is important you should be able to reconfigure very fast suppose you turned off the Bluetooth and you switched on the Wi-Fi then if it takes some 10 second for the hardware reconfiguration then this may not you know satisfy the user. So the reconfiguration has to be faster and very important is the granularity is important what part of the circuit can be reprogrammed is very important suppose the manufacturers restrict saying that only half the part of the chip can be reconfigured and all of the half part has to be reconfigured and things like that. The granularity is important and the flexibility how flexibility is like we should be able to reprogram any part of the chip or any area of the chip flexibility. So this dynamic reconfiguration this granularity the reconfiguration time the flexibility is very important. So let us move on this is another area as embedded system is concerned like also when system on chip is considered at a top level you need something called system modeling when you start with the system on chip you are not sure what part should be in hardware and what part should be in software. So there many a times you know that the hardware design is done in HDL and software design is done in C or C++ and it is a very cumbersome thing to like once a partition is made the hardware designer start designing the hardware and the software designer start designing in software and half the way you realize some software part has to be moved to the hardware it is a very tough thing. So it will be good at a system level you can model and study the performance at the cost that means hardware you know that it is concurrent we can make it very fast but it is very less flexible and the cost is higher. But software is sequential it has a lower performance compared to the hardware but it is more flexible you want to change the software you can change it easily. So it will be good to have a system modeling language we can model it together in one language and you know work out on the cost performance paid off and freeze it then go for the you know the hardware design and software design after partitioning. So the languages like system C allow the system modeling and there is a system verilog language which is mainly used for the system verification. So that is all about the system modeling let us move on you have learned you know like suppose you have learned the VLSI design or FPGA design that in itself is not an end. Because if you know how to design a VLSI chip or an FPGA chip but it is of no use but you know that you have to design the chip in some area. So it is very important to know that where these chips are used in which domain it is used ok. So maximum the A6 or FPGAs are used in communication networks. So if you are an VLSI or a FPGA designer you should have some background in communication network. So let us turn to the communication network. So you have learned about the layering of the protocol stack say layer 0 is a physical layer, layer 1 is a data link layer, layer 1 is the physical layer, layer 2 is the data link layer, layer 3 is the network layer and so on. So if you will take the physical layer mostly it is analog and digital mix. If you take the data link layer or many a times it is called MAC layer or media access control layer. It is digital mostly and in the case of a computer it is in hardware but it is controlled by a network driver. The operating system will have a driver to control this data link layer. So whenever a new networking protocol comes like you know you have the Wi-Fi or you have the latest protocol stack then a lot of design has to happen in the data link layer to implement this in a chip. And similarly network layer there is a layer 3 where the packets are switched or routed and that is as far as the end systems are concerned it is done in software. But if you look at the routers and switches on the main network this will be done in hardware. So there is lot of hardware work within the communication network. So it is worthwhile for an VLSI or FPGA designer to learn about communication network, communication protocols because lot of communication network based chips are designed. Similarly lot of things are happening in the signal processing like multimedia, the video encoding, video decoding, H.264, Mbac4 and various other codecs need to be designed, filters need to be designed, lot of compression need to be done all this happen in the signal processing area. So for an VLSI or FPGA designer it is very important to have some basic background the algorithms of signal processing so that you can implement it. And ultimately computer architecture within the like designing a CPU that is a job of VLSI designer many a times it is prototyped in the FPGA then move on to ASIC domain. So your FPGA design can move ultimately to the ASIC design so the computer architecture. So three areas one is communication network or computer networks then signal processing computer architecture. So that you should learn the basics of it so that when you design for a particular domain this knowledge comes handy and you will be a good designer in the field. So better know this so that gives an overview of the field. So we started talking about the various issues like application areas, design methodology, device technology, then the system modeling, then the high frequency design, low power design and so on. Just to give a glimpse of the state of the art or the current technology to be aware before moving into the nitty gritty of the digital design. So we have some time left let us move on to the digital design. So let me put the slide so I call it advanced digital design. So in this advanced digital design we will you know conceptually develop from a lower level to the higher level. We will start with small system then build we will see how the bigger systems are built upon these basic building blocks and what are the standard basic building blocks to understand the structure, timing and so on okay. So let us move on the first thing let us take the synchronous sequential circuit okay. So that is the first thing so I assume as I said before I assume all the background that you have learned the combinational circuit, sequential circuit and now we are coming to the serious design sequential circuit and synchronous sequential circuit and we will learn three things essentially the structure of a synchronous sequential circuit. What is the architecture of it, how to design it say knowing the structure how to design it and do the timing analysis of the synchronous sequential circuit. So that is what is shown in the slide. So we will study the structure of a synchronous sequential circuit design of it and the timing analysis of it and you must have learned we will start with the basic very simple thing you have learned that is the synchronous counter. You must have learned in your undergraduate program something called a ripple counter okay. This is a very crude circuit which has less use so like you know you have a suppose in a ripple counter you have a the least significant bit the output of which will clog the next bit and so on okay. This is not timing wise not a very good circuit. So forget about the ripple counter let us take the synchronous counter. Synchronous counter is the simplest synchronous sequential circuit we can study and the structure is same for all the synchronous sequential circuit or at least we can build on the basic synchronous counter. So let us try to design a very simple counter. So let me ask you how to design a modulo 6 counter okay. So modulo 6 counter has 6 states or 6 count which start with 0 it is a binary counter it start with 0 then it counts 1, 2, 3, 4, 5 and then goes to 0 okay and then it look it continues it loops okay that is a modulo 6 counter. So how to design this counter okay. So let us go step by step so we use binary encoding so that means we will encode the 6 in flip-flops. So we need logarithm to the base 2 number of flip-flops which comes you know some 3 point some numbers. So 2 point some numbers so we have to use 3 flip-flops. So let me put 3 flip-flops okay. Now I am already abstracting in your basic course you would have already put 3 flip-flops separate and try to design. So the first thing to notice is that we cannot go you know to the complex system with you know separate flip-flops you know because if you try to design something 32 bit we cannot put 32 flip-flops and in a paper or anywhere and design and we are also not you know that we are also not going to detail gate level design we are going to use higher level blocks. So we do not need to know all the details which is done by the tool optimization is done by the tool so we go to a higher level. So I have put 3 flip-flops together and you can see there is clocks are tied together in a synchronous circuit all the clocks of the flip-flops are same. So you get a single clock is connected to all 3 flip-flops a reset is connected to all the asynchronous reset. Now there are 3 queues Q2 Q1 Q0 and 3 Ds D2 and D1 D0 okay. Now assume that at the power on we have power on this at the power on this has become 0 0 0 3 0s that means the value is 0 now when the clock comes we should get the 1 here okay. So that is the basic counter design so how to make it 1 okay. So we only have we have initially made the 0 and somehow we have to derive in the next clock we have to get the 1 and you know that when the clock comes whatever as far as the flip-flops or registers are concerned whatever is here is transferred to the queue. So it is worthwhile it is enough if you have 1 ready here so when the clock comes 1 comes here and in the next clock 2 should be ready here. So you get the idea you at the beginning you have 0 here but we want 1 at the input so it is enough if you put a combination circuit here here and feedback this the present count to the input of that circuit. So that then we design that circuit such that given 0 that will give 1 given 1 that will give 2 and so on okay. So what I am saying is that we will put a combination circuit before the flip-flops and the input of that is the output of the flip-flops and the output of that combination circuit goes to the input of the flip-flops okay. The basic idea is that we design this combination circuit such that given 0 it gives 1, given 1 it gives 2 and so on okay in this fashion. Then when the clock comes initially it was 0 in the next clock if the 1 comes here and that 1 gives 2 here, next clock 2 comes here and 2 comes here and so on okay. So you design this circuit then you get a counter which count you know sequentially 0, 1, 2, 3, 4, 5 and you must have learned again in the basic course something like you want a mode 6 counter you have a mode 8 counter then what you do is that which counts up to 8 but then you catch 6 here decode and reset it and then it becomes 0 and so on. But there is a problem if you reset it using an asynchronous reset for a brief duration it might go to the next state and so on okay like you wait for the 7 to come here then you reset it then 7 there is a glitch 7 at the output. So this is a very neat design it works perfectly but next question is so that is the structure of a synchronous counter you have flip-flops and many a times we call this as a present state of the flip-flop and it goes to a combination circuit and the output of the combination circuit is called next state because upon the clock the next state it become present that is why it is called next state and this combination circuit is often called next state logic because it is a logic it is a combination circuit which decode the next state from the present state. Now it is very easy to design we have to design basically we have to design this combination circuit and we know how to design a combination circuit write the truth table in terms of the input present state is the input and the next state. So you write the truth table so we take this combination circuit develop the truth table the present state as 3 inputs Q2 Q1 Q0 the next state as we call it let us call it D2 D1 D0 because it is going to the D2 D1 D0. So the moment you know that you write the truth table we have to look at the D2 separate D1 separate and D0 separate the normal course of time you would have picked all the once in this D2 column and go to the Karnoff map minimize it and you come out with an equation or sum of product equation in terms of Q2 Q1 Q0. So ultimately you will get 3 Boolean equation in terms of D2 D1 and D0. So let us write that I say DI is Fi of Q2 Q1 Q0 so I is nothing but 2 1 and 0 so you have D2 is F2 of Q2 Q1 Q0 D1 is F1 of Q2 Q1 Q0 D0 is F0 of Q2 Q1 Q0 so you get 3 equation that can be implemented. So normally we are not going to do this hand level design it is enough if you describe the truth table in terms of the hardware description language in a high level design then you get the design okay. So many a times this is also called the next state is a function of the present state. So we call it next state is a function of the present state. So mind you the next question I want to ask is that we still take the mod 6 counter but it does not count sequentially like 0, 1, 2, 3, 4, 5, 0 it counts in a crazy way that it starts with 0 then 5, 3, 2, 1, 4, 5 okay. So the question is can we design such a counter you know already the answer is very simple absolutely no worry anybody specify anything you change this next state logic you change the truth table you write start with 0 the next state is 5 you write 5 here the next state is 3 you write 3 here the next state is 2 and so on then you take form the equation or write the truth table in VHDL code then this should be you know perfectly okay it can be designed. And so let us look at the little bit timing how this present state changes with respect to the clock to give you an idea you may already know it but then let us look at the timing the symbol timing of a counter. So let us move on so here this is the clock waveform you have the clock edge and this is a positive clock edge triggered flip flop. So at the positive clock edge the present state changes its state and that cannot happen immediately in many a times in textbook it will be shown that this state change will have you know coincide with this active clock edge it is in practical circuit with delays it does not happen you know that here the flip flop has delay called TCO when the clock comes this D is transferred to Q with the delay called TCO. So after the clock edge it takes TCO time for the present state to change. So when the clock edge comes the state will change the count will change only after the TCO. So similarly here it is 1 then but when the clock edge comes it after a TCO delay changes to 2 and after TCO delay it changes to 3 and so on mind you there are 3 flip flops. So there is Q2, Q1, Q0 so there is TCO1, TCO0, TCO2 so I am showing only one time so there are 3 TCOs we are taking the showing the worst case timing delay ok. So this is one disadvantage when you go for little abstract high level block diagrams it hides lot of details actually you are used to maybe showing the 3 flip flops separate in thinking that clarity comes but you should be very careful when you put higher and higher level blocks more and more abstract you should not forget the details involved. So here you should know that when you say TCO the 3 TCOs we take the maximum for the maximum like 3 outputs are changing we wait for the latest output to settle there will be lot of glitches here I am showing just state change but there can be glitches depending on the state change say like from 1 to 2 there could be glitches ok because there are 2 bits are changing like 1 is 0, 1 and 2 is 1, 0 so there are Q0 and Q1 is changing state there could be transitory state in between so there could be glitches which I am not showing here but this in real life it can happen. So let us look at a picture of a binary counter I just want to show that picture ok so this is a real picture this is what you have used I am showing a mod 8 counter which is count from 0 to 7 so you know that this is a picture we have shown in abstract next level higher level block diagram but here you see D0 is Q0 bar D1 is Q1 exclusive or Q0 and D2 is Q2 exclusive or Q1 and Q0 and so on ok. So when we put it you should not forget that D0 is a function of Q2, Q1, Q0 D1 is a function of Q2, Q1, Q0 and so on. In the case of a binary counter you know that the D2 only depends on you know the Q2, Q1, Q0 and D1 only depends on the Q1 and Q0 it does not depend on Q2 but if you take a counter which count not very sequentially all this can change maybe the D0 can depend on Q2 also. So that is just to say that do not forget when we use such block diagram do not forget the detail picture you should have in your head you should in the mind otherwise you can make mistake in analysis when you analyse some circuit debug some circuit you can forget something and make a you know it can create trouble. So we have looked at the basically at the structure of a synchronous counter how what is the structure it consists of flip flop and combinational circuit and the flip flop output is called present state and combinational circuit is called next state logic. It is basically designing the next state logic all the intelligence is in the combinational circuit the flip flops are used to control it control hold the value at every clock this looks you know this is like a gate which allows you know gate is open then the next count comes in at the precise interval you know it is precisely controlled every clock at the count changes then we have looked at the output waveform. So in real life the output changes after the TCO delay which is the worst case delay of the multiple TCO of the output and finally I have told about you should though we abstract to the next level of the diagram you should not lose sight of the detail diagram because if you forget it then you can make mistake in analysis in understanding and so on. So I stop here in the next lecture we will continue with the timing analysis of this and we will build on this you know we will go on to the real life design system level design very soon. So I suggest you go back to this lecture revise do some simple design of the counters look at the structure of it try to understand the timing details and so on I wish you all the best and thank you.