 In the last lecture, we have seen how do we use channel engineering and source drain engineering in order to design a transistor at nano scale. In this lecture, we will look at two aspects the transistor design matrix, how do we go about designing a transistor, what are the matrix that we want to achieve and then subsequently go through a conventional CMOS process flow. So, that is the target for today's lecture. Before that, I just wanted to highlight one very important aspect that you see in today's CMOS transistor technology and that is something called reverse short channel effect, which we have not yet discussed. We are discussing this right now because we have discussed the channel engineering process, wherein we introduce pocket hellos. It turns out because of the introduction of pocket hellos, we end up with a new phenomenon which is called reverse short channel effect. As the name suggests, as you know if you have a short channel effect, the threshold voltage at long length is constant and as you start you know coming down in terms of channel length, your threshold voltage starts coming down very drastically. And we have now discovered various techniques such as channel engineering and source drain engineering, which we discussed in the last lecture. If we follow all that, we can really improve this roll off rather than this starting to roll off here, we can extend this even to much shorter channel length. But in the process, often times what we see is that before the V T starts coming down for ultra short channels, you may see a small region, where your V T is actually increasing with respect to decreasing channel length. And this is what is called reverse short channel effect. Again this is relevant when the channel length is very small, but very small window of channel length over which the V T increases as a function of decreasing channel length. I mean this is something interesting for you to understand. It invariably exists in almost all sub micron technologies, which have utilized channel engineering and source drain engineering. The reason for that is, it turns out the techniques that are used to suppress short channel effect, more particularly pocket halo implant itself is responsible for reverse short channel effect. So, that is a very interesting lesson to understand. And you know V T of course, becomes sensitive, it can either go up or come down depending on which region you are operating. However, it has been extended, the flatness has been extended to much shorter channel length. Eventually it is going to roll down anyway. Now, it is not difficult to understand this effect. Again if you were to look at this transistor that we have, let me just sketch that. This is my gate length. And you see when we talk of pocket halos at an angle, we have increased the doping concentration in these pockets. If this is an N channel transistor with P type doping and eventually you will make N plus junctions here. And the concentration here has gone up, this P concentration. The P concentration here has gone up. A very simple way to understand reverse short channel effect is to really model this transistor as three transistors in series. There is a very tiny transistor here, which is due to this increased pocket halo implant that I have. And then there is another transistor that I have, which is essentially most of the channel length that I have. And then again there is another tiny region here and you can sort of think about it as if from source to the drain, this is my source and this is my drain terminal. Because there is a non-uniform doping concentration, this is a transistor with high doping concentration, effectively larger threshold voltage. Very simple zeroth order V T model that we have looked at in the very beginning, you know that increased doping concentration means increased V T. So, obviously in this region, this small channel length transistor has much higher V T compared to the V T in this region. And again this is exactly identical to this. Now, you see again when the channel length is very large, this region is so small that it is very insignificant. You do not see the effect of these regions at all. But once you start decreasing the channel length, before you actually begin to see the short channel effect, there could be a region where this length is now comparable to, this is the region where these lengths are comparable to this middle length, which mean the total conduction property of this channel is governed by these two high V T transistors as well in addition to the lightly doped channel here. And because of that you could expect over a very short region, the threshold voltage starts increasing. This is where these small regions of pocket halos are actually becoming important in determining the transistor conduction. But once you start decreasing the length further, you know then you know our conventional short channel effect starts coming in because the length is so small that you know you can essentially have the huge depletion width here, which will essentially govern the conduction of the transistor and then you have a conventional V T roll off. So, this is your conventional V T roll off whereas, this is V T roll up if you will, V T increases here rather than coming down it actually goes up. This is what we mean by reverse short channel effect. And as I said this is present in almost all technologies and again depending on which technologies you look at, if some foundry has put in lot more halo, you may see lot more reverse short channel effect whereas, if another foundry B has little less halo, you may not see as reverse short strong reverse short channel effect as you would expect. Now, given all that background when we are designing a transistor for a new technology that is for example, let us say you know I am going from 65 nanometer technology scaling down to 45 nanometer technology, it does not matter it could be any technology node. So, how do you design a transistor to meet the requirement of this new technology node? It turns out eventually the reason why we are building this transistor is eventually make some chips and hence to make some circuits. So, these circuits in turn will have certain metrics, they need to have certain delay as we will see it turns out this is a very important function of the ratio of threshold voltage to supply voltage. They need to meet certain active power specification, they should not really consume too much of power and they also need to meet certain standby power or leakage power consideration. Again we are talking of digital technology, we are not talking of analog technology. In other words we are not talking of building amplifiers, building A to D converters, if that is your metric then your different kinds of metrics. For example, then gain, linearity all those things become very important whereas, here when we are talking of digital logic circuit the most important thing is speed of the circuit and the next important thing is power dissipation of the circuit. So, when I go to a new technology node I have a requirement that my microprocessor should operate at 10 gigahertz rather than at 8 gigahertz. That should in turn translate to what should be your transistor speed, that information comes from experience. So, if you have to build transistor with certain architecture if the transistor has a propagation delay of let us say 5 picosecond that may likely give you a microprocessor at 10 gigahertz. So, that kind of benchmarking is available typically then those who are making these chips routinely would have all that information. Make use of that information and for this new technology node you know what market demands in terms of where do you want to position your chip in terms of speed power and so on and so forth and then translate it back to the fundamental building block which is transistor. Then you come up with the specs what should be the delay or propagation delay which we typically call tau for a transistor what should be the active power dissipation which we call sometimes p dynamic or simply p d or we also call this as p active sometimes just p a c t and accordingly you will also come up with the leakage current spec it is essentially p leakage. This will essentially tell you eventually all this numbers in turn will tell you for a transistor eventually what you are interested is to translate from here to ask the question what should be I on what should be I of what should be capacitance c g and also c junction and so on and so forth all transistor capacitance. So, this will eventually translate to the numbers that we can deal with in terms of transistor design now I know I need to meet this on current specification this off current specification this is the on current to off current ratio I need to build for transistor at this technology node similarly I need to make sure that my capacitances are within the limit. So, that your tau which is c v over i if you recall is also met and you reach the required speed specification for that technology you see. So, these are the things that we identify given this we go down and we know what length that we want to design the transistor if it is 45 nanometer logic technology transistor length will be even smaller than 45 nanometer as we have already discussed earlier and you would also know what would be your VDD because you have the historic scaling trend you do not want to let the electric fields go up very significantly right you come up with the VDD these are all you know external specification and that also sometimes get governed by you know where will this chip go what kind of system is it going to interface with and what supply voltage is required there and you determine that and then you go down further what kind of oxide thickness I need to have for this transistor to get certain capacitance to get certain on current what kind of doping concentration that I need to have N A or N D and what kind of junction depths that I need to create for this transistor and in turn as we have already discussed we do not want to do a very blind transistor process we make use of source drain engineering shallow extension and deep source drain channel engineering which is pocket halos and super steep retrograde channel using all this we essentially iterate right start with the best guess may be iterate once or twice to achieve all these metrics that we have that is how we satisfy the circuit metric and in turn if you make a more complicated chip such as Pentium or whatever you have you know that will also meet the speed specification power specification one other important point that I need to highlight depending on what product that you are making what technology that you are going to use you also have certain reliability consideration for transistor transistor when fabricated in a chip should not only give this performance today next week next month but may be for a year or 10 years right and that is essentially gone by your reliability is transistor going to fail in one year or five years if it is a chip which is going in mobiles for example you know people change keep changing the mobiles may be once in couple of years but there is no point in doing a reliable transistor for 10 year lifetime you know it is an overkill right you will spend all your energy is trying to make it so reliable that you know they do not even use that chip for so long whereas if the chip is going in satellites you know or some other very mission critical applications then may be you know you need to focus more on reliability so all I am saying is that reliability also become very important and any particular application that you have that in turn will have a reliability specs may be one year ten year five year reliability and the reliability is essentially two kinds of reliability number one is called hot carrier reliability and number two is called gate oxide reliability we will talk quite a bit on gate oxide reliability in one of the future lectures but we may not talk about hot carrier reliability but suffice it to say at this point that these two reliability come about because of two different electric fields there is one electric field in this direction there is one electric field in this direction you see you apply a gate voltage which sets up a vertical electric field you apply a drain voltage which sets up a lateral electric field hot carrier reliability is due to the lateral electric field and gate oxide reliability is due to the vertical electric field if you have two higher vertical electric field you suffer in terms of gate oxide if you have too high a lateral electric field from source to drain especially at the drain age you suffer in terms of hot carrier reliability In other words, the message is that you need to also engineer this transistor and make sure that the fields are within certain limits. So, that you meet the hot carrier reliability and gate oxide reliability spec whether it is for 1 year, 5 year, 10 year, whatever. So, this is how you essentially do the transistor design. These are the metrics and these are the knobs that are available for you to reach these metrics. Now, let us try to sort of revisit these 3 points in the context of digital technology again. This is what is called a VT VDD design plane. VT is a threshold voltage of a transistor, VDD is a supply voltage of a transistor. And first thing that we recognized is delay, we just normalize the scale. So, we do not want to put numbers here. The delay very interestingly is a very strong function of VT VDD, which is not very hard to understand you see because delay depends on on current. On current depends on your VDD minus VT, your VDD and VG are same, it is the same supply voltage because your gate on current is if it is in saturation, it is VG minus VT whole square. And similarly, if it is not necessarily in I mean it is a transistor which is velocity saturated and then you may not have a quadratic dependence, it may be little less than 2. But nonetheless, it is this difference VG minus VT. In other words, we really are interested in VT over VDD ratio and that in turn determines what is this difference. When VT over VDD ratio is small, the delay is also small. When VT starts approaching VDD for example, in the limit as VT tends to VDD, you have infinite delay because you do not have any current to switch on your capacitors. Remember CMOS circuits, you need to switch capacitors from VDD to ground ground to VDD, you need to have current to do that. So, if your VT starts approaching closer and closer to VDD, it is not a good thing. So, a typical VT to VDD ratio that we try to target for especially high speed, high performance application is your VT to VDD should be preferably less than 0.4. That is, if you have one volt supply, then your VT should be 250 millivolt max 0.25, lower the better. Of course, it is not good for leakage current, but it is good for on current. Now, we are talking of on current and how does it impact the delay. So, VT over VDD is important and hence in this VT versus VDD design plane, these lines which have constant slope, you see anywhere along this line, my VT to VDD ratio is constant. That is obvious here, VT versus VDD is what we are looking at here. So, tan theta is theta is same here, VT to VDD ratio is same. In other words, these are called constant delay contours. Along this line, anywhere I go along this line, I have the same delay more or less. There may be some minor variation. We are not talking about those minor variations and when I go from this line to this line, the delay increases and that is not hard to understand. Going from this line to this line meaning for the same VDD, I am going from this VT to larger VT for the same VDD. That is how I transition from this lower line to the upper line. So, obviously VT by VDD is increasing, your delay is increasing. So, all these are constant delay contours and the delay is increasing in this direction. Very important to understand this. Let us come to two other metrics. We talked about for digital technology. By active power, what is it dependent on? I have already mentioned it sometime ago. C VDD F, in the context of VT to VDD design plane, P active is a quadratic function of VDD, which means P active is a very strong function of VDD. So, along this line, these lines are called constant active power contour. For all practical purposes, again barring minor variation, as long as I keep my VDD constant, my power is same along this line. When I transition from this line to this line, I am going from lower VDDs transistor which operates at 1 volt versus transistor which operates at 1.2 volt. So, active power would increase then. So, the P active as the arrow shows along this direction, your active power is increasing. Let us come to the last part, which is standby power. What is standby power? Transistor is not switching, but still there is a leakage current. A very simple illustration is that I have a CMOS inverter, PMOS and N channel connected in series. My input is steady state 1, your output is steady state 0, digital logic VDD. Ideally, when your input is 1, this PMOS should be completely shut off and hence no current, but we have already seen there is sub threshold current. So, there is a non-zero current which flows here. So, that is off current times VDD. Typically, when we talk of off current, we talk of off current normalized to the width. In other words, the unit of off current here is ampere per micrometer and that is why you multiply with the total width of the transistors that gives you ampere times volt which is essentially your leakage power. Then, notice that standby power is a linear function of VDD and linear function of off current. However, off current as you may remember from our sub threshold discussion, off current is an exponential function of threshold voltage. A very small change in threshold voltage, remember the sub threshold slope discussion results in exponential increase in off state current. In other words, what you see in terms of VT VDD design plane is standby power is an exponential function of VT, standby power is a linear function of VDD. So, for all practical purposes, we can say that once we fix VT, the standby power gets fixed essentially because of the VT value. Although, there is a minor variation because of VDD, we are not really worried about the minor variation. That is why these lines will not be perfectly horizontal. You see these lines will be, they will have some slope which illustrate that these are constant power. If it is, we call them here as a constant standby power contour, but in reality, even though VT is same, when VDD increases, power increases a little bit. I know that from this equation. However, when I go from this VT to this VT, there is a huge change in standby power. So, that is why and also standby power is increasing as the arrow suggests here in this direction. Lower VT, higher standby power, standby power has increased exponentially. So, you see what has happened now. This is a VT VDD design plane. It gives you now what is the allowed operating regime for your new technology. Your new technology may have certain delay number. Let us say this is my delay requirement. It has certain active power requirement. Let us say this is my active power requirement. It has certain standby of power requirement. Let us say this is what it is. What it means is that you can be anywhere in this triangle and still meet all the specifications that are required. In other words, there is no unique solution. You can have different combination of VT and VDD. You see and meet the specification that you had to begin with. The delay specification, active specification, standby power specification and that is why if you look at technologies, let us say 45 nanometer technology from different foundries. Let us say Intel's technology, TI's technology and Infineon, ST microelectronics, TSMC. They may all be meeting same specification, but the transistors could be quite different. The way the transistors are made because there is a window of operation and each foundry may have some preference in designing a transistor. Still meeting all those specifications that you have. So, that is also very important point to recognize. Although, nominally all of them are 45 nanometer technologies, they are not identical. There could be huge difference between each of these technologies, but all of them will meet certain specifications. With that, let us look at a typical CMOS process flow. Today's technology, most of the modern CMOS technology uses what is called a twin well CMOS process flow. What it means is that, the starting wafer type is inconsequential. You can start with n type or p type because either for n MOS or for p MOS, you have to do the channel engineering, source drain engineering. You have to define all the doping wells the way you want, which means you have to define both the wells anyway, the way you want it. That is why it is called a twin well CMOS technology. It starts with defining isolations, which in today's technology as I mentioned, trench isolation technology. Then you define wells, n wells for p MOS and p wells for n MOS transistors. After that, you form what is called gate stack, which includes gate oxide formation and polysilicon deposition and polysilicon patterning. Then channel engineering, do the halo implants for n channel transistors at the gate edge. You see you have to increase the p type dopant whereas, for p channel transistors the substrate being n type. At the gate edge, you need to increase n type dopant. That is why you need to have different halo for n MOS and different halo for p MOS. Then you need to form spacer as we discussed last time. Then do a deep source drain implant, shallow extension. Before the spacer along with the halo, you also do the extensions. It becomes clear as we move on. Then do the n plus p plus deep source drain implant. After implantation as I have mentioned earlier, you have to do a heat treatment and that is what is called annealing. You do the annealing and there is another very important step. We have not yet discussed. I will talk about it later. Something called solicitation. Define your contacts for metal, deposit metal 1 layer, then via 1 on top of metal 1. If your technology has 10 metals, keep doing that metal 2, via 2, metal 3, via 3 all the way up to the last metal is reached. That completes your process flow. Let us look at it a little more carefully. Now, let us say that I want to build this twin well c MOS process wherein I want to build let us say an inverter, an n MOS transistor here, a p MOS transistor here. Eventually connected, the two gates are connected, two drains are connected. Let us say that is the structure I want to build, which is a simple representative circuit. The first thing that I need to do is the whole silicon wafer is semiconductor. I need to define isolations. We have already talked about isolation. One transistor should be isolated compared to the neighboring transistor. How do you do that? Put in oxide in silicon. The way process sequence goes as this. You start with bare silicon wafer and you grow what is called pad oxide. So, what is shown out here is really the pad oxide grown on top of silicon. Then you apply photoresist, then you do a photolithography, use this mask and this mask will tell you that these regions should be blocked. Only these regions should be filled with the oxide and those regions should be opened. You do that and then you etch the nitride and oxide stack that you have. You see you have oxide and nitride that you have deposited initially. You etch that, then etch the trench in silicon and fill that trench using depositing the oxide. In other words, you start with bare silicon wafer, grow oxide everywhere. This is what is called pad oxide. Typical pad oxides that we talk about are of the order of may be 10 nanometer. As the name suggests, its role is sort of cushioning. Silicon nitride has if you put it directly on silicon, it can actually impact the silicon substrate. It can create defects in silicon. That is why you put oxide first and then put silicon nitride. Silicon nitride because silicon nitride is a very good barrier for oxidation. That is why we are putting silicon nitride. Using photolithography, we say that in this region, I want to build a transistor. In this region, I want to build transistor, but in between I want to fill oxide. What I do is that I put photoresist and if I want to define this. I open the photoresist here using lithography. There is this mask. This is the region that I am talking about. This region corresponds to a transistor here. This region corresponds to another transistor here. This region opens the photoresist P R and then you etch this nitride. That is what is mentioned here. Etch the nitride oxide. Etch the oxide. This whole thing is etched. Let us go back to this. This whole thing is etched here and then you have a silicon opening. In this area, silicon is opened to the external world. You continue etching silicon. Silicon is etched further here. That results in a trench inside the silicon. That is what is meant by etch trench in silicon in this region. Then you fill this trench by depositing oxide. This is how I define some regions to be oxide. Some other regions which are protected by this stack continue to have silicon underneath. Once this job is done, I strip off the silicon nitride and I strip off this oxide. Having done this, you will have a substrate now which looks like this. Part of the region is now SiO 2. This is isolation. The rest of the region is very fine silicon. The shallow trench isolation is done. The way it is done is that you polish the excess oxide, remove nitride. When you do all that, you come back with a very flat surface of the silicon wafer. Typical depths that we talk about here are of the order of 350 nanometer or 0.35 micrometer. Compared to the wafer thickness, this is not to scale. Remember that if you talk of 8-inch wafer, for example, that may be close to 1000 micron thick, anywhere from 800 micrometer to 1000 micrometer. This is an 8-inch wafer. Compared to this dimension, 0.35 micron is insignificant. That is why we call shallow trench isolation or STI. This trench is very shallow compared to the dimensions that we are looking at. Well then, we have isolated. What is the next step? Well definition. In some regions, remember, I want to make PMOS transistors. In some regions, I want to make NMOS transistors. Wherever I want to make PMOS transistors, I want to put down photo resist first. Open the regions. The mask will look something like this. This is the region which is open. Using this, I can etch the photo resist here in this region. You do n-well implantation. This is n-well implantation. Phosphorous and antimony. Phosphorous decides the deep junction depth of the well because we want well to be very deep. Antimony, as you remember, will determine a very steep retrograde profile here, which will help subsequently when I make the junctions. I have not made the junctions yet. Remember that, so that will help us engineer the transistor in a better way as we have discussed. When you are doing this in n-well region, the whole p-well region is completely protected because you do not want these implants to go there. That is why you need a photolithography step. After this complement, you need to define p-well. The mask is complement of that. In the active regions, where you do not have n-well, you will make p-wells. Open those regions again using this mask, which again apply photo resist, photolithography using mask. Develop the photo resist. You open these areas, then implant boron and indium here. Boron determines the depth. Indium sits here. When you do that, you clear the photo resist and then you do after implantation invariably, you have to do annealing because implantation, if you remember, creates damage in silicon. During that annealing, there is also going to be some diffusion. The wells will diffuse and you will eventually get some n-well depth and p-well depth. We have defined wells. We have defined isolation and active region. We are ready for gate stack. How do you do gate stack? You again start with when we are doing the previous implants, you would have had something called sacrificial oxide. There is some oxide you need to strip that. Again, get a bare silicon wafer, flat silicon wafer. That silicon wafer will look like this. There are these oxide isolations. There are these wells formed, p-well formed, n-well formed with the flat silicon surface at the top. I need to grow gate oxide, ultrathin gate oxide. That is what we are talking about today, 1 nanometer kind of gate oxide. So, grow gate oxide, deposit polysilicon because polysilicon is our electrode. Polysilicon gate technology. We will later talk about metal gate technology, but for long years CMOS has been silicon oxide based polysilicon gate technology. You deposit polysilicon. What happens here? SiO 2 very thin. Let us say of the order of 1 nanometer to 5 nanometer depending on what technology you are looking at, then polysilicon. It is polysilicon because we deposit silicon because silicon is being deposited on oxide which is an amorphous. I cannot get single crystalline silicon. I end up either with amorphous silicon or polysilicon. But in this case, I want polycrystalline silicon because I want as low resistivity as possible. So, I intentionally go to high temperatures of processing and that will give me polysilicon. So, I get polysilicon. It essentially means that there are multiple crystallites of different orientation. Crystal orientation is not the same. Lots of crystallites, but you see now polycrystalline is everywhere on your wafer, meaning all gates are shorted. I need to do the lithography to isolate the gates. Let us say this is where I am building inverter. There will be a gate here. Remember this is the length of the transistor and width of the transistor is perpendicular to this screen. When I see the top view, this is the length and this is the width. It is going down here. That is what is shown here. This gate and this gate needs to be connected in an inverter and you will apply an input to this connected gates. Let us say I have this mask. I use that mask and photolithography using poly mask. This is called poly mask, which is P 4, which means fourth layer of the mask. Develop the photoresist H polysilicon. So, when I develop the photoresist, photoresist will be remaining only here and here rest of the region photoresist is gone. I expose the polysilicon to a chant. All polysilicon and oxide will be gone in this region. In this region, photoresist was protecting that. Strip off your photoresist, you will be left with a polysilicon oxide stack. This is what we call a gate stack. Polysilicon oxide stack, if you take a cross section here, this is what you see. The cross section is not taken here. If you take a cross section here, you will essentially see one strip connecting the two. The cross section is essentially taken here. So, isolation done, N well P well done, oxide, silicon oxide, extremely important gate oxide and polysilicon is done. Polysilicon at this time is still undoped. It is not doped yet. When I do the source drain, polysilicon also gets doped. So, then I am ready for channel engineering. What do I need to do channel engineering? Halo implants and also extension implants. So, I open the N MOS regions and block all P MOS region. That is why this mask is called N plus select mask. It selects only N channel region and blocks as you see here, a line here indicates blockage, blocks P channel region. So, whatever you are doing is only for N channel transistor. So, apply photo resist, photo using N plus select mask. You open it, develop photo resist means opens it. You have photo resist protecting everywhere else. Implant boron at an angle. That is the halo. I am increasing the P concentration selectively in this region. At the same time, I also do extensions. So, I follow this boron is done at 45 degree. Follow this with arsenic implant at 0 degree implant. What it means is that, your let me just see here, let me get a different color here. Just sort of illustrate that. This is your arsenic implant. It comes at a 0 degree to the normal, meaning it is coming perpendicular to the wafer surface. I can set that in my equipment. Whereas, when you are doing your halo, halo was coming at an angle. So, what have you done? You see boron got implanted everywhere, but in this region that boron was over compensated by a very significant implant. Just to give an idea, the typical halo implant dose. It is the dose which determines concentration. The halo implant dose could be anywhere in the range of 10 to the 12 to 10 to the 13 per centimeter square. That is how we define the dose. You see dose is different from the doping concentration in silicon. Dose is what is coming down per unit area. How many ions are coming down? How many ions have you put in per unit area? That is the dose. When that goes inside, you look at the volume and get the volume concentration. On the other hand, if you look at the extension implant, extension implant easily is in the range of 10 to the 14 to 10 to the 15 per centimeter square. You see two orders of magnitude higher and that is why even if there is some p here boron that is over compensated by arsenic. So, this whole region becomes n plus. Whereas, this region becomes p, enhanced p-dipe doping and I have been able to introduce pocket halos. I have been able to introduce shallow arsenic extension. Why shallow? Because, implantation energy is very low here. Typical arsenic implantation energy because you see it is energy that determines the depth is of the order of 1 kilo electron volt. Whereas, when we talk of deep implant for arsenic that is more like 5 kilo electron volt, 7 kilo electron volt. This energy determines the depth and the dose determines the concentration. I choose the dose such that in this region p becomes n and I choose the energy such that I get a shallow implant. This is all in the n channel region by blocking the p channel region using the mask that I have. Now, I do the complement for a p channel transistor. Do another lithography. This is the sixth lithography step. I block all my n channel regions which means photolithography using p plus select mask which opens only p mask region. Then phosphorus is what we use for halo, phosphorus because I want to increase this n type concentration selectively. Phosphorus is n type dopant and that is at 45 degree tilt angle. You see then follow it up with the other implant you know which is a boron shallow extension at 0 degree. Boron is a p type dopant as you know and that is coming down here at very low energy. Again the doses are two orders of magnitude different boron extension know this at least two orders higher than phosphorus halo dose. You see and that will make sure that this become p plus region here and also very shallow because energy is chosen properly. Now, I have done most of the transistor design here you know whatever design I had done I have implemented that in the process except last aspect which is deep source drain. So, spacer needs to be defined. How do you define? We have already discussed deposit oxide deposit nitride. So, then you have oxide and nitride everywhere except that because you had this gate stack your oxide covered like this and your nitride also came like this and hence when you did the ion isotropic chain you left with this region correct and that defines my spacer here. It is self-aligned meaning no lithography here wherever there is a gate as it has identified by itself automatically and created a spacer using this kind of a process sequence. Ready for final implant n plus needs deep arsenic implant again use the same n plus select mass block all p regions open this n region arsenic implant now much higher energy. So, that it gives a deep junction a compliment for a p channel transistor photo resist you know implant boron here. So, boron comes here. So, after this implantation again you have to anneal the source and drain because there is a damage you need to anneal the damage and there is a silly side formation will come to that in a while. Let us just look at some of these dimensions here I have just take 0.18 micron as an example for an illustration. So, the typical wafer thickness depending on what is the wafer diameter if it is a 6 inch wafer it may be 500 micron 8 inch wafer is much thicker like well depths are of the order of 1 micrometre wells are deeper. Whereas trenches are shallower than this as we have already seen which is 0.35 micron trench. Source drain junction depths these are deep junctions are of the order of 0.1 micrometre and if you look at the extensions even shallower they may be just 50 nanometre or so and poly silicon gate thickness about 2000 angstrom or 200 nanometre gate oxide thickness depends on your technology again this 25 angstrom is 0.18 micron technology 25 angstrom as you know is 2.5 nanometre correct that is 25 angstrom. But, this can be anywhere from 1 nanometre to 2 nanometre 5 nanometre depending on which technology you are looking at. So, almost done with the transistor now we are ready for contacts I need to make contacts in the transistor you see. So, the contact is to be done again using a mask I need to make a gate contact source drain contact and so on and so forth. So, here what will happen again first of all you deposit insulator which is oxide and in oxide open the holes wherever you want to make contacts. These are plugs which will be conductive plugs and you fill these plugs in fact it is called contact plug typically it is filled using tungsten a CVD process chemical vapour deposition process. So, if I want to define contacts to source and drain of NMOS source then drain of PMOS you need 4 openings at least right. If you also want to have an opening for the gate you need to define the gate opening as well. But that may not come here that may come at a different location because whenever you want to make a gate contact you see gate would have been connected like this eventually you make a gate contact here. So, again when I take a cross section here you would not see that and that is what I have shown only 4 contacts there the source and drain source and drain here. And now this is how I would eventually take this you know this has been filled with tungsten this has been filled with tungsten all I have done is that taken these connections to the next level I need to do appropriate interconnection using metal one now that requires metallization. If it is aluminum metallization technology you deposit aluminum everywhere that is you had these contacts and you deposited this aluminum aluminum is shorting all contacts this is not what we want we want to now etch aluminum selectively. If I want to connect only this contact and this contact because this is a drain of n channel transistor and this is a drain of a p channel transistor in an inverter only these two should be connected. But this should not be connected here. So, I will use a lithography mask I will protect this region open this region open this region etch out aluminum here etch out aluminum here and I have connected the drain of n channel and drain of p channel together to form the output of the inverter. And this will be the ground potential or VDD depending on whether it is n channel or p channel in this particular case it is n channel transistor. So, this you can connect to ground later and this is p channel transistor which you can connect to supply voltage. Now, you have a inverter a very simple circuit fabricated through a twin wheel CMOS process. But when your circuit is more complex there are so many transistor one layer of metal is not sufficient and that is why you need to start forming multi layer metal interconnect. You again deposit insulator put a via wherever you want to take the connection to the next level metal to pattern metal to and so on and so forth. You go up to metal 10 or whatever it is. So, each metal layer will require a via and metal which is two masks. Now, you can see right I mean if you have to add another 8 metal 9 metal layers you need another 18 masks because one via and one metal another 9 metal layers will be 9 metal plus 9 vias total 10 metal layer interconnect let us say. So, 18 masks you already have 10 masks 28 mask process very complex process all these masks have to be perfectly aligned to the patterns that are already printed. Otherwise you know you would not have a working chip right and this is really a very complicated you know technology that we have been able to routinely practice today. So, this is what we call a conventional CMOS and in the rest of this course we will look at lot of non-conventional things in the transistor high k gate dielectric. In fact, from the next lecture we will start discussing the issues with silicon oxide today and why do you have to replace silicon oxide with high k gate dielectric. Metal gate electrode polysilicon technology it is called a dual polysilicon technology I forgot to mention that to you when I make n channel transistor the polysilicon in n channel n channel transistor region is doped n plus whereas, this is doped p plus because whenever you are doing p implants that implant will also go into this polysilicon. Whenever you are doing n plus implant that will also go into the gate it will not come in the channel, but it will go in the gate electrode. And hence it is sometimes also called dual polysilicon gate technology dual meaning there are two kinds of polysilicon here in terms of doping concentration one is heavily n type doped the other one is heavily p type doped and hence the name dual polysilicon gate technology. Now, we are talking of replacing that polysilicon with metal gates we will talk about some interesting aspects related to that and subsequently in the course you will also look at what is called silicon uninsulated technology. I briefly mentioned this in the context of better sub threshold slope we will also look at strained silicon channel technology intentionally creating strain in the channel and not only silicon after this discussion you will also be looking at germanium based technology or you know compound semiconductor based channel and things like that and also you will also see things related to double gate and finfet technology. All these we call as non classical CMOS meaning classical CMOS was very simple silicon oxide as the gate insulator polysilicon as the gate electrode material and bulk silicon as the substrate not SOI and single gate transistor the gate is only on the top there is no gate on the bottom. When we talk of double gate there is a top bottom gate or two side gates or you know all around gate you know gate is surrounding the entire channel. So, we will have more discussion on this in the next lecture and may be in the next lecture I will also tell you about or may be one of the subsequent lecture what we mean by solicitation you know that is something that we skip during the discussion of CMOS process flow suffice it to say at this time that silicide what we mean by silicide is essentially it is a complex of metal plus silicon a combination of metal plus silicon is called silicide. So, then you can have titanium silicide it is a compound titanium silicide or you can have cobalt silicide or you can have nickel silicide and so on and so forth. The thing about silicide is that silicide has much lower resistance compared to silicon because you are putting some metal in it, but certainly it is not as lower resistivity as a metal is. So, it is somewhere in between silicon and metal the purpose of using silicide is essentially to reduce resistance compared to what it was for silicon. Silicon has higher resistance especially in the parasitic transistor region you see you need to reduce the resistance. In other words let us say the opening contact opening that we talked about let us say there is one contact here and let me just say that there is a contact here and there is a contact here, but remember how the current flows right current is flowing like this. This is a region which can be controlled by the transistor this region cannot be controlled I have talked about this earlier and this in fact is called parasitic resistance. Now, if this region which is silicon can be converted into a metal silicon complex this parasitic resistance that you have effectively or parasitic can come down for silicide. So, then what all we try to do is convert this region of silicon into a silicide which is a combination of metal and silicon and that is what we do today otherwise you would have had much higher resistance that is why it is a process that is used wherein you put the metal on top of it you anneal that metal at high temperature that metal will react with the silicon and form the silicide here. And it will also form the silicide here as well which is also good because that will also reduce the gate resistivity it is poly silicon becoming a silicide there in this region you have insulator. So, there would not be any silicide that is good because otherwise you would have a gate and drain shorting to each other that does not happen. So, that is the purpose of silicide. So, good we could cover that today. So, we will stop the lecture today and in the next lecture we will start talking about silicon oxide scaling and why do we need high K gain dielectric.