 Hello and welcome to this presentation of the STM32C0 real-time clock. It covers the main features of this peripheral, which is used to provide a very accurate time-base. The RTC peripheral features an ultra-low power calendar with alarm, which runs in sleep and stop modes. As long as the supply voltage remains in the operating range, the RTC never stops regardless of the device status. The RTC consumes only 1.13 microamps per MHz. The hardware calendar is provided in binary coded decimal or BCD format to reduce software load, and particularly when the date and time must be displayed. The key features of the RTC are seconds, minutes, hours, weekday, date, month and year, provided in binary coded decimal format. Sub seconds are provided in binary coded decimal format. Add or remove one hour on the fly to the calendar in order to manage daylight savings. One programmable alarm, which can wake up the microcontroller from sleep and stop modes. The calendar can be calibrated thanks to a reference clock source, which is the mains at 50 or 60 Hz. A digital calibration circuit allow in compensation of the crystal accuracy with 0.954 ppm resolution. A timestamp function to save calendar contents in timestamp registers depending on an external event. Regarding reset events, the calendar shadow registers and some bits of the RTC status register are reset to the default values by all available system reset sources. The other registers, including the current calendar registers, are reset to their default values by a power on reset and are not affected by a system reset. In addition, when clocked by LSE, the RTC keeps on running under system reset if the reset source is different from the one of the power on. Here's the RTC block diagram. The RTC has two clock sources, the RTC clock or RTC CLK used for the RTC timer counter and the APB clock used for RTC register read and write accesses. The RTC clock can use either the high speed external oscillator or HAC divided by 32, the low speed external oscillator or LSE, or the low speed internal oscillator or LSI. The RTC clock is first divided by a 7-bit programmable asynchronous pre-scaler, which provides the CKA pre-clock. Most of the RTC is clocked at the CKA pre-frequency, so in order to reduce power consumption, it's recommended to set a high asynchronous division value. The default value is 128. Then a 15-bit programmable synchronous pre-scaler provides the CKS pre-clock. The CKS pre-clock must be 1 Hz in order to update the time and date BCD registers in 1 second increments. The sub-second register resolution is defined by the CKA pre-frequency. By default, it's 256 Hz when the RTC clock frequency is 32,768 Hz. The SSR register resolution is increased by reducing the asynchronous pre-scaler value. The asynchronous pre-scaler can also be bypassed. In this case, the sub-second register resolution is defined by the RTC clock frequency. Current calendar is saved into timestamp registers when a programmable edge is detected on RTCTS input. When the current data becomes equal to the time programmed in alarm A, an alarm event occurs, which can be routed to an RTC outpin. The 512 Hz or 1 Hz clock can be driven in one of the RTC outpins for calibration purposes. In this figure, the shadow registers belong to the APB clock domain. This is explained later in this presentation. Note that RTC out1 and RTCTS are mapped on the same pin. The RTC is initialized using a safe method. The RTC registers are write protected to avoid any possible parasitic write accesses. A specific sequence must be written in the RTC write protection register. Initialization mode must be entered in order to change the clock pre-scaled values or the calendar values. The RTC calendar keeps running in sleep and stop-low power modes and during reset. Initialization of the time and date registers is performed via their shadow registers, which belong to the APB clock domain. The sub-second register cannot be initialized. Every RTC CLK period, the current calendar value is copied into the shadow registers. The calendar sub-second time and date registers content can be read in two different modes. When the bypass shadow registers control bit is cleared, the shadow registers are read. The advantage of this mode is that it guarantees that all three registers are consistent. Reading either RTC SSR or RTC TR locks the values in the higher order calendar shadow registers until RTC DR is read. The disadvantage of this mode is that when exiting sleep or stop mode, the software must wait for a synchronization delay to ensure that the shadow registers are updated with the last calendar register values. This synchronization delay can be up to four RTC CLK periods. Also, to read the RTC calendar registers properly in this shadow mode, the APB 1 CLK frequency must be equal to or greater than 7 times the RTC CLK frequency. When the bypass shadow registers control bit is set, the actual calendar registers are read directly. The advantage of this mode is that there is no need to wait for the synchronization delay. The disadvantage is that the read values can be false or not consistent due to synchronization issues, so they must be read twice and compared with previous read values to ensure that they're correct and coherent. This slide presents the main calendar features. Daylight savings can be managed by software with automatic one-hour addition or subtraction. The RTC can be synchronized to a remote clock with a high degree of precision. It's possible to synchronize the RTC CLK to this remote clock by adding or subtracting an offset to the sub-second register on the fly with CKA pre-clock resolution. This feature is commonly used in RF applications. A reference clock, mains at 50 or 60 Hz, can be used to enhance long-term calendar precision. The reference clock connected to the RTC REF IN pin is automatically detected. When the 1 Hz CLK becomes misaligned due to the imprecision of the LEC CLK, the RTC shifts the 1 Hz CLK a bit so that future 1 Hz CLK edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference CLK. When the reference CLK isn't available, the LEC CLK is automatically used to update the calendar. The digital calibration is used to compensate crystal inaccuracy and accuracy variations with temperature and aging. It consists in masking or adding a programmable number of RTC CLK cycles, fairly well distributed in a configurable window. The calibration value can be changed on the fly depending on detected temperature changes, for instance. A 1 Hz calibration output signal is provided to measure the crystal frequency before and after applying the calibration value. The accuracy shown here is the resolution of the digital calibration. The calibration window size is configurable between 8, 16 and 32 seconds. For a 32 second calibration window, the accuracy is plus or minus 0.477 ppm. The total correction range is from minus 487 to 488 ppm. The accuracy resolution scales with the calibration window size. Final accuracy in the application will depend on the crystal parameter precision, temperature detection precision, how often the software calibration procedure is launched, etc. In order to reach the precision of the calibration window, the measurement window must be a multiple of the calibration window. A timestamp function is available. The sub-second, time and date values are saved in timestamp registers when an event occurs on the timestamp IO. If a timestamp event occurs while the timestamp flag is set, the timestamp overflow flag is set. In this case, timestamp registers maintain the timestamp of the previous event. The RTC embeds one flexible alarm based on comparison with the calendar value. The alarm flag is set if the calendar sub-seconds, seconds, minutes, hours or date matches the value programmed in the alarm registers. The alarms events can wake up the device from sleep and stop modes. The alarms event can also be routed to the specific output pin RTC out with configurable polarity. The calendar alarm sub-seconds, seconds, minutes, hours or date fields can be independently masked or not masked for the comparison. When the masks are used, periodic alarms are generated. Two RTC events can generate an interrupt. These interrupt events can wake up the microcontroller from sleep and stop modes. The alarm A interrupt is set when the calendar value matches the alarm A value. The timestamp interrupt is set when a timestamp event occurs. The RTC peripheral is active in run sleep and stop modes. RTC interrupts cause the device to exit sleep and stop modes. In stop mode, only the LSE or LSI clocks can be used to clock the RTC. In standby and shutdown modes, the RTC is powered down. The RTC of the STM32C0 is a subset of the one present in the STM32G0. Here are the features which have been removed for cost and consumption reasons. The second alarm B, the tamper unit and the backup domain and therefore the capability of maintaining the RTC active in standby and shutdown modes. A bit is available in the MCU debug interface in order to stop the RTC counter when the core is halted for debugging. This is a list of peripherals related to the real-time clock. Please refer to these peripheral presentations for more information if needed. Reset and clock controller, power controller, extended interrupt controller. Thank you for attending this presentation.