 So, today last in the previous one, previous lecture what we had done was the canter network and with that we figured out what is the bound on the straight line on blocking switch, which was o on o n log 2 n square actually. So, with that we can always create a straight line on blocking switch that was the last thing which we did. So, with that now more or less most of the theoretical stuff is kind of over. So, now I would actually be doing something to do with time switching, how to build up a time switch using your random access memory. It is a basically a electronic circuit schematic which I will be discussing and how this actually functions. And then we will expand it on to what we call super multiplex switch and then of course TST configuration and you will get an idea that the switch is as far as the operating system of a switch is concerned. Switch is nothing but will be obstructed as nothing but a random access memory, where the control software has to just insert nothing but control words. And once you write a control word certain connections will automatically will get set up actually. So, as far as the control action which is required write the appropriate word things will happen in the back end automatically. You need not worry about how the switching is implemented. So, that is how it is obstructed in the software system because one has to write even an operating system of such a switch. So, first of all let us go to the basic time switch implementation. So, now what is there with us before we start designing this? We have we can take a even carrier system. Even carrier system will have as all of us know total 32 voice slots a 32 actually octets per 125 microsecond. And we are already aware of this that out of this there will be two slots which will be already occupied by design one for signaling purpose another one is for framing purpose. So, that you can identify the frames at the receiver end. So, frame boundaries are detected by these two. So, usually the idea is when you get such kind of an even frame I should be able to push it into a time switch there will be some controller some control action which we have to do which will now identify how actually it functions. And the end of it again I will get nothing but an even only coming out. And of course, your framing and signaling which is your 15th because I am counting from 0 and 30 first these two slots will be signaling and framing slots. So, I am not bothered about them, but the remaining slots will get swiped. So, if you might have some data at 0th slot which might end up in this octet might be arriving at third slot and so on. So, I am basically changing doing the time slot. So, are being changed interchanged actually with each other. So, this kind of switch is also known as time slot interchanger. So, in fact something like this can also be done in optical domain for implementing all optical switching circuit switching actually. And that is an optical time slot interchanger that is done usually by delay lines. Del line can always act as a memory fiber loop delay lines are used there here I will be using simply random access memory. So, now with that thing now the problem is this what I will do with the signaling in framing these are not required when I am doing time switching. So, usually when these will be coming at the interface first thing will be done is the information which is coming in your signaling thing will be listened by the interface board will be taken out. And this information then can be rooted because it is like a virtual channel will be going to the controller the software which is running inside the switch which is a master basically which runs everything is like operating system of a PC. So, in fact PC is also designed exactly in same with architecturally is not much different is a special kind of computer that is only thing we just switching functionality. So, once this is bypassed that signaling slot does not matter actually signaling happens end to end similarly the signaling information will be injected into this even till it goes to the next guy where it will be again taken out. So, signaling information is never switched if it has to be switched it has to come here it will identify where it has to be forwarded and it forwarded over a signaling channel. So, signaling channel provides a virtual connection or a virtual channel between two end points over a link always this is not like a circuit switching where the voice is simply just passing through this switch. So, these are basically what so that these entities can talk to each other similarly once have identified the frame here this frame boundary deniation octet is also not required to be switched. So, usually what you will get is a 30 frame or 30 slot frame that is what you will get not 32. So, the board interface board itself will identify that it will also give you the timing signal which is important timing recovery it would have done. So, it will give you a frame clock a pulse when the frame starts and when frame ends because within this board you require this within the switch. It will give you an octet clock every word this is known as word clock also and then there is a bit clock there are three clocks which will be there in the system and you will be writing into RAM you will be reading into RAM as per certain thing when it comes to the output you will again be actually getting all the three clocks you will be getting the frame which is going to come out serially and then this will be used to create whatever is the frame boundary thing the 31st slot the 16th slot will be inserted by the controller information signaling information you will get back new even which will be transported further. So, this will be more or less the mechanism in all kind of time switches for all kind of multiplexing. So, there is going to be a important thing in the interface board itself you will be stripping out your signaling end framing octets you will be actually retrieving out the all the three clocks which will be now will be used all through this particular board and they will be combined back again because once you are on this serial line. In fact you are clocking information your framing information signaling all three are embedded in one single serial line. So, I keep them in parallel while doing the switching. So, I am not going to discuss how this will be done this I think has already been done at some other places frame delineation mechanism clock recovery has been done in some other courses. So, but it is done that is it that is my assumption that actually even happens in reality. So, you can do it through PLL or whatever kind of line coding mechanisms which are used to recover the clock, but those are extremely important if that clock sync is not there you cannot receive anything it is impossible. This switch will only function and operate if you can retrieve the clocks. So, usually most of the line termination unit because anything where you terminate a line coming in line is a line termination of L T U there you will be always having an indicator whether my clock is in sync or not. If your PLL says that I am in synchronization then only you will interpret whatever is coming on the line otherwise you simply discard it. You should not start interpreting even without synchronization that is not possible. So, there is an assumption that there is synchronization this true with all kind of system CDMA becomes even severe because CDMA even the codes also need to be synchronized PN sequences which are there on at both ends. So, same concept applies here. So, my assumption is I got 30 slot and I am also getting the timing signal. So, this is my octets which are coming in and in fact another thing which I will do is these are the serial octets and I will be converting into a parallel stream now. This serial I will be converting into parallel 8 bit wide bus will be there which will be carrying the bits of a octet or a word. So, already this will be this requires a word clock remember otherwise you cannot do it because whenever the word boundary will come at that point at time you have to signal it is a basically serial in parallel out. There is going to be a clock here which is a word clock and so there is some clock extraction mechanism which is sitting here. So, what I have to do is these words which are coming in I have to write them into a memory. So, I will use a random access memory here technically data in and data out both are going to be from the same bus they are not from different buses actually in actual RAM. But here I am showing it as if coming from two buses only thing when you are having a read mode the same bus will be used for reading purpose when it is in write mode it will be for a write purpose. So, I am not showing that actually, but I think you can build up even that part. No, I am only able to write from the input to stream read to the output to stream, but technically it will be done from the same bus. I have already converted to parallel 8 bit you have to write in parallel there is nothing like serial into a RAM. A random access memory will have whatever is the memory size memory word is a 64 bit you have to have a 64 bit bus whatever is the word on that whenever you give the clock that time it will be written in the address which is there on the address lines. If you cannot have those many wires internally inside the chip you will be doing this job. So, whatever I am doing will be done internally inside the chip. So, that you actually have less fan out or less pins on the chip, but in abstraction wise yes those many lines are required. You require number of data lines is equal to data word size and whatever is the address those many bits will also be required to transfer the address. So, I am explicitly showing them separately. I am also showing input bus and output bus also separately, but technically it is actually same bus which will be coming in you will be reading here and there will be an end gate this is basically if the write is enabled and if the read is I call it this will be something like this. So, there is only one bus which is going inside. So, whenever the read is enabled read is 1. So, this will be 0 and this is the end gate. So, it is stopping nothing can be written into actually at this point, but here you can read it. So, whatever is there on the line so whatever address you will feed the same data will simply come and latch on to the bus and then that will become visible to outgoing bus. And whenever you say I am going to write into this this is a write bar. So, this will get inverted this will be enabled this will be disabled whatever is the address at that location you will be writing and this read write read oblique write bar also will be going into the chip for writing purpose. You can design in VLSI whatever way you wish and in fact VLSI chips for doing this thing is are already available. So, you can build up a limited 16 by 16 telephone exchange it is possible for you to build it actually in the lab and then fabricate test do whatever you wish with that. So, smaller size is pretty simple even larger size you can do because crossbars also technically are built using this logic gates and whatever mechanism I am telling that actually is the part of the design. So, this is what is going to be the RAM. So, I have to tell in the RAM at which location I have to write. So, I am assuming that first octet will be written at first location second will be at second location third will be at third location and so on. And 30th octet will be written at 30th location they will be written sequentially. So, that actually means whatever is the third clock I have to run a counter with this without this I cannot work actually. So, I will take this I will run a counter when this counter will be reset to 0 when the frame clock will come remember they are three clocks frame bit and word. And since I have converted to serial to parallel your word clock will be actually used here for serial in parallel out this what the clock which you are using is the bit clock which will be nothing equal to word clock this for parallel system. So, technically you do not require a bit clock you only work with two clocks one is frame other one is the word clock because my bit size is now increased whatever is the one octet size. Now, my bit is of this duration but they are parallel of that they are eight parallel bits on eight parallel lines that is what has been done here. Now, this counter is always going to be reset by frame clock. So, whenever the frame actually starts that time it will be set to 0. So, first octet 0th octet will be written in 0th location first one will be in first and 30th will be in 30th location this will automatically happen. So, this will give you the address this will be used for writing purpose remember this is a write address and how about what will be the size of this bus this will be also again parallel line. If you implement in side the VLSI then this will be depending on how many words are there if it is a even system you have 30. So, you require how many bits 5 bits because 2 is for 5 is 32. So, this is going to be 5 bit bus. So, this technically depends on how many words will be stored inside the RAM. RAM size will govern this I have to also read out remember. So, read out address also has to be fed into the system and this will be also going to the same port where the write address goes. So, I require a switch because of that. So, there is a switch or a multiplexer this is the address of 5 bits this address will come from another location I will tell how it comes I think some of you can immediately guess it because this is a very intuitive design there is nothing to understand. And of course, now when you are writing that is very important because read and write both cannot happen simultaneously in this switch. So, what we do is the word clock or any clock the will be going high and low for 50 percent of time it is high 50 percent it is low then the next clock pulse will come. So, the first part when it is 1 I can use it for the reading or writing whatever way I wish actually does not matter for me. So, if I want to use the first half for reading for writing the second half for reading which is perfect. So, whatever you write in the current frame can be read in current frame, but if you read first and then you write in the next half whatever you are going to write now will always be read in the next frame not in the current frame that is only implication. So, usually because we do not want to create one additional 125 microsecond delay inside the switch we always do a writing first and read later on that is usually is the strategy this is a very small thing. So, design will work correctly, but you start introducing 125 microsecond delay additionally inside the switch. So, that we can actually avoid in the scenario and of course, one important thing is that whatever you are writing now may be actually reading the next frame that is possible, but the question is when you are reading here in this cycle you may not be reading the word where you are writing from here that is important. So, part of it will be written later on will be read later on part of it will be read in the current cycle that is possible. So, it is not that everything remains in the same frame whatever is this all updates which are in one frame at the input may not be in one frame at the output that design requires two memories actually. So, what you do is the whole frame will be written in the first frame and nothing will be read out and in the next frame you will be reading the whole thing. So, that whole frame remains intact here I am not doing I am not using two ramps I am using only one single ramp. Those are also required if I have to put a time expander currently number of slots thirty slots are here thirty slots are at their output side, but then we will for example, implemented TST time is space time and I have to build up a real a strictly non blocking switch. The incoming number of slots in 125 microsecond is thirty outgoing will be 2 into 30 minus 1 ok which will be 59. So, 59 slots at the output and 30 slots at the input there is a clocking problem actually. I cannot use this kind of mode you read air and write air this can only be done if incoming slots and outgoing slots per unit frame time is same then only then it can be done. So, in that case we use twin memory system which can be clocked at two different clocks. So, that design can be made by modifying every system time permits I can actually I will tell you that thing also. Sir, this duration sir is in which which you have written W and R sir. This is a one clock pulse one T one word clock this will be technically 125 microsecond divided by number of slots which are there per frame. So, in this case it is thirty this is the value of T if it is a even carrier T one carrier system 24 slots it will be divide by 24 ok, but more or less I think the basic concept once you understand you can almost start designing almost all kind of things. So, I am going to write it. So, this actually means when this clock is going to be 1 when this will be 0 I have to put this address. So, 0 means this and 1 you have to select this is the control entity and I have to also feed read write bar here also. So, I will take this particular pulse sorry not from here because I have to write. So, write bar has to be it has to be 0 then only the write will happen. So, when it is 1 it gets inverted you have a 0 when you feed 0 the write happens and this address is what is going to be fed into the RAM you can write in sequence whatever is coming at the input now is ok. Let me explain it again this is a clock pulse which is coming whenever the clock pulse has to be 1 I have to write into the RAM and whatever is the value of the counter it has to go to that address counter is always reset at the beginning of the frame it is starts counting from 0. So, in our case will count from 0 goes till 30 then again it will be reset to 0 it will generate 5 bit address which I am taking out this address has to be sent to the RAM to give the location where the incoming octet or incoming sample voice sample which is 8 bit sample has to be written and it has to be done in the positive cycle because negative cycle I will be using it for reading purpose. So, when it is when the clock is high I have because remember read write bar actually means whenever read write bar input is going to be 0 write is 1 because w bar is 0 so w is 1 and r is 0. So, it will be doing only write operation that is why this after the inversion I have connected to read write bar and that that point of time this value which I am feeding for control to this MUX is 0. So, this input will get connected to the address input not this one when this value is 1 this will get connected this I will use it for reading purpose. So, I will be writing sequentially or cyclically into the RAM this cyclic write actually this cyclic write configuration and I will do a cyclic read cyclic write and a cyclic read. So, so far this was the writing part I am going to show another bus which is the outgoing bus, but these two buses are going to be attached the way I have shown using two gates and a common bus coming to the RAM it will be exactly that configuration, but I have not shown that thing explicitly here. Now, the question is how to read so there has to be somewhere some information remember when I did TSI I said there are going to be four slots and these have to be mapped. So, four has to be read here two has to be here one has to be here and three has to be here I want to generate this mapping this mapping has to be stored at some place some control information drawing it on the board is fine I am storing it in my mind the equivalent of that is some control memory. So, what I can do is I can always say in the first slot the first location of the control this is the control memory I will read the value I will put the value 4. So, while reading in slot one of the output frame I have to read from location four or fourth slot of the input frame should be here it has to be transferred here next I have to put two next I have to put one next I have to put three. So, I will do the exactly same thing I will take this as an output from we call it a control memory this is known as speech memory s n. Now, which is the location which has to be chosen in one particular slot this will be given by this counter only. So, I can just take this counter value use it again I will use a MUX there is a reason for doing that I will explain what the other address will be used for and this is what I am going to put as an address and when I am actually activating this this read address is going to be connected that time this address should be fed to control memory. So, this same control signal I can actually use. So, when it is read when this is one you are reading and I am also reading at the same time from here we will also write into this control memory that is what your operating system actually will do. So, this bus will be connected to interface or a bus of your PC. So, it will be connected to a your CPU or what you call ALU ALU RAM ROM everything will be there connected to bus and this will also be connected to the bus where you will write something. So, you will have the address. So, it will be what we call memory mapped address or IO mapped address kind of addressing can be used and you can write the words into this and they will be once it is written switching functionality will happen yes simple as that. So, as far as the machine is concerned it has to write into the world. So, you are switching technology totally independent of the computing, that both can be interface together. So, when this is in the read mode when this is one this will become one this address will be fed from here which is coming from this control memory whose address is coming from the counter. So, in the first slot I need to read four. So, one will be coming from here it will be connected because it is in the read mode whatever is written in the first slot which is four will be coming out all the way and this is also one. So, it will be get connected this is in the read mode. So, it will be read out and it will be coming on this side. So, fourth slot will be read in the first update location at the outgoing frame yes this is a control memory. So, what is written in RAM? Speech memory is the actual speech words whatever is your voice samples this is this is not having your voice samples is a circuit switch basically. So, whatever is the input frame whatever byte update is coming I am not bothered whether it is a voice or whether it is data actually as far as I am concerned I am able to implement a time plot intersinger. So, who is deciding this information to this slot? This has to be done by the controller the intelligent entity running in the switch. So, when you for example, you are you are having a phone and you connect to an exchange you dial certain number that number will be processed by the exchange. Interface board I told you there is interface board in the exchange in the first lecture and that particular thing interface board will know the number it will figure out where the routing has to be done. Once it figures out from this incoming port for to this outgoing port the connection has to be set up for your call that time it will it will not find out. You are actually at this slot number at the input the outgoing which I am connecting to some other guy some other exchange or some other person is on this slot number on this frame correspondingly it will actually put the words inside the control number that time. Once it is put this path is already set up or activating a cross point it is equivalent to that. Now, this particular address and there is one more thing the data which will be write written into this will be coming from your controller in fact, it does not matter you can I can even modify this design I need not take this r w bar from here. I can keep every all the time this in read mode this is anyway I am selecting at this point it is. So, even this r w bar can also come from this side. So, this circuit has to always keep this team r mode or read mode most of time whenever it wants to write it can write at any point of time whatever value it wants let this be taken care of by control and you are able to build up a very very simple and elementary basic time switch element. So, any doubts so far. See, what is that element called just below the ramp? This one this is a selector selector or multiplexer you can call it is taking two inputs and putting into one it is a multiplexer is a space multiplexer actually. It is selecting from one of the two space options is not TDM or WDM it is a space is selector basically the same unit is present here selector same thing. We basically gate 8 input and gate and only one of the two can be selected at any point of time. So, two end and one or it is good enough to build this. So, all are 8 input gates and 8 outputs that is everything. So, same thing is to here only thing is that this is what one has to also understand that when this count is going to be reset. So, you require two clocks word and frame clock here word clock will also be used to generate a 8 bit parallel system. So, most of the switching will be done in parallel this does have implications actually if you work at extremely high bit rates parallel lines always do create a problem. Because path lengths for one bit and path length for another bit may be actually different which may create clock skew. So, as your bit rates increase your size has to go down. So, at this clock skew can be controlled, but that is the only one implication which we have. Sir, I think it should have another parallel to serial converter at the end also. Yeah, right you are right you need a parallel to serial converter. In fact, there will be complete interface board which will take all parallel to serial thing which will insert whatever is the control thing which will insert the framing stuff and then from a even frame which will go out. So, there is a interface board here. So, most of the interface boards will do all this job. On all telecom switches the interface boards job is to take out all signaling take care of framing, deframing and make into a raw format which is internal to the switch which need not follow any standard because the whole switch usually comes from one single vendor and he knows about everything inside these two boundaries. So, only when you are actually talking to somebody else at the border itself only this standard comes into picture not inside. Inside you try to optimize to reduce the hardware and improve the performance. So, performance per unit of hardware has to be maximized that is a objective of any good design. Now, I can just move into something. Sir, what is the typical value of this word clock that we are using in the telecom? It depends on the frame. For example, if the word clock if you are going to have even carrier system it is 125 microsecond by 30 that is a word period that is at p. So, 30 divide by 125 microsecond that much is that much hertz or that much pulses per second is the clock rate. If you are going to use E3 system because number of words per 125 microsecond are different it is going to be different. If it is SDH it is going to be still different actually, but SDH works ok. So, that is actually usually part of the optical networks course the SDH framing and reframing thing. So, that I am not going to cover it here, but conceptually that is also 125 microsecond frame. But, you can actually look into there is a already a recorded lecture on that is there already on the site which talks about SDH, but that is in E646. Sir, why is that control memory you have one selector now. What is the second input for that? It is coming from the controller CPU. So, what? There is some master command of the switch which has to give this map. No, that map will be written through the data now. Through this, through this line. Control memory we have one data input now. This is the data input now. This is the address sorry this is the address where you will be writing this is the data, but where you are going to write what data. Here are we not writing sequentially in this like. Yes, if you do that in that case you require this framing thing you know that in the first slot I will be writing only in first location, second slot in second location third slot in third location only. If you put that constraint additionally then you can do away even with this address, but only thing now the machine or the controller should know what are the timings here. Because it has to know when the first slots turn will come when I can write in the first slot first location. Because in this location you can write only in the second slot here you can write only in the third slot not in arbitrary in any slot in that case that is only additional cost. That also is implemented by hardware manufacturers this particular trick because you save on track and track is important in any circuit. You reduce the track length, you reduce the cost, you reduce lot of complexity actually in manufacturing. So, that is I think another one trick which is used. So, now let us go to the we have 5 more minutes. So, I can quickly explains a super multiplex time switch. Time switching is good because you can easily operate at these bit rates. It is better to always do it in time mode because remember all the clocking rates are within your limits this can be handled even 1 gigahertz is actually nothing for us nowadays. Our computers works at even 2 gigahertz or 3 gigahertz kind of rates the frequency which we are talking about is pretty small compared to that for all of our circuit elements. But I have only told you for a framing of 30 slots suddenly you get a requirement that you are going to get a termination of 16 even carrier systems as in coming 16 even carrier which are going outgoing. Once this happens how you will build up a switch one way you can say for even carrier system I can use this particular time switch 16 30 frames in and 30 frames out and then I can create a space switch of 16 by 16 and then again time switch TST configuration. I can do that I can build up a rearrangement on blocking switch, but then suddenly you will realize you can actually do even simply with time switching only, but you have to do some trick. The trick is that whatever frames are coming 16 frames you will get these frames all of them are 125 micro second duration and if they are all synchronized I can combine all these and create one frame which is again 125 micro second, but now the number of octaves which are setting inside it is 13 to 16. So, what you have to do is you have to take the first one compress it in time and push it here. The second one will be compressed and push here and 16th one will be push here this is known as super multiplexing is already a multiplex stream I am doing further multiplexing of that without taking apart the whole system. So, only thing which you need to know is what is how the time compression will be done on this. A trick is again this very similar circuit which has to be used, but remember now your incoming clock rate and outgoing clock rates are different that is the only consequence which you have. So, this is known as frame hold buffer actually. So, time compressor is known as frame hold buffer. So, circuit will be very similar, but you will be having two ramps not one. So, what you will do is you will keep on writing in one ramp and there will be a switching functionality here and whenever this is going to be read out this will be connected for reading in. So, whenever this is going to be switched here this will be switched on this side that is the only thing which has to happen rest everything remains the same and what you do is the whole circuit not only this path have to be switched your timing circuits also have to be switched whatever we have at the other end. And of course with this actually means I will be able to put 125 microsecond whatever is coming here will be coming at this point, but there is a problem if you want to put it only here what will happen to the remaining period you do you want to make it silent probably it is a synchronous system it is not a good idea to do that you let it read multiple times 16 times how does it matter I will get the same thing replicated 16 times. So, that is what is going to be done so do not keep it silent here. So, read it 16 times faster just keep the frame synchronization and you will get the same thing repeated 16 times in this super frame once I am able to do this job then I can build up the whole structure. So, I am just quickly drawing that so this is a frame hold buffer. So, this is now a repeated 16 times repeated actually frame after time compression this is a time compression which is done here. So, this is a dual memory system so I have not written the diagram explicitly I think you can do it as an assignment and if you can get if you get stuck let me know I will just then probably build up a write up on that and submit or anyone of you who finishes it first he can scan it and upload it on our LMS system and I will publish it for the remaining period. So, that is doable I leave it to you this much creativity I think should be possible I can expect. So, this one is going to have a clock rate which is going to be so I have to generate 0 to 31 counter it is a 5 bit counter which will be generated this will also be remember that 5 bit counter is counting 0, 1, 2, 3 in 125 microsecond and here this also has to go to frame hold buffer. The way I am compressing this I have to now generate a count from 0, 1, 2, 3, 31 0, 1, 2, 3, 31 16 times in 125 microsecond. So, that will again be done this is known as time slot hold buffer. So, both are functionality by same they are 16 such elements which will be created and what you can do is I can do an ending. So, remember this is a 8 bit bus and for this also I can create an ending. So, for the first one this input will only be enabled in the first 1 by 16th period of 125 microsecond for the second input in the second part only this will be 1 this control which I am ending. So, for the first one I will time compress first 1 by 16th of second, second 1, second 1, third 1 and so on I simply add them wire ending I will create a super multiplex system I will get that actually. So, this is what is going to happen a wired end system then a speech memory out, but how this will be generated. So, both this will be coming from a decoder this will be counting on stream 1, 2, 3, 4, 5, 16 1, 2, 3, 4, 5, 16 this is what we call PCM stream counter. So, it will generate 4 bits and I will be using a decoder. So, when this value 0 the first one will be active and that particular 1 by 16th frame will be going to this wired end gate only one of them will be getting the input at any point of time when next one will come. So, next one's input will be going here to create super multiplex system. Now, speech memory requires not 5 bit address, but 9 bit address now. So, what you will do is whatever is this address coming in are 5 bits the 4 bits will be taken from this side combined together this will be going in MSB more significant bit side this will be going towards LSB because its rate of change is only 16 times it will change in 125 microsecond. This will change 32 times or 30 times in 1 by 16th of 125 microsecond. So, you will get a 9 bit thing and you will have a switch selector switch and all that option will be there and usually it will be again right cyclic and read a cyclic kind of configuration. You will have one control memory which will be now storing larger number of locations. So, depending on how many slots. So, this will be also giving out 9 those many locations are required it is a strictly non-blocking is equivalent of cross bar. So, again this requires similar kind of structure which was there earlier and on the inverse side again you will have similar kind of mechanisms to retrieve back the 16 streams. So, from any incoming port any slot I should be able to map any outgoing port any outgoing even frame or any outgoing port any slot. So, this mapping can be done this is super multiplex time super time multiplex switching structure. So, lot of things I have not covered here, but since I have done the basic time cell I actually request that all of you now should build up in detail this particular design. So, if there is going to be any issue then we will probably discuss this thing in more detail because my feeling is that we should be able to do it now. So, leaving it to you. So, with that I think we close today's lecture and we will actually look into TST and it is a control structure of TST in the next one and then we will move over to packet switching systems. Voice over IP I will be covering actually later on or do you want me to cover it first because I would like the packet switching to be done first and then ultimately the signaling and voice over IP framing formats everything will be done later on.