 Hello and welcome to this presentation of the STM32WB's Reset and Clock Control. The Reset and Clock Controller manages the various reset mechanisms and the generation of the system and peripheral clocks. STM32WB microcontrollers embed five internal oscillators, two oscillators for an external crystal or resonator, and two phase locked loops or PLLs. Many peripherals have their own kernel clock, independent of the system clock. The RCC provides high flexibility in the choice of clock sources, which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication baud rates, and also to keep certain peripherals active in low power mode. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages three types of resets, the system reset, the power reset, and the backup domain reset. The peripherals have individual reset control bits. Thanks to the Voltage's monitoring feature included into the power block or PWR, the filters embedded in the NRST pad and the RCC reset controller, the amount of external components is reduced to a single external capacitor connected to the NRST pin. The first type of reset is the system reset, which resets all the registers except certain registers with a reset and clock controller and power controller. It also does not reset the backup domain. Many sources can generate a system reset. An invalid voltage on the VDD or VFBS MPS supply, see PWR block for details. An invalid voltage on VDD due to brownout function. The brownout function allows the user to choose its own threshold levels for the VDD supply. See power block for details. An exit from standby or shutdown mode. A low level on the NRST pad. A timeout from the window watchdog. Software reset request initiated by the Cortex-M4 or Cortex-M0 plus core. Or a low power mode security reset, which is generated when stop, standby or shutdown mode is entered, but is prohibited by the option byte configuration. Note as well that the system reset, except when generated by a standby reset, asserts the NRST pad allowing the reset of external components when a system reset occurs. The reset source flag can be found in the reset and clock controller status register. The power on reset is the reset having the largest coverage. The power on reset resets all the logic located in the VDD and VFBS MPS domains except those in the backup domain powered by VBAT, which contains the RTC and the external low speed oscillator. Note that the power on reset also triggers the system reset, so the NRST pad is asserted during power on reset. The system reset resets most of the logic located in VDD domain except some resources located into the RCC and the PWR blocks. The backup domain is not affected by this reset. The backup domain reset resets the backup domain powered by VBAT, which contains the RTC and the external low speed oscillator. In addition, most peripherals have individual local reset control bits. The RCC offers a large choice of clock sources, which can be selected depending on low power, accuracy and performance requirements. STM32WB microcontrollers embed five internal RC oscillators. A high speed internal RC oscillator or HSI, which can work at 16 MHz. A low power internal RC oscillator or MSI, working at 100 kHz to 48 MHz. An accurate RC oscillator or HSI-48, working at 48 MHz. A low speed low power internal 32 kHz RC oscillator or LSI-1. And a low speed low drift internal 32 kHz RC oscillator or LSI-2, centered at about 37 kHz. STM32WB microcontrollers embed two oscillators for use with an external crystal or resonator. A high speed external 32 MHz oscillator or HSE with a clock security system. And a low speed external 32.768 kHz oscillator or LSE also with a clock security system. STM32WB microcontrollers also embed two phase locked loops, each with three independent outputs for clocking the CPUs and different peripherals at different frequencies. The high speed internal oscillator or HSI is a 16 MHz RC oscillator, which provides 1% accuracy and fast wake up times. The HSI is trimmed during production testing and can also be user trimmed. The HSI can be selected as clock at wake up from system stop and as the backup clock if an HSE failure is detected by the clock security system. The HSI is selected as system clock at wake up from standby mode. The HSI can remain powered when the system goes to stop mode in order to speed up the wake up time and used as a kernel clock by peripherals in stop mode. Some peripherals such as the I2Cs, USART, LPUART and LPTIMS can select the HSI as kernel clock. The HSI frequency can be trimmed versus HSE by using the MCO and TIM17 bits in capture mode. The low power internal oscillator or MSI is a multi-frequency RC oscillator in the 100 kHz to 48 MHz range which provides 3% accuracy and fast wake up times. The MSI is trimmed during production testing and can also be user trimmed. The MSI can be selected as clock at wake up from system stop. The MSI is selected as system clock after reset. Some peripherals such as the USB can use the MSI as kernel clock. The MSI frequency can be trimmed versus HSE by using the TIM17 bits in capture mode. The 48 MHz internal oscillator or HSI48 is a 48 MHz RC oscillator which provides 3.5% accuracy and fast wake up times. The HSI48 is trimmed during production testing and can also be user trimmed by using the clock recovery system. The HSI48 can be selected as clock for the USB and true random number generator kernel clock. The HSI48 frequency can be trimmed versus HSE by using the MCO and TIM17 bits in capture mode. The high-speed external oscillator or HSE provides a safe crystal system clock. The HSE supports a 32 MHz external crystal resonator. The frequency can be tuned to the required few one-tenth of PPM using on-chip capacitor trimming. Bias and current control tuning is also possible. A clock security system allows an automatic detection of HSE failure. In this case, a non-mascable interrupt is generated and a break input can be sent to timers in order to put critical applications such as motor control in a safe state. When an HSE failure is detected, the system clock is automatically switched to HSI or MSI so the application software does not stop in the case of crystal failure. The use of the high-speed external oscillator clock is mandatory when the radio is active. The high-speed external oscillator will automatically be managed in line with the radio activity. STM32WB microcontrollers embed two LSI oscillators. An ultra-low-power 32 kHz RC oscillator named LSI-1 and a low-drift 32 kHz RC oscillator named LSI-2. Both are available in all modes except shutdown and VBAT. One of the two 32 kHz RC oscillators can be selected as internal LSI clock. The LSI can be used to clock the RTC, LCD, low-power timers, and the independent watchdog. Only the LSI-2 can be selected for use by the radio system. The accuracy of the LSI-1 is plus or minus 1.6%, plus 1.5% over temperature and plus 0.2% over voltage. The LSI-1 consumption is typically 110 nanoamps. The initial frequency of the LSI-2 is between 22 and 44 kHz, with a stability of 125 parts per million per Celsius degree over temperature and voltage. The LSI-2 typically consumes 500 nanoamps. The LSI frequency can be trimmed versus HSE by using the TIM16 bits in capture mode. The 32.768 kHz low-speed external oscillator, or LSE, can be used with an external quartz or resonator or with an external clock source in bypass mode. The oscillator driving capability is programmable. Four modes are available, from ultra-low power mode with a consumption of only 250 nanoamps to high driving mode. A clock security system monitors failure of the LSI oscillator. In case of failure, the application can switch from the RTC clock to the selected LSI clock. The clock security system is functional in all modes except VBAT. It is also functional under reset. The LSE can be used to clock the radio system, the RTC, the LCD, the low-power timers, the USART, and low-power UART peripherals. The system clock can be derived from the HSI, MSI, HSE, or the PLL-RCLK output of the PLL system. The switch used to select the system clock is dynamic, meaning that it is possible to change the frequency on the fly according to application performance needs. The Cortex-M4 core, Cortex-M0 Plus radio system and the flash memory have their independent clock dividers allowing each of them to run on different frequencies. It is recommended to run the flash memory on the HCLK, shared at least at the same speed as the highest frequency selected for the Cortex-M4 and Cortex-M0 Plus cores. In addition, all the prescalers presented in the figure are dynamic, so they can be changed on the fly as well, making the frequency scaling operation very simple. To optimize power consumption at lower frequencies, the operating range can be changed or low-power run mode can be selected. In range 1, the clocks of the Cortex-M4 or HCLK and shared bus, HCLKS, must not exceed 64 MHz, and the Cortex-M0 Plus clock must not exceed 32 MHz. In range 2, the clocks of the Cortex-M4 or HCLK, shared bus, HCLKS, and the Cortex-M0 Plus must not exceed 16 MHz. In low-power run mode, the clocks of the Cortex-M4, HCLK, shared bus, HCLKS, and the Cortex-M0 Plus must not exceed 2 MHz. BLE operation requires an HCLK 2 clock frequency of at least 16 MHz and is not allowed in low-power run mode. The PLLs embedded into the STM32WB microcontroller provides a flexible way to generate the required frequency for the system or peripheral clocks. They offer a wide input frequency range from 4 to 16 MHz. The PLLs share the same clock source, HSE, HSI, or MSI, which can be pre-divided. The PLL VCO has a wide frequency range from 64 to a maximum of 344 MHz in range 1 and a maximum of 128 MHz in range 2. Both PLLs provide three different output clocks which are all derived from the PLL VCO frequency via post dividers, slash P, slash Q, and slash R. The PLL SIS is used to generate the system clock and SAI and USB kernel clocks. The PLL SAI is dedicated to generating kernel clocks for the SAI, ADC and USB peripherals. The multi-clock output is available on GPIO pin PA8 in run and stop modes and can select various high and low-speed clocks. A low-speed clock output is available on GPIO pin PA2 in run, stop and standby modes and can select various low-speed clocks. Some peripherals have a separate clock for the processor bus interface and the specific peripheral interface function. The bus clock is used to access the peripheral registers, whereas the kernel clock is used for the specific peripheral interface function. Having a separate bus clock and kernel clock allows the application to change the interconnect and processor working frequency without affecting the peripheral operation. For example, the USART kernel clock is used to generate the BOD rate for the serial interface communication and the bus clock for the register interface. The enabling of both the peripheral bus clock and kernel clock is controlled by the reset and clock controllers peripheral enable and sleep mode enable bits. When both bits are set to one, the peripheral is able to operate and transfer data in sleep mode. When HSI, LSI or LSE is selected as the kernel clock, the peripheral is able to operate and wake up the system from stop mode. In stop mode, the peripheral is not able to transfer data on the bus matrix, for example to memory. Refer to the specific peripheral training slides for more information. The USART and I2C1 are only available in stop 0 and stop 1 modes. CPU, bus matrix and peripheral clocks are gated according to the CPU operating mode, the peripheral allocation and the peripheral sleep mode enable bit. A peripheral is allocated to a CPU and the reset and clock controller peripheral enable bit belonging to the CPU is set. The peripheral and the associated bus matrix is clocked whenever the CPU is in C run mode. Before accessing a peripheral, it must be enabled by the CPU. When both CPUs need to access a peripheral, they must both enable the peripheral by the reset and clock controller peripheral enable bits belonging to the CPUs. A CPU is only clocked when in C run mode. Only allocated peripherals are clocked when the CPU is in C run or when the CPU is in C sleep when the peripheral sleep mode operation is enabled. A bus matrix will be clocked when a CPU or peripheral on the bus matrix is clocked. It is important to note that the reset and clock controller offer two register sets, allowing each peripheral to allocate or enable peripherals. A peripheral and the associated bus matrix will only be clocked when allocated by a CPU and the CPU is in C run mode or in C sleep mode when the CPU peripheral sleep mode enable bit for this peripheral is also set. Depending on the peripheral function, peripherals have a different behavior. Peripherals needed for the system to operate don't have enable bits and are all time allocated to both CPUs. The SRAM 1 and Quad SPI are dedicated to the CPU 1 and can't be allocated by the CPU 2. The radio peripherals can only be allocated by a CPU 2. All other peripherals can be allocated by both CPUs. Before accessing a peripheral, the CPU must allocate it. If a peripheral is shared by both CPUs, it must be allocated by both processors. It is up to the application to avoid peripheral access conflicts. A hardware semaphore IP exists to help manage accessing shared peripherals. The peripheral allocation allows you to dynamically configure a CPU subsystem and have only the peripherals used by the CPU being clocked. The CPU plus the peripherals allocated by this CPU and the associated bus matrixes are considered by the reset and clock controller as a CPU subsystem. To give a simple example, when the CPU 1 is active in run mode, the system peripherals, the CPU 1 peripherals and any allocated peripheral will run as well, including the shared bus matrix and the CPU 1 bus matrix. The radio system has its own subsystem, which consists of the BLE and IEEE 802.15.4 RF modules, the system peripherals, and both the shared bus matrix and radio bus matrix. This allows the radio system to transfer data to SRAM 2. The following table gives a simplified view of the system states versus subsystem states. When a subsystem is in C run or C sleep mode, its bus matrix is clocked. When a subsystem is in C stop mode, its bus matrix is stopped. The system only enters stop, standby, or shutdown mode when all subsystems are in C stop mode. For more details on system states, please refer to the power controller or PWR training slides. The radio system is capable of waking up autonomously from stop and standby modes and transferring data with the SRAM 2. The shared bus matrix clock either uses the currently running CIS clock when the system is already in run mode due to a CPU being active or uses the HSI clock. The clock for the radio system is automatically enabled by the radio system itself. The HSI is used during radio startup and the HSE during radio TX and RX communication. The reset and clock controller register bit stop wake-up clock must select the HSI as the wake-up clock source. The SMPS needs a clock to operate in SMPS mode. In bypass mode, no clock is needed. The clock to use and the frequency in SMPS mode can be selected between HSI, MSI and HSE via the reset and clock controller register bits, SMP-SSEL and SMP-SDIV. The SMP-S clock must be selected between 8 MHz and 2 MHz where a higher clock frequency allows a minimum supply noise and a lower frequency allows the lowest power consumption. When the radio system is active, the HSE is forced as SMPS clock in order for the SMPS artifacts to be synchronized with the carrier. When the system restarts, the clock system is reset. All high-speed clocks and PLLs are disabled except for the high-speed clock used to start up the system. LSI and LSE are still working if they were previously enabled. After power on and a system reset, the MSI clock is enabled as system clock. When waking up from stop mode, the system clock can be selected between MSI or HSI with reset and clock controller register bit, stop walk. When the SMPS mode or radio system are enabled, the HSI must be selected. In stop mode, the HSI clock may be kept active to allow its use as peripheral kernel clock. When using SMPS mode in stop zero mode, the HSI clock needs to be kept active and selected as SMPS clock. When waking up from standby mode, the HSI clock is enabled as system clock. When a CPU wakes up from C stop mode, while the system remained in run mode, the clock settings are maintained and the CPU will wake up with the same clock as when it entered C stop mode. The system wake up mode can be read from the power controller, stop and standby flags. Refer to power controller training slides for more information. The CPUC sleep mode does not affect the clock settings, but only plays on the CPU subsystem clock gating. This slide lists the reset and clock controller interrupts. The HSI and LSE clock security systems, the PLLs and all seven oscillator ready signals can generate and interrupt. In addition to this training, you may find the power control and interrupt controller training is useful.