 Hello and welcome to this presentation on the ULP Mark Peripheral Profile which measures the energy impact of common peripheral on deep sleep and highlights the benefits offered by the Low Power Background Autonomous Mode or LP BAM of the STM32 U5. Ultra Low Power or ULP is a major design challenge facing MCU today as many systems are battery powered especially in the IoT domain. ST Microelectronics deploys creative design techniques to reduce power consumption. The STM32 U5 series offers advanced power saving microcontrollers to meet the most demanding power versus performance requirements for smart applications. The Embedded Microprocessor Benchmark Consortium or EEMBC develops industry standard benchmarks for the hardware and software used in autonomous driving, mobile imaging, the Internet of Things, mobile devices and many other applications. The ULP subcommittee focuses on power and energy. Scores that are certified have undergone a rigorous analysis by the EEMBC Certification Lab. Certification is a benefit only available to members and guarantees that the score adheres to the official run rules for that benchmark. ST Measures certifies and publishes the scores of all STM32 families. Since the ULP Mark scores are an unbiased way to compare the performance of microcontrollers, developers increasingly rely on these scores rather than on metrics found in data sheets. In 2014, the ULP team introduced the ULP Mark Core Profile or CP for short. This benchmark runs an active workload for a period of time then goes to sleep. The energy measurement during the duty cycle reflects a real life test of embedded low power beyond a simple sleep count. The ULP Mark Peripheral Profile or PP for short launched in 2016 examines the energy cost of four peripherals. Real-time clock, pulse width modulation, analog to digital conversion and SPI communication. ULP Mark Core Mark or ULP Mark CM for short launched in 2019 measures the energy of the core mark in a consistent environment. It is EEMBC's first active power benchmark. For measuring the energy costs of neural net inference in embedded devices, EEMBC offers ULP Mark ML. ULP Mark PP focuses on the MCU's most commonly used peripherals like pulse width modulation, SPWM, analog to digital conversion, ADC, serial peripheral interface, SPI, and real-time clock, RTC. This benchmark defines 10 one-second activity slots, each with variable usage of ADC, SPI, PWM, RTC, allowing the MCU and peripherals to sleep after their activities have completed. The table gives an overview of the activity in each slot. As soon as the device finishes the peripheral operation for that slot, it can enter standby or stop to mode. This means faster peripherals will most likely score higher since they can remain off longer. ULP Mark has been redesigned since its first release in 2014. It now works with the EEMBC benchmark framework. The same one used by IoT Mark and Secure Mark with a super-thin API that enables any MCU to execute next-generation EEMBC benchmarks. In slot 1, there is one processor wake-up per sample, while in slot 2, there is a unique wake-up after 64 samples. Several peripherals support the autonomous mode, which allows it to be functional and perform DMA transfers in stop 0, stop 1, and stop 2 modes. In addition, the low-power background autonomous mode, LPBAM, is supported in stop 2 mode, allowing to build more complex use cases with autonomous peripherals without any CPU wake-up thanks to DMA transfers. In this autonomous mode, the Cortex-M33 core and most of the peripherals can remain inactive. In stop 2 mode, the CPU domain is in retention, no dynamic activity is possible, while the smart-run domain, or SRD, is fully powered. SRD autonomous peripherals are functional thanks to the LPDMA and the SRAM4. The low-power timer can be used by STM32U5 to trigger a series of transfers performed by the LPDMA to periodically trigger events over a large period of time. The STM32U5 can use the repetition counter capability of the low-power timer instead of the real-time clock. RTC, low-power timers number 1, 3 and 4, ADC4, SPI3 and LPDMA belong to the SRD as-does SRAM4. With respect to the ULPMPP benchmark, STM32U5 can implement LPBAM in stop 2 mode as follows. ADC4 with LPDMA in slot 3, SPI3 with LPDMA in slots 4, 5, 6, 7 and 8, PWM in slot 9. The MSI-K oscillator present in STM32U5 generates a clock that is independent of the system clock and therefore convenient for peripherals that require a fixed clock while the system clock may be gated off. Now we will move on to a practical example of consumption measurement with the ULPMARK peripheral profile on an STM32U575. These values depend on the product. For other references of this series, please refer to documentation on the concerned product. This slide details the consumptions in the 10-1 second activity slots of the ULPMARKPP benchmark. The STM32U power consumption calculator is used to provide these metrics. The microcontroller is in run mode at the beginning of each slot to initialize the peripherals which are active in the current slot. Once initialized, the peripherals collaborate to perform background tasks while the microcontroller is in stop 2 mode. The consumption is approximately 4 microamperes in stop 2. In slots 1, 2, 3, 9 and 10, standby mode is entered which decreases the power consumption down to 1 microampere because the microcontroller is completely idle at the end of the slot. This table indicates the scores of various microcontrollers. STM32U575, STM32L412, STM32L552 from ST Microelectronics, SAML11 from Microchip, R5F from RENASAS, Apollo 2 from Ambic Micro, The four first rows provide general information about the microcontroller, processor core, size of the flash memory, size of the SRAM, maximum frequency. The fifth row indicates the consumption when stop mode is active with RTC enabled. The sixth, seventh and eighth rows indicate whether ADC conversions can occur while the microcontroller is in stop mode. The STMU575 supports the capability through LP BAM. The ninth row provides the ULP MarkPP score. All the STM32U575 is the microcontroller with the largest consumption in stop with RTC active mode. It occupies the fourth position in terms of ULP MarkPP due to the LP BAM mode and the use of the LP timer to trigger the conversions rather than using the RTC. This slide details the consumption during the second slot of the ULP MarkPP benchmark. The ADC acquires 64 samples at a frequency of 1 kHz and generates 40 PWM pulses at a frequency of 32 kHz with a duty cycle that increases gradually from 10 to 20%. The 64 samples acquired during the first slot are evaluated by software. LP BAM enables the ADC and PWM to remain active while the STM32U5 microcontroller is in stop to. LP DMA is used to transfer samples from ADC4 to SRAM4 and to transfer duty cycle values from SRAM4 to the LP timer. For STM32L412 and STM32L552, the core is asleep while the ADC and DMA remain active but all other peripherals are also active in low power sleep mode. As a result, the consumption is higher than that of STM32U5. For STM32L412, a wake-up of the Cortex-M4 core is required to update the duty cycle of the PWM. This slide details the consumption during the fourth slot of the ULP MarkPP benchmark. Results are expressed in microjoule units. 18.4 microjoule is the total energy of slot 4. 10.9 microjoule is the energy in stop 3 and 7.3 microjoule is the energy in standby. 10.9 plus 7.3 equals 18.2. The ADC acquires one sample at a frequency of 1 Hz, generates 100 PWM pulses at a frequency of 32 kHz with a fixed duty cycle of 40% and transmits 128 bytes on the SPI interface. For STM32U5, all these operations can be performed in stop 2 mode by implementing the LP BAM. The SPI controller number 3 belongs to the smart run domain. For STM32L412, transmitting data on SPI can be performed in low power sleep mode but all peripherals remain active, not just DMA and the SPI controllers. Both microcontrollers support the generation of PWM pulses at a fixed duty cycle in stop 2 mode. This slide details the consumption during the ninth slot of the ULP MarkPP benchmark. The ADC acquires one sample at a frequency of 1 Hz, generates 30 PWM pulses at a frequency of 1 MHz with a duty cycle that increases gradually and transmits 128 bytes on the SPI interface while checking the 128 bytes received in slot number 8. The consumption of the PWM in this sequence is more than 7 times lower with STM32U5 compared to STM32L412 due to LP BAM which enables the duty cycle to be updated while the microcontroller is in stop 2 state. The typical use case of using the ADC in a power sensitive system consists in acquiring samples in stop 2 mode and using an event to wake up the CPU that will process these samples. In order to compare the performance of STM32U575 and STM32L552, two tests are performed on STM32U575, one with LP BAM and the other without LP BAM, based on the sleep and run modes. Multiple frequencies were tested, the clock source being the multiple speed internal oscillator system, MSIS and kernel MSIK. The results of these tests are described in the next slide. It is interesting to study the impact of the SMIS and MSIK frequencies on the overall consumption when LP BAM is active and when the legacy sleep run approach is used. When LP BAM is implemented, the variation of consumption is 6.5% when the frequency of MSIS and MSIK varies respectively from 100 kHz to 4 MHz and from 100 kHz to 1 MHz. This demonstrates that the frequency of the oscillator has minor impact on the consumption when LP BAM is used because peripherals with the LP BAM capability can switch on MSIS or MSIK for transferring data. During idle time, the oscillator is switched off. When the sleep and run approach is used, based on the processor wake-up, each time a sample is acquired, the consumption has an important relationship with the frequency of the oscillator. The reason is that all peripherals remain active in sleep mode, not just the ADC. In this case, the consumption is more than doubled when the frequency of MSIS and MSIK varies respectively from 100 kHz to 4 MHz and from 100 kHz to 1 MHz. Testing the power consumption when a temperature acquisition is performed with a sensor connected to Y-square C is a second important use case for low power performance analysis. The low power timer is used to trigger the Y-square C read operation. Two different power modes are tested with LP BAM and stop-to mode with a sleep and run approach also supported by STM32L412. In the first case, the LP timer triggers the Y-square C read transaction and the LP DMA transfers the received data from the Y-square C received buffer to SRAM. Then an interrupt wake-ups the processor. In the second case, the LP timer wakes up the processor that transitions the system from stop-to to sleep mode. Then the DMA transfers the data received from the Y-square C to a buffer in SRAM. Finally, another interrupt wake-ups the processor that transitions the system back to stop-to. Several low power timer frequencies are tested. The results of these tests are described in the next slide. Let us first compare consumption when the LP TIM frequency is 6 Hz. STM32U575 with LP BAM consumes more than twice as much as STM32L412 in more than four times when sleep and stop-to modes are used when the LP TIM frequency is 60 Hz. STM32U575 with LP BAM consumes 15% less than STM32L412 but consumes more than twice as much as STM32L412 when sleep and stop-to modes are used when the LP TIM frequency is 600 Hz. STM32U575 with LP BAM consumes 61% less than STM32L412 but consumes 18% more than STM32L412 when sleep and stop-to modes are used. Therefore, the lower the period of the Y-square C read operation, the higher the score of the STM32U575 when LP BAM is active. When the traditional sleep and stop-to approach is implemented, STM32L412 offers a lower consumption even if the gap decreases when the frequency of Y-square C reads increases. In addition to this presentation, you can refer to the following presentations, pair management, reset and clock controller.