 Hello, and welcome to this presentation that describes the register file of GPDMA and LPDMA. The register file is composed of global registers applicable to all channels and channel-related registers. The channel-related registers are split into the channel-linked list register file that can be updated during a link and the other registers that are not affected by links. The registers CXTR3 and CXBR2 are only present in the GPDMA channels 12 to 15. Here's a brief description of the global registers. The SEC-CFGR and PRIV-CFGR registers configure the security and privilege attributes of each channel. The RC-FG-LOCKR register is used to lock the secure and privilege settings until the next reset. The MISR and SMISR are interrupt status registers for the non-secure and secure worlds. Here's a brief description of the channel-linked list register file. TR1, TR2, and TR3 are transfer configuration registers. BR1 and BR2 control the transfer at the block, respectively repeated block level, SAR, and DAR are the source and destination address registers. LLR controls the link operation. Here's a brief description of the other channel registers. L-BAR points to the 64 kilobyte area containing the LLI's. FCR is a flag-clear register, SR is a status register, CR is a control register. This figure describes the direct programming of the GPDMA channel without link list. When GPDMA, CXLLR equals 0, no link occurs. At the beginning, software initializes the channel by directly programming the channel-related registers. Then, software enables the channel. The DMA hardware checks the configuration and if an error is detected, the USEF flag is set and the channel is automatically disabled. When there are no configuration errors, the DMA proceeds with the transfer. If an error is encountered while the transfer is ongoing, the DTEF flag is set and the channel is automatically disabled. When no transfer error is detected, the transfer completes successfully and the transfer complete flag, or TCF, is set. Channel transfer completes when bits 15 to 0 of BNDT becomes equal to 0. This is the block number of data bytes to transfer from the source. For channels 12 to 15 of GPDMA, the channel transfer completes when both the block repeat counter and the block number of data bytes to transfer become equal to 0. A channel reconfiguration is possible only when the channel is disabled. Without link, software is in charge of reprogramming at least the source and or destination address to restart the same transfer. This table highlights the difference in terms of register file between the GPDMA and the LPDMA. The channel status register of the LPDMA has no FIFO level field because the LPDMA does not support channel FIFOs. The channel control register of the LPDMA has no field to select the AHB masterport used to perform the link transfer because it supports a unique masterport. Similarly, the transfer register 1 of the LPDMA has no field to select the AHB masterport used to perform the data transfer because it supports a unique masterport. Since the LPDMA channels do not include a FIFO, data manipulation such as byte reordering, packing and unpacking operations are not supported. Unlike the GPDMA, the LPDMA does not implement bursts, only block transfers. There is no field to select the hardware request from the destination peripheral in the LPDMA because it only supports requests from the source peripheral. Only the channels 12 to 15 of the GPDMA have the capability of repeating block transfers and adding a signed offset between consecutive bursts and blocks. These offsets are programmed in TR3 for the burst offset and BR2 for the burst offset only present for these channels. As a consequence, the user can decide to update these registers when a link is performed by programming the UT3 and UB2 control bits. In addition to this presentation, you can refer to the other presentations on the GPDMA and LPDMA, DMA overview, DMA transfers hardware and software views, Autonomous DMA and low power mode, DMA link list, DMA circular buffering and double buffering, DMA 2D addressing, DMA error reporting, DMA input output LLI control.