 if you could ask your question please. Sir, we have a question. It could be a currentian feedback amplifier also, but I need some amplifier design with independent AC current so. Let me give you a quick example. Consider this MOS example, this is a P channel transistor and I have some bias generated for it so that this will feed a fixed amount of current. Now, if I put an N channel transistor here and put my signal here assuming that V in is riding over some DC which is high enough to turn this transistor on. Now, because this is the current source the total amount of change in current here. So, suppose this is V out then the equivalent of this transistor can be taken to be like this and because this is the current source its impedance is infinite. As a result my output voltage will be V i times g m times r 0 and therefore, my gain will be g m times r 0. So, this is a simplest case in which we have got maximum possible gain because we are using a current source. I could have designed the same thing in a more familiar amplifier which is this and I put a resistor here and take the output from here. Notice that now the equivalent circuit will be g m r 0 this is the this is the lower transistor this one. However, in parallel with this will be the load transistor and therefore, in this case the gain will be g m times r 0 parallel r l which is always smaller than this. So, as a result by using a current source I can make a high voltage gain amplifier. This is just a quick example of how we can use current sources in actual amplifier over. Hello sir, I have one more question regarding MOS capacitor. So, the question is when we are giving positive voltage to the meter if the semiconductor is p type the holes will be repelled from the surface of the semiconductor. So, at a particular voltage inversion occurs in the in the semiconductor thereby the population of electrons and holes will reverse. How can we justify justify this phenomena? Well, you do not really have to justify this phenomenon this occurs, but just to get back to your question you probably what you want to know is what causes this phenomenon to occur. So, let me take that up as a question this is the metal in an MOS structure, this is the oxide and this is the semiconductor this is p type. If you recall the band structure which we had talked about is like this because k t by q l n p by n i is positive the Fermi potential is positive and therefore, Fermi energy is minus q times pi f which is negative with respect to the intrinsic level. This is how the semiconductor looks before you have applied the potential. Now, let us say this is the surface and this is the bulk the depth of the semiconductor that means this point is here and this is plotted versus depth. Now, when I apply a positive voltage the electrostatic potential will do something like this because the potential is positive you have applied a positive voltage to the metal. Therefore, this surface of the semiconductor will now acquire a positive potential the energy corresponding to that is therefore, minus q times this potential. Therefore, what we will get the as to the total energy of an electron will be this band bands will be bent downwards. This is the total energy this includes the original energy of the crystal and over and above this minus q times the electrostatic potential. Therefore, these bands will be bent downwards. Now, no current flow therefore, the Fermi level essentially remains wherever it was and now notice that in the bulk the Fermi level is close to the conduction band, but at the surface the Fermi level is close to the in the bulk it is close to the valence band and at the surface the Fermi level is close to the conduction band. What this implies is that there are many more electrons at the surface whereas, there are there is a huge number of holes in the bulk and this transitioning took place at this point. That means, initially when you had 0 voltage applied you had things like this. As you start applying the voltages the band start bending and E F I starts coming closer to E F. As the bands bent downwards this intrinsic Fermi level will come close to E F that means, the material is now becoming intrinsic. Once it becomes intrinsic it is no more P type. Now, whatever the electrostatic potential dictates you will get that kind of carrier. So, if you apply even more potential then you will get this state in which the bending is so much that the intrinsic Fermi level actually goes below E F and now this Fermi level is actually closer to the conduction band this is the conduction band. So, the conduction band has come much closer to E F than the valence band and that means, now energetically it is much more favorable for electrons to be here than for holes to be here. This is equivalent to saying that the holes have been repelled away and electrons are needed and at this point to ensure electrostatic balance. So, this is this is how we can explain the inversion over. Hello sir, this is concerning biasing of class AB amplifier. I think instead of two diode in series there is a problem that the we have connected vi to the only one of the transistor only one base of the transistor and there is no connection to the other base of transistor which I think is essential. Alternatively could you have two diodes in series from plus V cc to minus V cc and middle point of that is connected to base of the two transistors. I have drawn the circuit, please with that you just give me your opinion. Thank you over to you. Yeah, this is regarding the question, the diagram I gave nothing wrong about it, the same circuit is used in 740 and op amp and if you look at it carefully, the essence of biasing that class AB is to ensure that between the two bases of the PNP and the NPN, you have two diode drops. So, the purpose of I will just redraw it. So, this particular biasing circuit is very much used in op amps. So, there is nothing wrong about that, it is a very much working circuit. I will just redraw it again and the essentially what is being done is to create two diode drops. So, this is this is a circuit at draw, this is a very much correct circuit and it is used. So, basically what you should appreciate is the output is here at the two emitters. Now, between the two bases, you are essentially applying two diode drops, one diode drop is meant for the NPN, one for the PNP. So, this is very much correct and the input is supplied at the. So, mind you the important thing to remember here is that both of them are biased just before threshold. So, that when you apply a V I in the positive direction, the NPN will take over and the negative direction the second one will conduct. So, it is a working circuit, circuit which you draw will have its own problem. This circuit though simple, one of the biggest plus point of this is these in an IC, these diodes would be essentially made out of transistors and they have a good temperature point from the temperature point of view, the any changes in the voltage V B will be cancelled out because they all will change together. So, there will not be a thermal runaway, this is why this particular circuit is used. Just to add to what professor John said, I think that should be clear enough. In fact, the circuit that you have drawn will not work and let me just illustrate it by a numerical example. Let us say that VCC is 6 volts and you have biased it so that V 0 is around 3 volts. For both of these transistors to be on, this one is an NPN and therefore, you want this to be around 2.3 volts. However, this is a PNP and therefore, you want this base to be 3 volts minus 0.7. Sorry, the upper one should have been 3.7 and this one should be 2.3 volts, only then you have a forward bias here of 0.7 and a forward bias here of 0.7. That means, you want 3.7 volts here and 2.3 volts here, you want 1.4 volts between these two and that is possible only if there are two diodes here. In your circuit, you have shorted both bases. If you short both bases, then both of them will be at the same DC potential. As a result, if this whatever the voltage you choose, one of the emitter base junction is always going to be 0.7 volts into cutoff and will not be in class AB. So, the circuit that you have drawn will not work and therefore, you need this circuit. However, you had also raised a supplementary question saying one of the bases is in fact, not connected and that is also not correct. Consider the following. Let us draw a practical circuit without any sources and say this is the driver circuit and these are the two transistors. This is 6 volts, this is 3 volts and we want this to be at 3.7 and this to be at 2.3. Because this is 3.7, let us say that we are operating this at a bias of 1 milliamp. Because this we wanted 3.7 therefore, 2.3 volts drops across this and let us say therefore, we use 2.3 k here. Now, if there is a fluctuation of 0.1 milliamp here that means, if this guy drops 0.1 milliamp more then this voltage will drop by 0.1 milliamp into 2.3 k that means, 230 millivolts. So, this voltage will come down by 230 millivolts and so will this because this one remains 1.4 volts below that. Therefore, both bases will change their voltage by 0.23 volts or 230 millivolts. As a result both bases are being driven in this case even though the direct connection of this collector is to only one of the bases. So, therefore, this has only established the DC condition and any delta v that occurs here because the drop across these two diodes remains constant, the same delta v will occur here and as a result both transistors are driven and both are ready to be on depending on the direction of the signal. Should the signal become slightly negative then this guy would cut off and the lower one would turn on should it become even micro volts positive this guy would start conducting and this will be off. Therefore, the circuit originally given by professor Joseph John is correct and works as desired. Sir, in a Glitz circuit if I change the propagation delay for the NAND gate and inverter gate is 8 and 6. The example we have given by you know in that the NAND gate propagation delay is 6 and the inverter propagation delay is 8. So, interchange that delay propagation delay is any rule sir if I interchange 6 and 8 the first question. Second question the transistor level coding can I use VHDL or verilag the transistor level coding? Whether VHDL support or verilag support? Second question the third question give some open sources for the VLSF front end and back end over self. I hope I remember all your questions I will maybe answer them in arbitrary order. First of all those numbers were so taken so that there is only one transaction waiting at a given time. If you go through the tutorial which follows that one then you will see what happens if more than one transaction is waiting on that. So, if you follow that there is no rule there is no rule that the inverter should be slower than the NAND. In fact, it could be faster and you will still get the proper output. However, in this case there is a slight complication which I wanted to avoid while giving that tutorial and that was that at a given time there might be more than one transaction waiting on the same signal. If you follow through my second tutorial in that same lecture please download that file and look at the second tutorial. Then it tells you the rule depending on the type of delay. In short a later transaction for a different value on a node over writes the previous transaction. If you follow that rule then you will be able to simulate for the interchanged case as well. So, therefore, hardware is what it is there is no rule that the inverter cannot have a 6 unit delay and the NAND cannot have 8 unit delay. It just leads to an example which is more complicated and I wanted to give you a first tutorial on something which did not have those complications. So, I guess that is you will be able to do it. You had a question about transistor level god knows this question is asked from me at countless places and there is clearly some low quality text book which has propagated this myth. There is no reason why VHDL cannot simulate transistor level. There is no reason why only very long can do something and VHDL cannot. Both of them are full pledged hardware description languages. Whatever you can do in very long you can do in VHDL the level of convenience will be different. This question by the way and that is why I was smiling when this was put up has been asked to me at countless places and I am sure there is some book which I have not seen which has propagated this myth. The point is that for any hardware VHDL requires a model. The AND gate and the NAND gate and the transistors are not built in pieces of the hardware of the language. Very long has built in pieces for transistors and for gates. Therefore, you do not have to do anything additional in case of very long. If you want to simulate at gate level forget about transistor level but for transistors also it has got built in models. In VHDL there is no reason why you cannot simulate a transistor level. You will simply have to describe a model which describes the transistor. You have to do it rather than the language having to do it. That is indeed the big difference. There are no built in models in VHDL. There are built in models in very long. If the built in models are appropriate for your hardware, very long is convenient. Otherwise VHDL requires that you use libraries and the language itself like C. For example, C does not have built in things. You have to include libraries. Similarly, in VHDL you have to include libraries. If you have a library model of a transistor, you can in fact, yes, you can simulate at transistor level. I do not know what has propagated this myth. It is a force difference between VHDL and very long that VHDL cannot simulate at transistor level and very long can. That is wrong. The language it only requires an external model. VHDL can simulate at transistor level. If you give it an external model, if you define a model for the transistor. Hello. Sir, my question is regarding a biasing of transistors. When we bias a transistor, how do we decide that is when we are asked to decide on the values of R1, R2 and Rc for a particular region, whether it is active region, saturation, whatever it is, how do we decide the value of beta for a particular region. For example, given a transistor BC108, when we refer a data sheet, we will be given a beta minimum and beta maximum and besides that we will be given a beta typical value. How do you decide the value of beta to design a particular biasing circuit? We should restrict to beta minimum or beta maximum or the typical value of beta. Thank you, sir. Go over to you. Yes. Thanks for asking this question. See the, if you remember when we talked about common emitter amplifier, there were some thumb rules. Now, one of the purposes of biasing itself is to make sure that beta variation from one transistor to another transistor should not change anything. If you remember, when we talked about common emitter amplifier, we said two things. One thing we said was, we need to put a resistor Re, which is supposed to take care of thermal runaway and we choose the other thing was about regarding the choice of R 1 and R 2. We had mentioned that if your current, emitter current is I E, if you can ensure that the current through R 1 and R 2 is 0.1 or let us say 10 times base current or 0.1 is even better. By doing this, you are ensuring that any value of beta, even if it is 100 percent change, does not make much difference. So, what you said is a very valid point, but you could please try this. My suggestion would be, please take two transistors with two different betas and try it out and be convinced yourself. So, this is, there should not be any problem. This is why it is done, because what you said is a practical problem. You never get two transistors with the same beta, but these rules would ensure that this is taken care of. Now, one more thing regarding the choice of R 1 and R 2. Now, the first R 1 and R 2, another very important thing to remember here is these R 1 and R 2 would come in parallel in the AC equivalent circuit. So, remember that your input impedance is going to be affected by this. This would come in parallel with R pi. If you have a bypass capacitor, you would in the emitter, this would come in parallel with R pi. So, generally we will assume that the input impedance is R pi on the assumption that R 1, R 2 parallel is much greater than R pi. So, these are the considerations and that should take care. I hope your doubt is cleared. So, with Professor Jones permission, I will also chip in a little bit. I think reading between the words, I can understand what your doubt is. Your doubt is that we are saying that the current through this should be 10 times the base current and if we do not know the beta, how do we know the base current. So, let me take the exact question that you had asked. Let us say that we take a B C 108. Let us say that the beta has a range of 200 to 800 and let us quickly design a common emitter amplifier. This is the configuration that Professor Jones has given to you and I am going to choose values. So, that our calculation is easy. Let us say that the power supply is 6 volts. To have equal amount of head room on the positive side and negative side, we will say that we will use, we will bias this point to 3 volts. Very often this point is kept equidistant from V d d in ground so that you can go up as much as you can go down. So, let us say we have taken this as 1 milliamp. Because the current we have chosen as 1 milliamp and how did we decide it? Because if you look at the characteristics of beta versus current, it has an inverted u shape curve and you choose some value of some low value of current at which the beta remains maximum and that happens to be of the order of milliamp. So, we have chosen 1 milliamp as the current. Now, because 3 volts is dropping here 6 volts to 3 volts and 1 milliamp is the current therefore, this resistor is 3 K. Because we want freedom from thermal variation which changes about 26 milli electron volts per degree centigrade therefore, we want to keep this drop much larger than the amount of change that we expect in V B E. As a result, remember V B E changes about 2 milli volts per degree. So, over the temperature range may be it will change by 30, 40 milli volts. Therefore, we will say that we will keep this as 300 milli volts. So, 300 milli volts 1 milliamp directly gives you 300 ohms here and that means the DC voltage here is 0.3 volts. Assuming a 0.7 volts drop here that means this should be 1 volt. So, far no problem at all this is quite straight power. The next question is the doubt that you had that how do I know how much is the base current. So, what I do is that I take minimum beta to find the maximum base current. So, if the minimum beta is 200 then 1 milliamp divided by 200 gives me 5 microamp. If I make sure that the current through this is much larger let us say 100 microamp. 100 microamp means that the sum of these two resistors R 1 plus R 2 should be 60 volt and R 1 60 k and R 1 by R 2 should be 5. So, that 6 volts divides in the ratio of 5 volts to 1 volt. Now, if you know the sum and the ratio you can find out R 1 and R 2 independently. Now, you have designed this whole circuit should the beta become 800 rather than 200. The base current will only be less than 5 microamp. It will now be of the order of a couple of microamp and our original assumption that the current through the bias network is much larger than beta remains even for 800. Therefore, you can now take any old BC108 and put it in here with this design and it will work the same. The whole idea of a biasing circuit is that your design should be independent of the beta of the transistor as long as it is large enough and that is why we design the bias network in this particular way. There is not much to choose based on area. Let me just draw the two gates and then it will become clear. This is the north and this is the land. Notice that both have four transistors. However, because these two transistors are in series, they must be 2 x. These two are in parallel. Therefore, they can be their regular size. Here, these are in parallel and therefore, they are their regular size. On the other hand, these two are 2 x. So, in short, you have two 2 x transistors in both cases and two 1 x transistors in both cases. There is a slight penalty of area in case of in case of north because this x is larger than this x because the p channel transistor needs to be wider to carry the same amount of current. So, there is a small change in area. It is not identical, but it is not a big deal. On the other hand, as far as speed is concerned, these two transistors are in series and therefore, you can expect that the geometry will not fully compensate for the fact that this source is not quite at ground and therefore, the conductance of this will be slightly lower. As a result, the 1 to 0 transition in a NAND is a bit slower. Similarly, a 0 to 1 transition in case of a NOR is a bit slower. Overall speed is comparable. Therefore, you have to choose whether your significant edge is 1 to 0 or 0 to 1 and then based on that, you may choose NAND or NOR. Otherwise, there is not too much to choose between. Sir, in case of MOS capacitor, there is a term surface potential comes into existence. So, can you just explain what I mean by surface potential over to you, sir? This is in fact the diagram that I had drawn just sometime back, but I will just come back to it very quickly. Look at the electrostatics of the whole question. I am drawing the MOS capacitor turned by 90 degrees, so that it is horizontal. This is the metal. This is the oxide and this is the, let us take the p-type semiconductor that we had talked about. Now, I put a positive voltage here. Some voltage v has been put here. Now, the 0 is here at the back of the semiconductor. This voltage v has to divide itself between the semiconductor and the oxide. Now, inside the oxide, there are no charges. It is a clean oxide because del dot d is rho which is equal to 0. Therefore, there is no charge here inside here. Therefore, I will have a field which is constant because this is 0. The field is constant. This can be written as epsilon del dot e equal to 0 or therefore, e equal to constant because the field is constant. The voltage changes linearly inside the oxide. As a result, if I plot voltage, then at the metal, this is the applied voltage and it drops linearly over the oxide. This is the oxide. Now, here the charge density is non-zero. Therefore, I have to solve this equation and I do not have the time, but you get an exponential square law kind of a thing. You have solved it for p-n junctions and there you know that it is square law if you make the depletion approximation. So, in short, the potential here then drops in a square law kind of fashion and becomes 0 here. That means the potential here is somewhere between 0 and the applied voltage. The potential divides in a non-linear way. This is linear and this is non-linear. Now, given this, if you now draw the energy diagram, the original energy diagram was straight. This was p-type material, but now what I am saying is that over and above that energy and electron has an energy minus q times the electrostatic potential. As a result, the total energy will have the bands bent and this change from the original position of the band is minus q times the surface potential. Therefore, the surface potential is important. If this surface potential becomes more than the amount by which the intrinsic Fermi level is above Fermi level, then the two will cross over and inversion will happen. So, that is the important. If the surface potential is greater than equal to 2 phi f, then the material will become as n-type at the surface as it is p-type in the bulk because now it will be phi f below what was phi f above e f i. So, as a result, you have full inversion. So, that is why the surface potential is important and this is the basis. When you solve the electrostatic equation, that directly tells you that depending on the total charge in the silicon, a certain amount of potential must be there at the surface and therefore, a certain amount of band bending and that determines the charge. Over. As the amplifier can be used for audio-frequency amplification or hype can be used like that I heard in a magazine, I read in a magazine and can you tell me more explanation about where they are used and how they are like pulse width modulation technique that is the kind of just before the speaker. So, that these can be done just like that. Can you please more explain. Yeah, unlike class A, B and C which are analog amplifiers, class D make use of digital switches. So, I will just illustrate the fact. Suppose, you have a speaker here, and you drive it by a digital switch. The advantage of a digital switch is the following. Either the voltage, so you suppose we are talking of two switches here and they are complementary to each other, this is just like the C-boss inverter. Now, because it is a switch, when it is on, the voltage across it is 0 and when it is off, the current through is 0. As a result, there is no power dissipation in the switch itself. Therefore, it is very power efficient. However, the output will appear to be very distorted. What we do actually is that we drive it at a frequency which is orders of magnitude higher than the one at which this speaker can respond. That means, I drive it let us say at megahertz and now, the duty cycle of this megahertz signal and I can easily drive megahertz. After all, C-boss inverters work at gigahertz. So, I can definitely drive it at several megahertz. Now, if the duty cycle changes, then the average DC here will depend on the duty cycle. So, now what I make sure is that the average duty cycle follows the audio signal which is at very low frequency. So, when I drive it, in short, I am actually driving it like this and the envelope follows the, this is the signal and this is the modulation. Rather than doing amplitude modulation, what I am actually doing is duty cycle modulation. So, I have pulses which are very closely spaced here and far, far here and so on. So, the DC value here, as you can see that the average value here is high, but the average here value here is very low. So, even though, sorry, I should have drawn the constant amplitude here. So, the amplitude remains constant, but the duty cycle becomes low. Therefore, the DC here follows the duty cycle and the duty cycle is changed in accordance with the analog signal. So, now, I have the advantage that what this speaker will reproduce is only the low frequency component or the average DC at this point. Therefore, we will hear only the audio. On the other hand, we are driving it at a very high frequency and this can be very efficient because there is no power converted to heat in these switches. So, therefore, wherever power is very important and you have the capability of operating at a very high frequency, then class D amplifiers can be used. And many of these MP3 players and many of the modern audio amplifiers, in fact, use class D amplifiers like this. They are not analog in nature, they are digital in nature and the duty cycle of the pulse is varied in accordance with the low frequency signal. And therefore, the average DC at this particular point follows the audio signal and that is how we get the amplification over. We will stop here.