 Let us start with a brief review of last class. Last class we started looking at transistors. Transistors are three terminal two junction devices. We first started by looking at bipolar junction transistors BJT. So in the case of a PNP bipolar junction transistor, we had a N region which was your base through which the minority carriers which are your holes go as they go from the emitter to the collector. After BJT, we looked at a junction field effect transistor JFET. In the case of a JFET, we already had an N channel and the width of the channel was controlled by applying the voltage to the P regions. So this essentially forms the gate while we had a source and a drain and the current went from the source to the drain through the N channel. So a BJT is a current control device and then a JFET is a voltage control device. Towards the end of last class, we started looking at a metal oxide semiconductor field effect transistor. So in this particular case, the channel is not there initially when the device is in equilibrium but the channel is created by applying a bias. So we saw the example of a metal oxide semiconductor junction. In this case, we have a metal. We have a P-type semiconductor. So we apply a bias between these two. The metal is connected to positive and the P-type semiconductor is connected to negative. In this particular case, we have a positive charge on the metal side. Now there is a negative charge that extends through the P-type material not only at the surface but also some width within the junction, within the bulk. So we have two regions. We define one region that we called a depletion region. In the depletion region, the material is still a P-type but the concentration of holes is less than NA which is your acceptor concentration. And if you apply a further bias, we defined a region which is your inversion region in which case you have N greater than P. So that you have an N-channel that is created within your P-type material. So today, we will take up this further and look at a MOSFET. The first thing I am going to do is to draw the structure of a MOSFET device so that we can look at the IV characteristics. So let us look at the basic structure of a MOSFET. So I have my bulk semiconductor material. We will still keep it to be P-type. There is a metallization layer. So we can form electrical contacts and then there is an oxide layer on the surface. We have two regions within the MOSFET which are heavily N-type doped N plus. So these are called the source and the drain and we again make electrical connections to the source and the drain. So let me call them S and D so that they are your source and the drain. We also have a gate region through which you can apply a potential. So the two N plus regions form a junction with the P-type. So you have two PN junctions. Since N plus is heavily doped, most of the depletion region will be on the P-side. So this material where silicon, so you have P-type silicon and N-type silicon. Then the oxide will essentially be SiO2. The gate material can either be a metal or it can be polysilicon which is heavily doped so that it is conductive. So we are going to look at how a N channel is formed in this MOSFET and also the IV characteristics of this transistor. So let me start by looking at the working of the MOSFET. So I am going to redraw this figure but then I am also going to make electrical connections between the various terminals. So you have a source, gate and a drain terminal. So let me redraw. You are going to keep the MOSFET as the same. So you have a bulk P. I have two N plus regions. So I have my source and the drain and I have a gate. So let me just mark them as G and D. So how do we bias this MOSFET? So let me first bias the source and the gate. So in this particular case the gate is connected to a positive potential and the source is connected to a negative potential. We call this VGS. Then I will also bias the source and the drain. So the drain is connected to a positive potential with respect to the source. So we are going to apply a potential to the gate in such a way that holes will flow away from the gate towards the bulk of the P type and electrons will flow towards the oxide layer. So we have two depletion regions here. We are going to bias the material in such a way that holes will flow down and electrons will flow up but the potential is lower than the potential that is required for inversion. So VGS is less than V threshold. We saw earlier that V threshold is the potential for inversion. So in this particular case you are going to find that you will have a depletion region here. So let me just erase this and join the two depletion regions together. So we now have a depletion region but the material is still P type. So that electrons are still the minority carriers. So current I will be very small and it will be equal to your minority carriers flowing in a P type material. So it will be very similar to your reverse saturation current. So as we keep increasing the gate and source voltage, the depletion region is going to increase and ultimately when the voltage is above V threshold, we are going to form a channel between the source and the drain. So let me draw that next. So once again I have my MOSFET, my 2 N plus regions. I have a bulk P region and I have my gate. So I have my source, my gate and my drain. This is VGS, this is VDS. So now I am in a situation where I have the gate source voltage greater than V threshold so that I have an inversion region. So once again I have a depletion region between the 2 P and junction but now I am at a higher potential so that I have an N channel that forms between the 2 N plus regions. So this one is your N channel and the N channel forms because my gate source voltage is above V threshold. So now I can have electrons flowing from the source to the drain and the electron flows because we have a positive potential that is applied to the drain compared to the source. In the case of a MOSFET, you will not have current conduction when the voltage is below V threshold but above V threshold, we now have an N channel and we have conduction. Thus the gate source voltage essentially acts as a controlling parameter in order to control the current in the MOSFET and this essentially is the transistor action where the voltage between 2 terminals determines the current or the voltage between other 2 terminals. You can also say that this gate source voltage acts as a switch. So it helps to turn off or turn on your transistor. Now what happens as V DS increases? When V DS increases, V DS is the voltage between the drain and the source. So as V DS increases, if you look at the P N junction on the drain side, if you look at this P N junction, N plus is connected to positive, P is connected to negative so that this is reverse biased. So this essentially means the channel starts to get narrower as V DS increases and ultimately above a certain voltage, the channel just gets pinched off. If you were to draw that, so again I have my 2 N plus regions. I have my bulk P, my oxide layer and my gate source, gate and drain. So I have my gate source voltage above the threshold so that I have an N channel but when I start increasing V DS, the channel starts to narrow towards the drain region so that ultimately you have pinch off. To show this, you can show the N channel that is narrowing as we approach the drain region. So you have a depletion region that is surrounding it. Once pinch off occurs, the current is essentially a constant because the current is determined by the resistance of the N channel and as long as the pinch off width is small, it will not affect the total current. So in the case of a MOSFET, if we put all this information together, we can draw a current versus voltage characteristics. We will plot the current through the channel as a function of the drain source voltage for different values of V GS. So ID is the drain current. So this is the current that is flowing from the source to the drain as a function of V DS which is the voltage between the drain and the source. If the gate source voltage is below the threshold value, the current is very small. So this is a line that is very close to the axis. So this is as long as V GS is less than V threshold. So when V GS goes above V threshold, we are going to start to see an increase in current. Ultimately, there comes a point when pinch off occurs and the current becomes a constant. So this is for V GS equal to 5 volts which is greater than V threshold. Now if you keep increasing the value of V GS, then you are going to have a wider channel which means there will be more current but eventually there will be pinch off. So this is V GS equal to 8 volts. So this is the IV characteristics in the case of a MOSFET. The difference between this and the JFET where we saw earlier was there we would shrink the N channel by applying a potential to the gate. In this case, you increase the N channel by applying a potential to the gate. So let us now do some calculations in order to figure out the width of this depletion region and the inversion region and how that is related to the doping level in your bulk semiconductor. So we will again look at the metal oxide semiconductor junction and look more closely at the band picture and especially band bending. So let me again go back to my picture of the metal oxide semiconductor and I want to draw a band diagram for this. For simplicity, I am going to say that the work function of the metal is the same as the work function of the P type semiconductor. So instead of silicon, I will just say S so that is the most generalized argument but we will start with the work functions being the same. The advantage is that you say both work functions are the same. In the absence of any external potential, the Fermi levels will just line up. So on the left, I have my metal which has a Fermi level of EF. The dotted line represents my vacuum level so that phi m is the work function of the metal. I then have an oxide layer of some thickness D towards the end. We will see what role this oxide or more general an insulator plays. So we have an oxide layer and then I have a P type semiconductor, EFP. So this is a P type material. So the Fermi level is close to the valence band. It is EV and that is EC. So for the semiconductor, this will be my work function, call it psi PS and then this will be my electron affinity. So in this diagram, let me just drop the subscript P. So I will just call this psi S. So just saying psi m is equal to psi S but we know that we are starting with a P type material. So this metal oxide semiconductor can be biased and there are two ways of biasing it. In one particular way, if you connect the metal to a negative and the semiconductor to a positive, then you are injecting holes into the semiconductor and these holes will accumulate at the junction but that is not what we want. We want to bias in such a way that we are going to have holes moving away from the junction. So we have an N channel. So let us look at the metal oxide semiconductor under bias. So I am just drawing a schematic. We are going to bias this in such a way that the metal is connected to positive and the semiconductor is connected to negative, some voltage V. So if we were to draw the band diagram in this case, we are applying an external potential so that the Fermi levels no longer line up. This is my metal oxide and P type semiconductor. This is the work function of the semiconductor. This is the externally applied potential. So the Fermi levels shift by the applied potential far away from the junction. You still have a P type but as you go closer towards the junction, since you are moving electrons away, your material becomes more and more intrinsic in the depletion region and ultimately in the inversion region, you have an N type material. So you have band bending as you go towards the junction. So in this particular case, V is less than V threshold so that you can define a depletion region. If you have a situation where V is greater than V threshold, your bands have bent so much that towards or near the surface, you have inversion. So if you were to draw that again, so let me say metal oxide semiconductor, shall V, this is E of P. So far away from the junction, it still behaves like a P type. Now you have a depletion region but within the depletion region, there is another smaller region where N is more than P so that you have inversion. So this is what happens to the band diagram, the case of metal oxide semiconductor when we try to form an N channel. So let us look more closely at the semiconductor side so we can put in some of these potentials and use it to calculate the width of the depletion and the inversion regions. So we will look only at the semiconductor side of the junction. So this is my oxide layer, this is my P type semiconductor. So let me mark E of P. So E of P since it is P type will be closer to the valence band. This is EC and EV. In this diagram, let me also mark the intrinsic Fermi level E of I. Now the intrinsic Fermi level as we have seen earlier is very close to the center of the band gap. It is not exactly at the center because the effective masses of the electrons and holes are different but it is very close to the center. So we also have drawn E of I. The gap between E of I and E of P I am going to call phi B which is the bulk potential. So let me call this phi B, phi B is nothing but E of I minus E of P which is the bulk potential. So now we have applied a potential such that you have an inversion layer at the surface and you also have a depletion layer. So I will also draw E of I. So this is EC, EV and E of I. So in this case, we can also define a surface potential psi S. So I will call surface potential which is the difference between the intrinsic Fermi level in the bulk and the intrinsic Fermi level in the surface. So phi S is E of I at the surface minus E of I in the bulk. If I were to draw this, let me just draw a dotted line so that this is phi S. So we have a bulk potential, we have a surface potential. We can also define the potential at any distance x from the surface. So in this particular case, the surface is taken as 0 and x is the distance as we go into the material. So phi as a function of x is nothing but psi S minus x over Wd where Wd is the width of the depletion region. So Wd is the width of the depletion region. So x is defined from the surface so that when x is 0, psi of x is just the surface potential and when x is equal to Wd, x is equal to 0. So Wd represents the start of the band bending because it is a measure of how much your intrinsic Fermi level has shifted because of band bending. So let us now relate these potentials to the concentration of electrons and holes in the semiconductor. So within the bulk of the semiconductor, p is equal to Na which is your acceptor concentration n will just be ni square over Na. We can also relate the position of p the position of the Fermi level to p and if you were to do that, p is nothing but ni exponential is ni exponential minus Efp minus Efi over kT. So this we have seen before. Efp minus Efi is nothing but the bulk potential. So this is ni exponential minus phi b over kT or actually this should be plus phi b because it is minus Efp minus Efi which is minus phi b. So it is plus phi b over kT. Same way at the surface, we can also define a concentration of electrons and holes. So if you were to do that ns, so this is the concentration of electrons at the surface. It is again related to the position of the Fermi level. So ni exponential and this we can simplify to include the surface potential and the bulk potential. So it is exponential phi s minus phi b over kT. So that it is the difference between the surface potential and the bulk potential or in other words how much the Fermi level has shifted with respect to the intrinsic Fermi level. Ps, we can just calculate from ni square and the same way here n, I can calculate from just p. This value of phi s depends upon the concentration of acceptors within the bulk p type material. So we can relate phi s to the bulk concentration and also the width of the depletion region. If we do that phi s is just related to NaE square Wd square by 2 epsilon naught epsilon naught r. So this we can get by assuming a certain distribution of electric charge within the depletion region and thus calculating the electric field and linking that to the potential. So we have done a calculation for this when we looked at the p in junction. So the argument here is also similar. So we can relate phi s which is the surface potential to Na which is the concentration of acceptors within your p type semiconductor and also Wd which is the width of the depletion region. In the case of a MOSFET, we have inversion so that we have an n channel that is created. We define a condition called strong inversion. In the case of strong inversion, we create an n channel where the concentration of holes, I am sorry the concentration of electrons is equal to Na. So that we create a channel that is as strongly n type as the bulk material is p type. So when we have strong inversion and n is equal to Na, psi s will be just twice the bulk potential. So this we can understand because phi B is the location of the Fermi level with respect to the intrinsic Fermi level. In the case of p type, this Fermi level is located below EFI and now if I make it n type, the Fermi level goes above EFI and when n is equal to Na, the distance of the Fermi level from the intrinsic will be the same. So it starts phi B below EFI and when it becomes n type, it becomes phi B above EFI so that the total potential is just 2 times phi B. So this is a particular case of inversion and it is called strong inversion. So we will equate this in order to calculate the width at strong inversion. So we have a case of strong inversion where phi s is 2 times phi B. This in turn is related to the concentration of the acceptors non Na over Ni. We also saw an expression relating phi to the width of the depletion region. So let Wm be the width of the depletion region in strong inversion. So in this particular case, 2 kT ln of Na over Ni is related to Na P square Wm over 2 cilon naught r where epsilon naught r is the relative permittivity of your semiconductor. Can rearrange this to get the width of the depletion region that is just 2 square root of epsilon naught cilon r kT over E square Na ln of Na over Ni. So this equation gives the width of the depletion region. So the total width when we have strong inversion and this is related to the concentration of acceptors within the material. We also wanted to find the width of the inversion region. The depletion region is both the inversion and the other region where we have P greater than N but less than Na. In order to do that, we start with this expression psi of x minus x and now I am looking at a condition of strong inversion. So I will put Wm whole square. We will define the inversion region as where psi of x is equal to psi b. Remember the surface potential is 2 times psi b. So we can put this values here and simplify to get x equal to 2 minus 1 divided by root 2 times Wm. So we can calculate both the total width of the depletion region which is given by this formula and the width of the inversion region. Let us actually substitute some values in order to get a sense of these numbers. So I have a P type semiconductor. I am going to take silicon with Na to be 10 to the 17th per centimeter cube. We can first calculate the bulk potential which is the difference between the Fermi level in the intrinsic material and the Fermi level in your P type. That is nothing but kT ln of Na over Ni. If you have silicon, we know that Ni is 10 to the 10. So that this gives you a value of 0.417 electron volts and this is below EFI. So we now want to create an N channel in this P type material and we want to make it a strong inversion so that the material is as much N type as the bulk is P type. In order to do that we need to have a surface potential psi s. There is 2 times psi B. This is nothing but 0.834 electron volts. We also wrote down an expression for the total width of the depletion region. So we can substitute the values here and that gives psi M to be 100 nanometers. So this represents the total width of the depletion region. If you want to calculate the width of the inversion region which is x, this one is approximately 30 nanometers. So this one which is 100 nanometers which is Wm is the total width of the depletion region. Within this depletion region you have an N channel which is your inversion region which is approximately 30 nanometers wide. If you increase the value of Na, so you make your material more P type, the total width of the depletion region will reduce correspondingly the width of the channel will also reduce. So one last thing before we look or before we end the MOSFETs, the oxide layer in the case of a MOSFET acts as an insulator. So we can define a capacitance for the oxide layer or for the MOSFET and the capacitance is nothing but epsilon naught, epsilon naught oxide times area divided by the thickness of the oxide layer. In the case of the IC industry silicon is your material of choice for the MOSFET. So the oxide layer that is used is always SiO2 and SiO2 has a relative permittivity of 3.9. Now as the dimensions of the transistor start to come down, so this is your scaling where you have more transistors that are packed within a given IC. As the dimension starts to come down, the dimensions of all the other components of your transistor will also have to come down. So as the thickness reduces, your capacitance will increase but if your thickness becomes too small, the oxide layer is very thin so that you can have tunneling between the made metal layer which is your gate and the end channel and this will affect the properties of the channel. In order to prevent that, the oxide layer is replaced by other high-cade dielectric materials. So you can still have a reasonable thickness while at the same time having a higher capacitance. So we replace the silicon die oxide with other materials with a higher epsilon naught R. So some of the other materials that are used is silicon nitride with a relative permittivity of 7 but metal oxides are also used. So tantalum oxide is 25, titanium dioxide is anywhere from 60 to 100. So in the recent IC industry, we replace the metal oxide semiconductor with an insulator that has a high dielectric value. With this we are done with the MOSFET part of the course and the transistors as well. Next, we will start to look at what happens when light interacts with your semiconductors. So we are going to look at optoelectronic devices like LEDs and solar cells but before we do that, we will first treat the general interaction of light with semiconductors.