 Hello everyone, myself Sanjay Udge, assistant professor, department of electronics engineering, Walsh Chandra Institute of Technology, Solapur. Today we are going to discuss synchronous counter. Learning outcomes. At the end of this session, students will be able to design different synchronous counters. Outline, introduction to counters, synchronous up counters, synchronous down counters, question, answer, design of counter references. In the earlier session, we discussed the asynchronous counters. The advantage of asynchronous counter is simplicity in the logic circuit, but that creates accounting delay. This limits the speed of operation of this asynchronous counter because of the introduction of repulse. Since, in synchronous counters, all the flip-flops are clocked simultaneously. It means that the flip-flops in the counter are having a clock signal simultaneously, but they require additional logic circuitry. The drawback of this asynchronous counter, that is, the speed of operation is removed by providing a clock signal simultaneously to all flip-flops. And the circuit is called as a synchronous counters. Types of synchronous counters. Classified depending upon the way in which counter advances its count. Up counters. Start to count from decimal 0, that is, binary 0000 and increment or count upward towards decimal 15, that is 1111 in binary. For 4-bit counters, that is, up to maximum count. Down counters. Start to count from decimal 15, that is, maximum count, binary 1111 and decrement or count downwards to decimal 0 or binary 0000. This is the synchronous up counter. It's a 3-bit synchronous counter. 3-bit synchronous counter uses 3 flip-flops, ff0, ff1, ff2. The inputs to these flip-flops are j0, k0, j1, k1, j2, k2. And the outputs are q0, q1 and q2. Remember here, being a synchronous counter, the clock signal is simultaneously connected to all the flip-flops. Here, j0, k0 input is connected permanently to logic 1, that is, high. It will act as a t-flip-flop, so output should toggle at around the every clock pulse. So, q0 output of first flip-flop is given as an input to the second flip-flop, whereas q0 and q1 output, these are ANDed together and given as an input to the third flip-flop. Here, if you look at this timing diagrams, this q0 output will toggle at the leading edge of the every clock cycle, whereas q1 will toggle or it will change its state only when the q0 output changes its state from 1 to 0, whereas this q2 output will change when both q0 and q1 changes their states from 1 to 0. This is the summary of operation. So, initially when the counter is recited, so the outputs are 0, 0, 0, decimal, 0. Then, at the arrival of the every clock pulse, the counter will advance to 0, 0, 1. Then 0, 1, 0. 0, 1, 1. 1, 0, 0. 1, 0, 1. 1, 1, 1, 0. And finally, 1, 1, 1. Going back over here, now when q0, q1 and q2, they are 1, 1, 1, that is the last count, maximum count. At the arrival of the next clock pulse, what happens? This q0 will toggle to 0. Next, q1 will also toggle to 0 and q2 will also toggle to 0 because q1, since q0 earlier, in the earlier state, q0 of 1, so q1 will change to 0. In similar manner, q2 will also toggle from 1 to 0, since this J3, it was 1. So, after 1, 1, 1, the next count will be 0, 0, 0. That is the counter will be recited. This is the 4-bit synchronous up counter. The only difference in the 3-bit and the 4-bit is it uses one more flip-flop, that is the fourth flip-flop. Again, this is flip-flop, A, B, C, D. Outputs are A, B, C, D. Again, clock signal is given simultaneously to all four flip-flops. Output of the first is given as input to the second. Then output of the first and second and it together to give input to the third flip-flop. Again, the outputs of one, that is A, B, C, R and it together and they are given as input to the fourth flip-flop. So, this is the timing diagram for the 4-bit synchronous up counter. Here again, flip-flop A will toggle at the arrival of every clock signal, that is leading edge of the clock signal. B will toggle when flip-flop A changes from state from 1 to 0. Similarly, third flip-flop C will change state when both A and B flip-flop changes from 1 to 0. And finally, flip-flop D, it will change its state only when a flip-flop A, B, C will change their states from 1 to 0. This is the down counter. It is a 4-bit down counter. There is a slight difference. In up counters, we were using Q0, Q1, Q2, Q3 or QA, QB, QC, QD outputs for the up counters. Here, the only difference is we are using QA bar, QB bar, QC bar and QD bar. We can give input to the next flip-flop. Here, AND gates are connected at the QA bar and QB bar and given as an input to the C flip-flop. Starting from the flip-flop A, QA output is directly connected to J, B and KB. Next, output of QA bar and QB bar they are added to weather to give the input as JC and KC. In similar manner, JD and KD will receive the input which is the ending of the previous flip-flop. QA bar, QB bar and QC bar these three outputs are added together and given as an input. Initially, when all these flip-flops are reset to 0, 0, 0 at the arrival of the first clock pulse since the first flip-flop is connected to logic 1, J1, K1, J, K. So, A will toggle, change to state 1. Here, earlier it was 1. So, this B will also 1, C and D will also 1. So, the initial count will be 1, 1, 1, 1 at the arrival of the first clock pulse. In the second clock pulse, this A will toggle to 0 while B, C, D will remain to 1, 1, 1. So, the count will be 1, 1, 1, 0. In similar manner, it will count down towards 0, 0, 0, 0. So, this is the working of the down counter. The only difference is we are using inverted outputs of all the flip-flops. That is QA bar, QB bar, QC bar and QD bar. Down counter, this is the second flip-flop second flip-flop FFB input is inverted output of the previous flip-flop. Whereas, next stage of flip-flops receives the inverted outputs of the previous flip-flop with some additional logic circuitry, that is the AND gate. Exercise assignment, how many numbers of flip-flops are required to design mod N counter? And the answer is, number of flip-flops required will be equals to log N upon log 2 where N is equal to number of states of counter. Design up counter. Find the number of flip-flops required. Write down the sequence in the tabular form. Determine the flip-flop inputs which must be present for the desired next state from the present state using the excitation table of the flip-flop. The excitation table consists of present state, next state and what should be the inputs? That is written on the right-hand side columns. Prepare K-map for flip-flop input in terms of flip-flop outputs as the input variables. Simplify the K-map and obtain the minimize the expression. Connect the circuit using flip-flop and other gates corresponding to the minimize the expressions. Design of three-bit counters. See, for three-bit counters, we need three flip-flops. ff0, ff1, ff2. And their inputs and outputs are given below. So ff0 will have input j0, k0, ff1, j1, k1, ff2, j2, k2 and their outputs are q0, q1, q2 respectively. This is the design of the transition table. So first of all, let us go through the excitation table. This is the first column, present state, second column, next state and to change from present state to next state, what should be the inputs? So 0, don't care, 1, don't care, 1 and don't care, 0. So this is what we are using over here. This qc, qb, qa, present state, this again qc, qb, qa, next state, whereas these are the inputs jc, kc, ja, then jb, kb and jk. For example, to change this qa to 1, we must need jk as 1 extra. Now qb, to change this, to remain it from 0 to 0, we will have 0, don't care. Again qc, 0 to 0, we are again using 0k. So again, next, we want to change a second row. We want to change qa from 1 to 0. We must have jkx1. In this way, let us prepare the different input conditions for the different present and the next state. So this is what the design of the transition table. After designing this transition table, we must prepare a Kmat to determine the input. What it requires? It requires the determination of the inputs j0, j1, j2, k0, k1, k2 by considering the outputs q2, q1 and q0 as variables and find out the pairs, cod and octet to get the Boolean expression. For j0, k0, we got a cod, so j0, k0 will be equals to 1. Here, in the middle tables for j1 and k1 maps, we got this cod, 1xx1, x1, 1x. So it is nothing but the q0. j1 equals to k0, k1 equals to q0. In the last left hand side to tables j2 and k2, we got this 1 and x, it is a pair. So it is q2, q0, q1. So j2 equals to q0, q1 and k2 equals to q0, q1. So this is what we got the inputs of flip-flops using Kmap and the design table. j0, k0 equals to 1, j1, k1 equals to k0, j2, k2 equals to q0, q1. And with this, we can able to implement the logic circuit with 3 flip-flops fs0, 1, 2 as input j0, k0, j1, k1, j2, k2 and this j0, k1 equals to high at logic 1, j1, k1 equals to q0 whereas j2, k2 equals to q0, q1. These are the references. Thank you.